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# Release Notes for STM32L1xx CMSIS Copyright © 2017 STMicroelectronics
## Update history ### V2.2.1 / 21-April-2017 Main Changes General updates: Updated CMSIS Device compliancy with MISRA C 2004 rules: MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type) U pdated system_stm32l1xx.h/.c files. Aligned Bit definitions for SCB_CFSR register to be compliant with CMSIS Core V4.x and V5.x. Renamed RTC_CR_BCK bits in RTC_CR register to RTC_CR_BKP, to be aligned with others series. Renamed GPIO_AFRL_AFRLx and GPIO_AFRL_AFRHx bit definitions (from GPIO_AFRL/AFRH registers) to GPIO_AFRL_AFSELx. ### V2.2.0 / 01-July-2016 Main Changes Add macros _Pos and _Msk for each constants. For instance: #define ADC_LTR_LT ((uint32_t)0x00000FFFU) Is now provided as: #define ADC_LTR_LT_Pos (0U) #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) #define ADC_LTR_LT ADC_LTR_LT_Msk IS_I2S_ALL_INSTANCE is now SPI2 and SPI3 instead of SPI1 and SPI2. Update the TIM_ARR_ARR and TIM_CNT_CNT as they support the 32 bit counter feature. Add macro IS_TIM_ETR_INSTANCE. Add RI_ASCR2_GR6_x with x = 1,2,3,4 if applicable. Add macro IS_SMBUS_ALL_INSTANCE. Set default value for SystemCoreClock to 2097000 instead of 32000000. Correct the presence of TIM9 for some devices inside various TIMER macros. ### V2.1.3 / 04-March-2016 Main Changes Add HardFault_IRQn. Add BKP5R to BKP19R for RTC_TypeDef for stm32l151xba. Align bits naming on all stm32 families (ex: WWDG_CFR_WDGTB0 -> WWDG_CFR_WDGTB_0). Rename RCC_CFGR_MCO_DIVx to RCC_CFGR_MCOPRE_DIVx Align Bits naming on all stm32 families (ex: EXTI_IMR_MR0 --> EXTI_IMR_IM0) Update .icf file to correct empty linker ROM Start/End menu, under IAR, for stm32l151xdx, stm32l152xdx and stm32l162xdx. Rename RCC_CFGR_MCO_x to RCC_CFGR_MCOSEL_x to be aligned with Reference Manual. Update CMSIS drivers to apply MISRA C 2004 rule 10.6. (Use U postfix) Add defines FLASHSIZE_BASE and UID_BASE ADC common instance standardization (new define ADC1_COMMON) Remove bit GPIO_BRR_BR_x from Cat1 to Cat2 devices Literals "ADC_SMPR1_SMP27, ADC_SMPR1_SMP28, ADC_SMPR1_SMP29" are available on Cat4, Cat5 only. Add DMA_CNDTR_NDT, DMA_CPAR_PA and DMA_CMAR_MA definitions present on other stm32 families. Add defines to trig feature inside source code based on CMSIS content: RTC_TAMPER1_SUPPORT RTC_TAMPER2_SUPPORT RTC_TAMPER3_SUPPORT RTC_BACKUP_SUPPORT RTC_WAKEUP_SUPPORT RTC_SMOOTHCALIB_SUPPORT RTC_SUBSECOND_SUPPORT. PWR_PVD_SUPPORT Set CMSIS variables PLLMulTable, AHBPrescTable and APBPrescTable as external in system_stm32l1xx.h. Bit 23 of all EXTI registers (IMR, EMR, ...) is not supported on Cat 1 & 2. Correct a wrong values for RI_ASCR1_CH_27 to RI_ASCR1_CH_30 Add defines for LCD capacitance Suppress SPI1 from I2S_ALL_INSTANCE ### V2.1.2 / 09-October-2015 Main Changes Removing the __IO attribute for PLLMulTable and AHBPrescTable. This was leading to issue during C++ initialisation. IDR field of CRC_TypeDef changed from uint32_t to uint8_t to comply with register structure. Added TIM10 and TIM11 to IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE). Renaming USB_CNTR_LP_MODE to USB_CNTR_LPMODE for naming consistancy with other bits. Renaming USB_ISTR_PMAOVRM to USB_ISTR_PMAOVR to use the name of the bit in this register. ### V2.1.1 / 31-March-2015 Main Changes Ensure compliancy w/ C++ Minor update on Timer assert. Adding IS_AES_ALL_INSTANCE macro for product with AES. ### V2.1.0 / 16-January-2015 Main Changes Add CMSIS files for new STM32L1 eXtended Devices : STM32L151xDX, STM32L152xDX & STM32L162xDX ### V2.0.0 / 05-September-2014 Main Changes Update based on STM32Cube specification This version has to be used only with STM32CubeF4 based development ### V1.3.1 / 06-March-2014 Main Changes stm32l1xx.h: update RAM functions attribute definition for GNU compiler ### V1.3.0 / 31-January-2014 Main Changes Add support for STM32L1xx XL-density devices "Ultra Low Power XL-density devices: STM32L151xExx, STM32L152xExx and STM32L162xExx" Add new startup file startup_stm32l1xx_xl.s for all toolchains stm32l1xx.h Add new macro STM32L1XX_XL for XL-density devices Update IRQn enumeration for STM32L1XX_XL GPIO BRR register is declared only for STM32L1XX_HD and STM32L1XX_XL devices All devices definition (i.e. STM32L1XX_xx) are commented out, user need to define the right STM32L1xx device in the toolchain compiler preprocessor Extend HSE_STARTUP_TIMEOUT and HSI_STARTUP_TIMEOUT values to 0x5000 ### V1.2.1 / 19-June-2013 Main Changes stm32l1xx.h Update RI_TypeDef structure by adding registers RI_ASMRx, RI_CMRx and RI_CICRx (x=1..5) Add bits definition for registers RI_ASMRx, RI_CMRx and RI_CICRx (x=1..5) ### V1.2.0 / 22-February-2013 Main Changes stm32l1xx.h List of supported devices: add reference to STM32L100xx Ultra Low Power Value Line devices Add SPRMOD bit definition in FLASH_OBR register Add RDERR bit definition in FLASH_SR register Rename FLASH_OBR_nRST_BFB2 to FLASH_OBR_BFB2 Delete FLASH_OBR_USER define (useless) ### V1.1.1 / 05-March-2012 Main Changes All source files: license disclaimer text update and add link to the License file on ST Internet. ### V1.1.0 / 24-January-2012 Main Changes Alpha version for STM32L1xx High-density and Medium-density Plus devices. Add support for STM32L1xx High-density and Medium-density Plus devices: Add new product define: "#define STM32L1XX_MDP" Add new product define: "#define STM32L1XX_HD" Change the library version to V1.1.0 Add new IRQ to support STM32L1XX_HD and STM32L1XX_MDP vector table Add new and update some Typedef to support new peripherals (AES, SDIO, OPAMP, FSMC, I2S) Add new peripherals address mapping Update bits definition Add new startup file "startup_stm32l1xx_mdp.s" for all toolchains Add new startup file "startup_stm32l1xx_hd.s" for all toolchains Change the RTC "CAL" register name to "CALR" Update registers bits definitions. ### V1.0.0 / 31-December-2010 Main Changes Created ## License Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 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