SET_FLAG MODE BATCH
SET_FLAG STANDALONE_MODE TRUE
SET_PREFERENCE ipi_mode no
SET_PREFERENCE is_ip_locked false
SET_PREFERENCE devicefamily artix7
SET_PREFERENCE device xc7a35ti
SET_PREFERENCE speedgrade -1L
SET_PREFERENCE package csg324
SET_PREFERENCE verilogsim false
SET_PREFERENCE vhdlsim true
SET_PREFERENCE designentry VHDL
SET_PREFERENCE outputdirectory /media/1TB/Dropbox/PipelineC/git/PipelineC/examples/arty/arty.srcs/sources_1/ip/ddr3_0/_tmp/
SET_PREFERENCE subworkingdirectory /media/1TB/Dropbox/PipelineC/git/PipelineC/examples/arty/arty.srcs/sources_1/ip/ddr3_0/_tmp/
SET_PREFERENCE flowvendor Other
SET_PREFERENCE tool vivado
SET_PREFERENCE compnamestatus 0
SET_PARAMETER component_name ddr3_0
SET_PARAMETER xml_input_file /media/1TB/Dropbox/PipelineC/git/PipelineC/examples/arty/arty.srcs/sources_1/ip/ddr3_0/mig_a.prj
SET_PARAMETER data_dir_path /media/1TB/Programs/Linux/Xilinx/Vivado/2019.2/data/ip/xilinx/mig_7series_v4_2
SET_CORE_NAME Memory Interface Generator (MIG 7 Series)
SET_CORE_VERSION 4.2
SET_CORE_VLNV xilinx.com:ip:mig_7series:4.2
SET_CORE_PATH /media/1TB/Programs/Linux/Xilinx/Vivado/2019.2/data/ip/xilinx/mig_7series_v4_2
SET_CORE_DATASHEET /media/1TB/Programs/Linux/Xilinx/Vivado/2019.2/data/ip/xilinx/mig_7series_v4_2/data/docs/ds176_7series_MIS.pdf
