<foedag>
=-=-=-=-=-=-=-=-=-=-=
=-= FOEDAG HELP   =-=
=-=-=-=-=-=-=-=-=-=-=
</foedag>
<openfpga>
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
=-= FOEDAG OpenFPGA HELP  =-=
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
</openfpga>
Command-line Options:
   --help           : This help
   --version        : Version
   --batch          : Tcl only, no GUI
   --replay <script>: Replay GUI test
   --script <script>: Execute a Tcl script
   --project <project file>: Open a project
   --compiler <name>: Compiler name {openfpga...}, default is a dummy compiler
   --mute           : Mutes stdout in batch mode
<openfpga>
   --verific        : Uses Verific parser
   --device <name>  : Overrides target_device command with the device name
</openfpga>

Tcl commands (Available in GUI or Batch console or Batch script):
---------------
--- General ---
---------------
   help                       : Help

---------------
--- Project ---
---------------
   create_design <name> ?clean? ?-type <project type>? : Creates a design with <name> name
     <project type>           : rtl (Default), gate-level
     clean                    : If project folder already exists, remove recursively folder content
   close_design               : Close current design
   open_project <file>        : Opens a project
   run_project <file>         : Opens and immediately runs the project
<openfpga>
   target_device <name>       : Targets a device with <name>
   device_file <file>         : Set file <file> with supported devices which replaces default file (device.xml)
   set_device_size XxY        : Device fabric size selection
</openfpga>
   add_design_file <file list> ?type?   ?-work <libName>?   ?-L <libName>? 
       <type>                 : -VHDL_1987, -VHDL_1993, -VHDL_2000, -VHDL_2008, -VHDL_2019, -V_1995, -V_2001, -SV_2005, -SV_2009, -SV_2012, -SV_2017, default auto-detect 
       -work <libName>        : Compiles the compilation unit into library <libName>, default is "work"
       -L <libName>           : Import the library <libName> needed to compile the compilation unit, default is "work"
   set_top_module <top> ?-work <libName>? : Sets the top-level design module/entity for synthesis
   add_include_path <paths>   : Specify paths for Verilog includes (Not applicable to VHDL)
   add_library_path <paths>   : Specify paths for libraries (Not applicable to VHDL)
   add_library_ext <ext>      : Spcify library extensions (Not applicable to VHDL)
   set_macro <name>=<value>   : As in -D<macro>=<value>
   read_netlist <file>        : Read a netlist (.blif/.eblif) instead of an RTL design (Skip Synthesis)
   constraint_file_policy <policy> : "vpr" for VPR mode or "SDCCompatible" for SDC-vpr compatibility mode (default), or "SDC" for standard SDC mode
   add_constraint_file <file> : Sets constraints file (SDC) filename and location
   add_simulation_file <file list> ?type?   ?-work <libName>?   ?-L <libName>? 
       <type>                 : -VHDL_1987, -VHDL_1993, -VHDL_2000, -VHDL_2008, -VHDL_2019, -V_1995, -V_2001, -SV_2005, -SV_2009, -SV_2012, -SV_2017, -C, -CPP 
       -work <libName>        : Compiles the compilation unit into library <libName>, default is "work"
       -L <libName>           : Import the library <libName> needed to compile the compilation unit, default is "work"
   clear_simulation_files     : Remove all simulation files
   script_path                : Returns the path of the Tcl script passed with --script
   architecture <vpr_file.xml> ?<openfpga_file.xml>?
                              : Uses the architecture file and optional openfpga arch file (For bitstream generation)
<openfpga>
   set_top_testbench <module> : Sets the top-level testbench module/entity for simulation
   verific_parser <on/off>    : Turns on/off Verific Parser
   custom_openfpga_script <file> : Uses a custom OpenFPGA templatized script
</openfpga>

--------------------
--- Design query ---
--------------------
   all_inputs                 : Return all input ports for the current design.
   all_outputs                : Return all output ports for the current design.
   get_ports <pattern>        : Return all ports for the current design that match a specified pattern. If pattern is empty, get_ports returns empty string.
       <pattern>              : Examples of supported patterns: {*}, {cl*}, {d[0]}, {clock}, {clock1 clock2}

-------------------
--- Constraints ---
-------------------
<openfpga>
   keep <signal list> OR all_signals : Keeps the list of signals or all signals through Synthesis unchanged (unoptimized in certain cases)
   message_severity <message_id> <ERROR/WARNING/INFO/IGNORE> : Upgrade/downgrade message severity
</openfpga>
   set_pin_loc <design_io_name> <device_io_name> ?<internal_pinname>?: Constraints pin location (Use in constraint.pin file)
   set_property mode <io_mode_name> <device_io_name> : Constraints pin mode (Use in constraint.pin file)

----------
--- IP ---
----------
   add_litex_ip_catalog <directory> : Browses directory for LiteX IP generators, adds the IP(s) to the IP Catalog
   ip_catalog ?<ip_name>?     : Lists all available IPs, and their parameters if <ip_name> is given 
   configure_ip <IP_NAME> -mod_name <name> -out_file <path-to-file> -version <ver_name> -P<param>="<value>"...
                              : Configures an IP <IP_NAME> and generates the corresponding file with module name
   ipgenerate ?clean?         : Generates all IP instances set by ip_configure
     clean                    : Deletes files generated from this task
   simulate_ip  <module name> : Simulate IP with module name <module name>
   ip_add_to_design <IP name> : Add IP <IP name> to the design. IP must be generated before

------------------
--- Simulation ---
------------------
   simulation_options <simulator> <phase> ?<level>? <options> : Sets the simulator specific options for the specified phase
                      <phase> : compilation, elaboration, simulation, extra_options
   simulate <level> ?<simulator>? ?clean? : Simulates the design and testbench
     <level>                  : rtl, gate, pnr, bitstream_bd, bitstream_fd
       rtl                    : RTL simulation,
       gate                   : post-synthesis simulation,
       pnr                    : post-pnr simulation,
       bitstream_bd           : Back-door bitstream simulation
       bitstream_fd           : Front-door bitstream simulation
     <simulator>              : verilator, vcs, questa, icarus, ghdl, xcelium
     clean                    : Deletes files generated from this task
   wave_*                     : All wave commands will launch a GTKWave process if one hasn't been launched already. Subsequent commands will be sent to the launched process
   wave_cmd ...               : Sends given tcl commands to GTKWave process. See GTKWave docs for gtkwave:: commands
   wave_open <filename>       : Load given file in current GTKWave process
   wave_refresh               : Reloads the current active wave file
   wave_show <signal>         : Add the given signal to the GTKWave window and highlight it
   wave_time <time>           : Set the primary marker to <time>. Time units can be specified, without a space. Ex: wave_time 100ps

-----------------
--- Synthesis ---
-----------------
   parser_type <type>         : Parser <type> in: verific, yosys, surelog, ghdl
   synth_options <option list>: Yosys Options
   analyze ?clean?            : Analyzes the RTL design, generates top-level, pin and hierarchy information
     clean                    : Deletes files generated from this task
   synthesize <optimization>  ?clean? : RTL Synthesis, optional opt. (area, delay, mixed)
     <optimization>           : area, delay, mixed
       area                   : Optimize for reduce resource area 
       delay                  : Optimize for performance
       mixed                  : Optimize for area and performance (default)
     clean                    : Deletes files generated from this task
<openfpga>
   set_limits <type> <int>    : Sets a user limit on object of type (dsp, bram), specify 0 to disable block inferrence
       dsp                    : Maximum number of usable DSPs
       bram                   : Maximum number of usable BRAMs
       carry_length           : Maximum carry length
   synthesis_type Yosys/QL/RS : Selects Synthesis type
   custom_synth_script <file> : Uses a custom Yosys templatized script
</openfpga>

---------------
--- Packing ---
---------------
   packing ?clean?            : Packing, clean removes related files
     clean                    : Deletes files generated from this task
<openfpga>
   pnr_netlist_lang <format>  : Chooses post-synthesis netlist format, (blif, eblif, edif, verilog, vhdl)
   packing_options <option list>: Packing options
     -clb_packing <directive> : Performance optimization flags (auto, dense, timing_driven)
       auto                   : CLB packing automatically determined (default)
       dense                  : Pack logic more densely into CLBs resulting in fewer utilized CLBs however may negatively impact timing
       timing_driven          : Pack logic to optimize timing
</openfpga>


-------------
--- Place ---
-------------
   pin_loc_assign_method <method>: Algortihm for automatic pin assignment (in_define_order, random, pin_constraint_disabled)
       in_define_order        : Port order pin assignment (default)
       random                 : Random pin assignment
       pin_constraint_disabled: No automatic pin assignment
   place ?clean?              : Placer
     clean                    : Deletes files generated from this task
   pnr_options <option list>  : PnR Options

-------------
--- Route ---
-------------
   route ?clean?              : Router
     clean                    : Deletes files generated from this task
<openfpga>
   set_channel_width <int>    : VPR Routing channel setting
</openfpga>

------------------------------
--- Static Timing Analysis ---
------------------------------
   sta ?clean? ?opensta?      : Statistical Timing Analysis
     clean                    : Deletes files generated from this task
     opensta                  : Use OpenSTA tool for timing analysis
     
------------------------------
--- Power Analysis -----------
------------------------------
   power ?clean?              : Statistical Power Analysis
     clean                    : Deletes files generated from this task

-----------------
--- Bitstream ---
-----------------
   bitstream ?force? ?clean? ?enable_simulation? ?write_xml? ?write_fabric_independent? ?pb_pin_fixup? : Bitstream generation
     clean                    : Deletes files generated from this task
<openfpga>
   bitstream_config_files -bitstream <bitstream_setting.xml> -sim <sim_setting.xml> -repack <repack_setting.xml> -key <fabric_key.xml>
                              : Uses alternate bitstream generation configuration files
</openfpga>

------------------
--- Programmer ---
------------------
   programmer <command>           : A programmer tool allows you to program and configure FPGA devices via JTAG 
     command                      : fpga_config, flash, fpga_status, list_device, list_cable, otp
     fpga_config -c <cable name/index> ?-d <device_index>? <bitstream_file> : Program the FPGA device via JTAG
       -c <cable_name/index>    : Specify the cable name or index
       -d <device_index>        : Specify the device index
       <bitstream_file>         : Bitstream file to program
     flash -c <cable name/index> ?-d <device_index>? ?-o <operations>? <bitstream_file> : Program the Flash via JTAG
       -c <cable_name/index>    : Specify the cable name or index
       -d <device_index>        : Specify the device index
       -o <operations>          : Specify the operations to perform on the flash (Valid operations: program)
       <bitstream_file>         : Bitstream file to program
     fpga_status -c <cable name/index> -d <device_index> : Query FPGA Configuration Done and Configuration IsError status for a specified device
       -c <cable_name/index>    : Specify the cable name or index
       -d <device_index>        : Specify the device index
       -v                       : Verbose mode. Display additional information of fpga_status output
     list_device ?-c <cable name/index>? ?-v?: List all available devices or specified cable devices
       -c <cable_name/index>    : Specify the cable name or index
       -v                       : Verbose mode. Display additional information of list_device output
     list_cable ?-v?            : List all connected USB programmer cables
       -v                       : Verbose mode. Display additional information of list_cable output
     otp -c <cable name/index> -d <device_index> ?-y? <bitstream_file> : Program the device OTP via JTAG. WARNING: OTP programming is not reversible once programmed successfully.
       -c <cable_name/index>    : Specify the cable name or index
       -d <device_index>        : Specify the device index
       -y                       : Indicate the consesus of the user to proceed with OTP programming.
       <bitstream_file>         : Bitstream file to program

-----------------------------------------------

--------------
--- Debug  ---
--------------
   diagnostic <type>          : Debug mode. Types: packer
   
-----------------------------------------------
