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config_bits.c
1
17/*
18© [2024] Microchip Technology Inc. and its subsidiaries.
19
20 Subject to your compliance with these terms, you may use Microchip
21 software and any derivatives exclusively with Microchip products.
22 You are responsible for complying with 3rd party license terms
23 applicable to your use of 3rd party software (including open source
24 software) that may accompany Microchip software. SOFTWARE IS ?AS IS.?
25 NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS
26 SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT,
27 MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
28 WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
29 INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY
30 KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
31 MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE
32 FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP?S
33 TOTAL LIABILITY ON ALL CLAIMS RELATED TO THE SOFTWARE WILL NOT
34 EXCEED AMOUNT OF FEES, IF ANY, YOU PAID DIRECTLY TO MICROCHIP FOR
35 THIS SOFTWARE.
36*/
37
38// Configuration bits: selected in the GUI
39
40// FSEC
41#pragma config BWRP = OFF //Boot Segment Write-Protect bit->Boot Segment may be written
42#pragma config BSS = DISABLED //Boot Segment Code-Protect Level bits->No Protection (other than BWRP)
43#pragma config BSEN = OFF //Boot Segment Control bit->No Boot Segment
44#pragma config GWRP = OFF //General Segment Write-Protect bit->General Segment may be written
45#pragma config GSS = DISABLED //General Segment Code-Protect Level bits->No Protection (other than GWRP)
46#pragma config CWRP = OFF //Configuration Segment Write-Protect bit->Configuration Segment may be written
47#pragma config CSS = DISABLED //Configuration Segment Code-Protect Level bits->No Protection (other than CWRP)
48#pragma config AIVTDIS = OFF //Alternate Interrupt Vector Table bit->Disabled AIVT
49
50// FBSLIM
51#pragma config BSLIM = 0x1fff //Boot Segment Flash Page Address Limit bits
52
53// FOSCSEL
54#pragma config FNOSC = FRC //Oscillator Source Selection->Internal Fast RC (FRC)
55#pragma config IESO = OFF //Two-speed Oscillator Start-up Enable bit->Start up with user-selected oscillator source
56
57// FOSC
58#pragma config POSCMD = NONE //Primary Oscillator Mode Select bits->Primary Oscillator disabled
59#pragma config OSCIOFNC = ON //OSC2 Pin Function bit->OSC2 is general purpose digital I/O pin
60#pragma config FCKSM = CSECMD //Clock Switching Mode bits->Clock switching is enabled,Fail-safe Clock Monitor is disabled
61#pragma config PLLKEN = ON //PLL Lock Status Control->PLL lock signal will be used to disable PLL clock output if lock is lost
62#pragma config XTCFG = G3 //XT Config->24-32 MHz crystals
63#pragma config XTBST = ENABLE //XT Boost->Boost the kick-start
64
65// FWDT
66#pragma config RWDTPS = PS2147483648 //Run Mode Watchdog Timer Post Scaler select bits->1:2147483648
67#pragma config RCLKSEL = LPRC //Watchdog Timer Clock Select bits->Always use LPRC
68#pragma config WINDIS = ON //Watchdog Timer Window Enable bit->Watchdog Timer in Non-Window mode
69#pragma config WDTWIN = WIN25 //Watchdog Timer Window Select bits->WDT Window is 25% of WDT period
70#pragma config SWDTPS = PS2147483648 //Sleep Mode Watchdog Timer Post Scaler select bits->1:2147483648
71#pragma config FWDTEN = ON_SW //Watchdog Timer Enable bit->WDT controlled via SW, use WDTCON.ON bit
72
73// FPOR
74#pragma config BISTDIS = DISABLED //Memory BIST Feature Disable->mBIST on reset feature disabled
75
76// FICD
77#pragma config ICS = PGD2 //ICD Communication Channel Select bits->Communicate on PGC2 and PGD2
78#pragma config JTAGEN = OFF //JTAG Enable bit->JTAG is disabled
79#pragma config NOBTSWP = DISABLED //BOOTSWP instruction disable bit->BOOTSWP instruction is disabled
80
81// FDMTIVTL
82#pragma config DMTIVTL = 0x0 //Dead Man Timer Interval low word
83
84// FDMTIVTH
85#pragma config DMTIVTH = 0x0 //Dead Man Timer Interval high word
86
87// FDMTCNTL
88#pragma config DMTCNTL = 0x0 //Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF)
89
90// FDMTCNTH
91#pragma config DMTCNTH = 0x0 //Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF)
92
93// FDMT
94#pragma config DMTDIS = OFF //Dead Man Timer Disable bit->Dead Man Timer is Disabled and can be enabled by software
95
96// FDEVOPT
97#pragma config ALTI2C1 = OFF //Alternate I2C1 Pin bit->I2C1 mapped to SDA1/SCL1 pins
98#pragma config ALTI2C2 = OFF //Alternate I2C2 Pin bit->I2C2 mapped to SDA2/SCL2 pins
99#pragma config ALTI2C3 = OFF //Alternate I2C3 Pin bit->I2C3 mapped to SDA3/SCL3 pins
100#pragma config SMBEN = SMBUS //SM Bus Enable->SMBus input threshold is enabled
101#pragma config SPI2PIN = PPS //SPI2 Pin Select bit->SPI2 uses I/O remap (PPS) pins
102
103// FALTREG
104#pragma config CTXT1 = IPL6 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits->Alternate Register set assigned to IPL level 6
105#pragma config CTXT2 = IPL5 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits->Alternate Register set assigned to IPL level 5
106#pragma config CTXT3 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits->Not Assigned
107#pragma config CTXT4 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits->Not Assigned
108
109// FBTSEQ
110#pragma config BSEQ = 0xfff //Relative value defining which partition will be active after device Reset; the partition containing a lower boot number will be active
111#pragma config IBSEQ = 0xfff //The one's complement of BSEQ; must be calculated by the user and written during device programming.
112
113// FBOOT
114#pragma config BTMODE = SINGLE //Device Boot Mode Configuration->Device is in Single Boot (legacy) mode
115