|  | Dual Active Bridge Development Board (Part-No. ) |
Content |  |  |  |  |  |

Loading...
Searching...
No Matches
can1.c
Go to the documentation of this file.
1
17/*
18© [2024] Microchip Technology Inc. and its subsidiaries.
19
20 Subject to your compliance with these terms, you may use Microchip
21 software and any derivatives exclusively with Microchip products.
22 You are responsible for complying with 3rd party license terms
23 applicable to your use of 3rd party software (including open source
24 software) that may accompany Microchip software. SOFTWARE IS ?AS IS.?
25 NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS
26 SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT,
27 MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
28 WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
29 INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY
30 KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
31 MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE
32 FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP?S
33 TOTAL LIABILITY ON ALL CLAIMS RELATED TO THE SOFTWARE WILL NOT
34 EXCEED AMOUNT OF FEES, IF ANY, YOU PAID DIRECTLY TO MICROCHIP FOR
35 THIS SOFTWARE.
36*/
37
38// Section: Included Files
39
40#include <string.h>
41#include "../can_types.h"
42#include "../can1.h"
43
44// CAN Bus FIFO Memory information
45#define CAN1_FIFO_ALLOCATE_RAM_SIZE 360U // CAN FIFO allocated ram size based on (number of FIFO x FIFO message Payload size x Message object DLC size)
46
47// CAN Bus receive FIFO Memory information
48#define CAN1_NUM_OF_RX_FIFO 2U // No of RX FIFO's configured
49#define CAN1_RX_FIFO_MSG_DATA 64U // CAN RX FIFO Message object data field size
50#define CAN_RX_FIFO_WORD_0 0
51#define CAN_RX_FIFO_WORD_1 1
52#define CAN_RX_FIFO_WORD_2 2
53#define CAN_RX_FIFO_WORD_4 4
54
55// CAN Bus Transmit FIFO Memory information
56#define CAN1_TX_MSG_SEND_REQ_BIT_POS 0x200U // CAN FIFO TX Message Send Request bit
57#define CAN1_TX_INC_FIFO_PTR_BIT_POS 0x100U // CAN FIFO Increment Head/Tail bit
58#define CAN_TX_FIFO_WORD_0 0
59#define CAN_TX_FIFO_WORD_1 1
60#define CAN_TX_FIFO_WORD_2 2
61#define CAN_TX_FIFO_WORD_4 4
62
63// CAN Message object arbitration field information
64#define CAN_MSG_OBJ_DLC_FIELD_SIZE 0xFU
65#define CAN_MSG_OBJ_ID_TYPE_FIELD_POS 0x10U
66#define CAN_MSG_OBJ_ID_TYPE_SHIFT_POS 0x4U
67#define CAN_MSG_OBJ_RTR_SHIFT_POS 0x5U
68#define CAN_MSG_OBJ_RTR_FIELD_POS 0x20U
69#define CAN_MSG_OBJ_FRAME_TYPE_FIELD_POS 0x20U
70#define CAN_MSG_OBJ_FRAME_TYPE_SHIFT_POS 0x5U
71#define CAN_MSG_OBJ_BRS_FIELD_POS 0x40U
72#define CAN_MSG_OBJ_BRS_SHIFT_POS 0x6U
73#define CAN_MSG_OBJ_FORMAT_TYPE_FIELD_POS 0x80U
74#define CAN_MSG_OBJ_FORMAT_TYPE_SHIFT_POS 0x7U
75#define CAN_STD_MSG_ID_MAX_SIZE 0x7FFU
76#define CAN_MSG_OBJ_SID_SHIFT_POS 0x12U
77#define CAN_EXT_MSG_ID_HIGH_MAX_SIZE 0x1FFFU
78#define CAN_EXT_MSG_ID_LOW_MAX_SIZE 0x1FU
79#define CAN_MSG_OBJ_EID_LOW_SHIFT_POS 0xBU
80#define CAN_MSG_OBJ_EID_HIGH_SHIFT_POS 0x5U
81
82// Section: Driver Interface
83 const struct CAN_INTERFACE CAN_FD1 = {
84 .Initialize = CAN1_Initialize,
85 .Deinitialize = CAN1_Deinitialize,
86 .OperationModeSet = CAN1_OperationModeSet,
87 .OperationModeGet = CAN1_OperationModeGet,
88 .IsBusOff = CAN1_IsBusOff,
89 .SleepMode = CAN1_Sleep,
90 .Transmit = CAN1_Transmit,
91 .TransmitFIFOStatusGet = CAN1_TransmitFIFOStatusGet,
92 .IsTxErrorActive = CAN1_IsTxErrorActive,
93 .IsTxErrorPassive = CAN1_IsTxErrorPassive,
94 .IsTxErrorWarning = CAN1_IsTxErrorWarning,
95 .Receive = CAN1_Receive,
96 .ReceiveMessageGet = CAN1_ReceiveMessageGet,
97 .IsRxErrorPassive = CAN1_IsRxErrorPassive,
98 .IsRxErrorWarning = CAN1_IsRxErrorWarning,
99 .IsRxErrorActive = CAN1_IsRxErrorActive,
100 .ReceivedMessageCountGet = CAN1_ReceivedMessageCountGet,
101 .RX_FIFO_StatusGet = CAN1_RX_FIFO_StatusGet,
102 .InvalidMessageCallbackRegister = &CAN1_InvalidMessageCallbackRegister,
103 .BusWakeUpActivityCallbackRegister = &CAN1_BusWakeUpActivityCallbackRegister,
104 .BusErrorCallbackRegister = &CAN1_BusErrorCallbackRegister,
105 .ModeChangeCallbackRegister = &CAN1_ModeChangeCallbackRegister,
106 .SystemErrorCallbackRegister = &CAN1_SystemErrorCallbackRegister,
107 .TxAttemptCallbackRegister = &CAN1_TxAttemptCallbackRegister,
108 .RxBufferOverFlowCallbackRegister = &CAN1_RxBufferOverFlowCallbackRegister,
109 .Tasks = CAN1_Tasks
110};
111
112// Section: Private Variable Definitions
113// Start CAN Message Memory Base Address
114static uint8_t __attribute__((aligned(4)))can1FifoMsg[CAN1_FIFO_ALLOCATE_RAM_SIZE];
115
116// CAN Default Callback Handler
117static void (*CAN1_InvalidMessageHandler)(void) = NULL;
118static void (*CAN1_BusWakeUpActivityHandler)(void) = NULL;
119static void (*CAN1_BusErrorHandler)(void) = NULL;
120static void (*CAN1_ModeChangeHandler)(void) = NULL;
121static void (*CAN1_SystemErrorHandler)(void) = NULL;
122static void (*CAN1_TxAttemptHandler)(void) = NULL;
123static void (*CAN1_RxBufferOverFlowHandler)(void) = NULL;
124
125// CAN Receive FIFO Message object data field
126static uint8_t rxMsgData[CAN1_RX_FIFO_MSG_DATA];
127
134struct CAN1_RX_FIFO_MSG
135{
136 const enum CAN1_RX_FIFO_CHANNELS channel;
137 uint8_t headCount;
138};
139
140 static volatile struct CAN1_RX_FIFO_MSG rxFIFOMsg[CAN1_NUM_OF_RX_FIFO] =
141{
142 // Receive FIFO, FIFO head count
143 {CAN1_FIFO_1, 0U},
144 {CAN1_FIFO_2, 0U},
145};
146
152 struct CAN1_FIFO_INFO
153{
154 uint8_t payloadSize;
155 uint8_t msgDeepSize;
156 uint16_t *address;
157};
158
159// Section: Private Function Definitions
160
166 static uint8_t CAN1_DlcToDataBytesGet(const enum CAN_DLC dlc)
167{
168 static const uint8_t dlcByteSize[] = {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 12U, 16U, 20U, 24U, 32U, 48U, 64U};
169 return dlcByteSize[dlc];
170}
171
179 static void CAN1_FIFO_InfoGet(const uint8_t fifoNum, volatile struct CAN1_FIFO_INFO *fifoInfo)
180{
181 switch (fifoNum)
182 {
183 case CAN1_TXQ:
184 fifoInfo->address = (uint16_t *) &C1TXQUAL;
185 fifoInfo->payloadSize = 64U;
186 fifoInfo->msgDeepSize = 3U;
187 break;
188
189 case CAN1_FIFO_1:
190 fifoInfo->address = (uint16_t *) &C1FIFOUA1L;
191 fifoInfo->payloadSize = 64U;
192 fifoInfo->msgDeepSize = 1U;
193 break;
194
195 case CAN1_FIFO_2:
196 fifoInfo->address = (uint16_t *) &C1FIFOUA2L;
197 fifoInfo->payloadSize = 64U;
198 fifoInfo->msgDeepSize = 1U;
199 break;
200
201 default:
202 fifoInfo->address = NULL;
203 fifoInfo->payloadSize = 0U;
204 fifoInfo->msgDeepSize = 0U;
205 break;
206 }
207}
208
214 static void CAN1_RX_FIFO_ResetInfo(void)
215{
216 uint8_t count;
217
218 for(count = 0; count < CAN1_NUM_OF_RX_FIFO; count++)
219 {
220 rxFIFOMsg[count].headCount = 0;
221 }
222}
223
229 static uint8_t CAN1_RxFifoSearch(uint8_t fifoNum)
230{
231
232 uint8_t rxFifoIndex;
233
234 // If the last entry in the array holds the value
235 if ((uint8_t)rxFIFOMsg[CAN1_NUM_OF_RX_FIFO - (uint8_t)1].channel == fifoNum)
236 {
237 rxFifoIndex = CAN1_NUM_OF_RX_FIFO - (uint8_t)1;
238 }
239 else
240 {
241 for (rxFifoIndex = 0; (uint8_t)rxFIFOMsg[rxFifoIndex].channel != fifoNum; rxFifoIndex++)
242 {
243
244 }
245 }
246
247 return rxFifoIndex;
248}
249
255 static void CAN1_RX_FIFO_OverflowStatusFlagClear(const enum CAN1_RX_FIFO_CHANNELS fifoNum)
256{
257 switch (fifoNum)
258 {
259 case CAN1_FIFO_1:
260 C1FIFOSTA1bits.RXOVIF = false;
261 break;
262
263 case CAN1_FIFO_2:
264 C1FIFOSTA2bits.RXOVIF = false;
265 break;
266
267 default:
268 break;
269 }
270}
271
277 static void CAN1_RX_FIFO_IncrementMsgPtr(const uint8_t fifoNum)
278{
279 switch (fifoNum)
280 {
281 case CAN1_FIFO_1:
282 C1FIFOCON1Lbits.UINC = 1; // Update the CAN1_FIFO_1 message pointer.
283 break;
284
285 case CAN1_FIFO_2:
286 C1FIFOCON2Lbits.UINC = 1; // Update the CAN1_FIFO_2 message pointer.
287 break;
288
289 default:
290 break;
291 }
292}
293
299 static uint16_t CAN1_RX_FIFO_MessageIndexGet(const enum CAN1_RX_FIFO_CHANNELS fifoNum)
300{
301 uint16_t fifoMsgIndex;
302
303 switch (fifoNum)
304 {
305 case CAN1_FIFO_1:
306 fifoMsgIndex = C1FIFOSTA1bits.FIFOCI;
307 break;
308
309 case CAN1_FIFO_2:
310 fifoMsgIndex = C1FIFOSTA2bits.FIFOCI;
311 break;
312
313 default:
314 fifoMsgIndex = 0;
315 break;
316 }
317
318 return fifoMsgIndex;
319}
320
326 static void CAN1_TX_FIFO_MessageSendRequest(const enum CAN1_TX_FIFO_CHANNELS fifoChannel)
327{
328 switch (fifoChannel)
329 {
330 case CAN1_TXQ:
331 // Update the CAN1_TXQ message pointer; Set TXREQ bit
332 C1TXQCONL = (C1TXQCONL | (CAN1_TX_MSG_SEND_REQ_BIT_POS | CAN1_TX_INC_FIFO_PTR_BIT_POS));
333 break;
334
335 default:
336 break;
337 }
338}
339
347 static void CAN1_MessageReadFromFifo(uint16_t *rxFifoObj, struct CAN_MSG_OBJ *rxCanMsg)
348{
349 /*
350 Receive FIFO Object format:
351
352 Receive FIFO WORD_0: |15:8|| EID<4:0> | SID<10:8> ||
353 | 7:0|| SID<7:0> ||
354
355 Receive FIFO WORD_1: |15:8|| SID<11> | EID<17:13> ||
356 | 7:0|| EID<12:5> ||
357
358 Receive FIFO WORD_2: |15:8||FILHIT<4:0> | Reserved | ESI<1> ||
359 | 7:0||FDF<1> | BRS<1> | RTR<1> | IDE<1> | DLC<3:0>||
360
361 Receive FIFO WORD_3: |15:8|| Reserved ||
362 | 7:0|| Reserved ||
363
364 Receive FIFO WORD_4 to |15:8|| Receive Data Byte 1,3,5.. n ||
365 Receive FIFO WORD_n: | 7:0|| Receive Data Byte 0,2,4.. n-1 ||
366 When timestamp is disabled
367 */
368
369 uint8_t dlcByteSize = 0;
370
371 // SID <10:0> and EID <4:0>
372 uint16_t rx0Data = rxFifoObj[CAN_RX_FIFO_WORD_0];
373
374 // SID11 and EID <17:5>
375 uint16_t rx1Data = rxFifoObj[CAN_RX_FIFO_WORD_1];
376
377 // DLC <3:0>, IDE <1>, RTR <1>, BRS <1>, FDF <1>
378 rxCanMsg->field.dlc = (rxFifoObj[CAN_RX_FIFO_WORD_2] & CAN_MSG_OBJ_DLC_FIELD_SIZE);
379 rxCanMsg->field.idType = ((rxFifoObj[CAN_RX_FIFO_WORD_2] & CAN_MSG_OBJ_ID_TYPE_FIELD_POS) >> CAN_MSG_OBJ_ID_TYPE_SHIFT_POS);
380 rxCanMsg->field.frameType = ((rxFifoObj[CAN_RX_FIFO_WORD_2] & CAN_MSG_OBJ_FRAME_TYPE_FIELD_POS) >> CAN_MSG_OBJ_FRAME_TYPE_SHIFT_POS);
381 rxCanMsg->field.brs = ((rxFifoObj[CAN_RX_FIFO_WORD_2] & CAN_MSG_OBJ_BRS_FIELD_POS) >> CAN_MSG_OBJ_BRS_SHIFT_POS);
382 rxCanMsg->field.formatType = ((rxFifoObj[CAN_RX_FIFO_WORD_2] & CAN_MSG_OBJ_FORMAT_TYPE_FIELD_POS) >> CAN_MSG_OBJ_FORMAT_TYPE_SHIFT_POS);
383
384 /* message is standard identifier */
385 if(rxCanMsg->field.idType == (uint8_t) CAN_FRAME_STD)
386 {
387 // SID <10:0>
388 rxCanMsg->msgId = ((uint32_t)rx0Data & CAN_STD_MSG_ID_MAX_SIZE);
389 }
390 else
391 {
392 /* message is extended identifier */
393 // EID <28:18>, EID <17:0>
394 rxCanMsg->msgId = ((((uint32_t)rx0Data & CAN_STD_MSG_ID_MAX_SIZE) << CAN_MSG_OBJ_SID_SHIFT_POS) |
395 (((uint32_t)rx1Data & CAN_EXT_MSG_ID_HIGH_MAX_SIZE) << CAN_MSG_OBJ_EID_HIGH_SHIFT_POS) |
396 (((uint32_t)rx0Data >> CAN_MSG_OBJ_EID_LOW_SHIFT_POS) & CAN_EXT_MSG_ID_LOW_MAX_SIZE));
397 }
398
399 dlcByteSize = CAN1_DlcToDataBytesGet(rxCanMsg->field.dlc);
400
401 // Coping receive FIFO data starting memory location
402 (void)memset(rxMsgData, 0, CAN1_RX_FIFO_MSG_DATA);
403 (void)memcpy((char *) rxMsgData, (char *) (&rxFifoObj[CAN_RX_FIFO_WORD_4]), dlcByteSize);
404 rxCanMsg->data = rxMsgData;
405}
406
413 static void CAN1_MessageWriteToFifo(uint16_t *txFifoObj, struct CAN_MSG_OBJ *txCanMsg)
414{
415 /*
416 Transmit FIFO Object format:
417
418 Transmit FIFO WORD_0: |15:8|| EID<4:0> | SID<10:8> ||
419 | 7:0|| SID<7:0> ||
420
421 Transmit FIFO WORD_1: |15:8|| SID<11> | EID<17:13> ||
422 | 7:0|| EID<12:5> ||
423
424 Transmit FIFO WORD_2: |15:8||Sequence<6:0>(Not implemented) | ESI<1> ||
425 | 7:0||FDF<1> | BRS<1> | RTR<1> | IDE<1> | DLC<3:0>||
426
427 Transmit FIFO WORD_3: |15:8||Sequence<22:15>(Not implemented) ||
428 | 7:0||Sequence<14:7>(Not implemented) ||
429
430 Transmit FIFO WORD_4 to |15:8|| Transmit Data Byte 1,3,5.. n ||
431 Transmit FIFO WORD_n: | 7:0|| Transmit Data Byte 0,2,4.. n-1 ||
432 */
433
434 uint8_t dlcByteSize = 0;
435
436 /* message is standard identifier */
437 if(txCanMsg->field.idType == (uint8_t) CAN_FRAME_STD)
438 {
439 // SID <10:0>
440 txFifoObj[CAN_TX_FIFO_WORD_0] = (txCanMsg->msgId & CAN_STD_MSG_ID_MAX_SIZE);
441 }
442 else
443 {
444 /* message is extended identifier */
445 // SID <10:0> and EID <4:0>
446 txFifoObj[CAN_TX_FIFO_WORD_0] = (((txCanMsg->msgId >> CAN_MSG_OBJ_SID_SHIFT_POS) & CAN_STD_MSG_ID_MAX_SIZE) |
447 (txCanMsg->msgId & CAN_EXT_MSG_ID_LOW_MAX_SIZE) << CAN_MSG_OBJ_EID_LOW_SHIFT_POS);
448
449 // EID <5:17>
450 txFifoObj[CAN_TX_FIFO_WORD_1] = ((txCanMsg->msgId >> CAN_MSG_OBJ_EID_HIGH_SHIFT_POS) & CAN_EXT_MSG_ID_HIGH_MAX_SIZE);
451 }
452
453 // DLC <3:0>, IDE <1>, RTR <1>, BRS <1>, FDF <1>
454 txFifoObj[CAN_TX_FIFO_WORD_2] = (txCanMsg->field.dlc & CAN_MSG_OBJ_DLC_FIELD_SIZE) |
455 ((txCanMsg->field.idType << CAN_MSG_OBJ_ID_TYPE_SHIFT_POS) & CAN_MSG_OBJ_ID_TYPE_FIELD_POS) |
456 ((txCanMsg->field.frameType << CAN_MSG_OBJ_FRAME_TYPE_SHIFT_POS) & CAN_MSG_OBJ_FRAME_TYPE_FIELD_POS) |
457 ((txCanMsg->field.brs << CAN_MSG_OBJ_BRS_SHIFT_POS) & CAN_MSG_OBJ_BRS_FIELD_POS) |
458 ((txCanMsg->field.formatType << CAN_MSG_OBJ_FORMAT_TYPE_SHIFT_POS) & CAN_MSG_OBJ_FORMAT_TYPE_FIELD_POS);
459
460 // Data frame message
461 if(txCanMsg->field.frameType == (uint8_t) CAN_FRAME_DATA)
462 {
463 dlcByteSize = CAN1_DlcToDataBytesGet(txCanMsg->field.dlc);
464
465 // Coping TX message object to FIFO
466 (void)memcpy((uint8_t*)(&txFifoObj[CAN_TX_FIFO_WORD_4]), txCanMsg->data, dlcByteSize);
467 }
468 // RTR frame message
469 else
470 {
471 txFifoObj[CAN_TX_FIFO_WORD_2] = txFifoObj[CAN_TX_FIFO_WORD_2] | (((bool) 1 << CAN_MSG_OBJ_RTR_SHIFT_POS) & CAN_MSG_OBJ_RTR_FIELD_POS);
472 }
473}
474
480 static void CAN1_TX_FIFO_Configuration(void)
481{
482 // TXAT Unlimited attempts; PLSIZE 64; FSIZE 3; TXPRI 0;
483 C1TXQCONH = 0xE240;
484 // TXQEIE disabled; TXREQ disabled; TXQNIE disabled; TXATIE disabled; UINC disabled; FRESET enabled;
485 C1TXQCONL = 0x480;
486}
487
494 static void CAN1_RX_FIFO_Configuration(void)
495{
496 // TXAT Disabled; PLSIZE 64; FSIZE 1; TXPRI 0;
497 C1FIFOCON1H = 0xE000;
498 // TFHRFHIE disabled; TFERFFIE disabled; RXTSEN disabled; TXREQ disabled; RXOVIE disabled; RTREN disabled; TXEN disabled; TXATIE disabled; UINC disabled; FRESET enabled; TFNRFNIE disabled;
499 C1FIFOCON1L = 0x400;
500 // TXAT Disabled; PLSIZE 64; FSIZE 1; TXPRI 0;
501 C1FIFOCON2H = 0xE000;
502 // TFHRFHIE disabled; TFERFFIE disabled; RXTSEN disabled; TXREQ disabled; RXOVIE disabled; RTREN disabled; TXEN disabled; TXATIE disabled; UINC disabled; FRESET enabled; TFNRFNIE disabled;
503 C1FIFOCON2L = 0x400;
504}
505
511 static void CAN1_RX_FIFO_FilterMaskConfiguration(void)
512{
513 /* Configure RX FIFO Filter control settings*/
514
515 // message stored in FIFO1
516 C1FLTCON0Lbits.F0BP = 1;
517 // EID 0; SID 1026;
518 C1FLTOBJ0L = 0x402;
519 // EID 0; EXIDE disabled; SID11 disabled;
520 C1FLTOBJ0H = 0x0;
521 // MSID 2047; MEID 0;
522 C1MASK0L = 0x7FF;
523 // MEID 0; MSID11 disabled; MIDE enabled;
524 C1MASK0H = 0x4000;
525 // Enable the filter 0
526 C1FLTCON0Lbits.FLTEN0 = 1;
527
528 // message stored in FIFO2
529 C1FLTCON0Lbits.F1BP = 2;
530 // EID 0; SID 1027;
531 C1FLTOBJ1L = 0x403;
532 // EID 0; EXIDE disabled; SID11 disabled;
533 C1FLTOBJ1H = 0x0;
534 // MSID 2047; MEID 0;
535 C1MASK1L = 0x7FF;
536 // MEID 0; MSID11 disabled; MIDE enabled;
537 C1MASK1H = 0x4000;
538 // Enable the filter 1
539 C1FLTCON0Lbits.FLTEN1 = 1;
540}
541
547 static void CAN1_BitRateConfiguration(void)
548{
549 // BRP 0; TSEG1 30;
550 C1NBTCFGH = 0x1E;
551 // SJW 7; TSEG2 7;
552 C1NBTCFGL = 0x707;
553 // BRP 0; TSEG1 6;
554 C1DBTCFGH = 0x6;
555 // SJW 1; TSEG2 1;
556 C1DBTCFGL = 0x101;
557 // EDGFLTEN disabled; TDCMOD Auto; SID11EN disabled;
558 C1TDCH = 0x2;
559 // TDCV 0x0; TDCO 7;
560 C1TDCL = 0x700;
561}
562
568 static void CAN1_ErrorNotificationEnable(void)
569{
570 // CAN1 CAN1 Callback initialize
571 CAN1_InvalidMessageCallbackRegister(&CAN1_InvalidMessageCallback);
572 CAN1_BusWakeUpActivityCallbackRegister(&CAN1_BusWakeUpActivityCallback);
573 CAN1_BusErrorCallbackRegister(&CAN1_BusErrorCallback);
574 CAN1_ModeChangeCallbackRegister(&CAN1_ModeChangeCallback);
575 CAN1_SystemErrorCallbackRegister(&CAN1_SystemErrorCallback);
576 CAN1_TxAttemptCallbackRegister(&CAN1_TxAttemptCallback);
577 CAN1_RxBufferOverFlowCallbackRegister(&CAN1_RxBufferOverFlowCallback);
578}
579
580// Section: Driver Interface Function Definitions
581 void CAN1_Initialize(void)
582{
583 /* Enable the CAN1 module */
584 C1CONLbits.CON = 1;
585
586 // RTXAT disabled; ESIGM disabled; TXBWS No delay; STEF disabled; SERRLOM disabled; ABAT disabled; REQOP Configuration mode; TXQEN enabled;
587 C1CONH = 0x490;
588
589 /* Place CAN1 module in configuration mode */
590 if(CAN_OP_MODE_REQUEST_SUCCESS == CAN1_OperationModeSet(CAN_CONFIGURATION_MODE))
591 {
592 /* Initialize the C1FIFOBAL with the start address of the CAN1 FIFO message object area. */
593 C1FIFOBAL = (uint16_t) &can1FifoMsg[0];
594
595 // BRSDIS disabled; CON enabled; WAKFIL enabled; WFT T11 Filter; ISOCRCEN enabled; SIDL disabled; DNCNT 0x0; PXEDIS enabled; CLKSEL disabled;
596 C1CONL = 0x8760;
597
598 // Disabled CAN1 Store in Transmit Event FIFO bit
599 C1CONHbits.STEF = 0;
600 // Enabled CAN1 Transmit Queue bit
601 C1CONHbits.TXQEN = 1;
602
603 /* configure CAN1 Bit rate settings */
604 CAN1_BitRateConfiguration();
605
606 /* configure CAN1 FIFO settings */
607 CAN1_TX_FIFO_Configuration();
608 CAN1_RX_FIFO_Configuration();
609
610 /* Configure Receive FIFO Filter and Mask settings */
611 CAN1_RX_FIFO_FilterMaskConfiguration();
612
613 /* CAN Error Notification */
614 CAN1_ErrorNotificationEnable();
615
616 // Reset the CAN1 receive FIFO head count
617 CAN1_RX_FIFO_ResetInfo();
618
619 /* Place CAN1 module in Normal Operation mode */
620 (void)CAN1_OperationModeSet(CAN_NORMAL_FD_MODE);
621 }
622}
623
624 void CAN1_Deinitialize(void)
625{
626 /* Place CAN1 module in configuration mode */
627 if(CAN_OP_MODE_REQUEST_SUCCESS == CAN1_OperationModeSet(CAN_CONFIGURATION_MODE))
628 {
629 C1CONL = 0x760;
630 C1CONH = 0x498;
631
632 /* Reset bit rate settings to POR*/
633 C1NBTCFGH = 0x3E;
634 C1NBTCFGL = 0xF0F;
635 C1DBTCFGH = 0xE;
636 C1DBTCFGL = 0x303;
637 C1TDCH = 0x2;
638 C1TDCL = 0x1000;
639
640 /* configure CAN1 FIFO settings */
641 /* Reset TX FIFO settings to POR*/
642 C1TXQCONH = 0x60;
643 C1TXQCONL = 0x480;
644
645 /* Reset RX FIFO settings to POR*/
646 C1FIFOCON1H = 0x60;
647 C1FIFOCON1L = 0x400;
648 C1FIFOCON2H = 0x60;
649 C1FIFOCON2L = 0x400;
650
651 /* Reset RX FIFO Filter control settings to POR*/
652 C1FLTCON0Lbits.F0BP = 0x0;
653 C1FLTOBJ0L = 0x0;
654 C1FLTOBJ0H = 0x0;
655 C1MASK0L = 0x0;
656 C1MASK0H = 0x0;
657 C1FLTCON0Lbits.FLTEN0 = 0x0;
658 C1FLTCON0Lbits.F1BP = 0x0;
659 C1FLTOBJ1L = 0x0;
660 C1FLTOBJ1H = 0x0;
661 C1MASK1L = 0x0;
662 C1MASK1H = 0x0;
663 C1FLTCON0Lbits.FLTEN1 = 0x0;
664
665 }
666
667 /* Disable the CAN1 module */
668 C1CONLbits.CON = 0;
669}
670
671 enum CAN_OP_MODE_STATUS CAN1_OperationModeSet(const enum CAN_OP_MODES requestMode)
672{
673 enum CAN_OP_MODE_STATUS status = CAN_OP_MODE_REQUEST_SUCCESS;
674
675 if((CAN_CONFIGURATION_MODE == CAN1_OperationModeGet()) || (requestMode == CAN_DISABLE_MODE)
676 || (requestMode == CAN_CONFIGURATION_MODE))
677 {
678 C1CONHbits.REQOP = requestMode;
679
680 while(C1CONHbits.OPMOD != requestMode)
681 {
682 // This condition is avoiding the system error case endless loop
683 if(C1INTLbits.SERRIF == 1)
684 {
685 status = CAN_OP_MODE_SYS_ERROR_OCCURED;
686 break;
687 }
688 }
689 }
690 else
691 {
692 status = CAN_OP_MODE_REQUEST_FAIL;
693 }
694
695 return status;
696}
697
698 enum CAN_OP_MODES CAN1_OperationModeGet(void)
699{
700 return C1CONHbits.OPMOD;
701}
702
703 bool CAN1_Receive(struct CAN_MSG_OBJ *rxCanMsg)
704{
705 uint8_t fifoChannel;
706 uint8_t count;
707 uint8_t rxMsgStatus;
708 volatile struct CAN1_FIFO_INFO fifoInfo;
709 bool status = false;
710
711 // Iterate all receive FIFO's and read the message object
712 for(count = 0; count < CAN1_NUM_OF_RX_FIFO; count++)
713 {
714 fifoChannel = rxFIFOMsg[count].channel;
715 CAN1_FIFO_InfoGet(fifoChannel, &fifoInfo);
716 rxMsgStatus = CAN1_RX_FIFO_StatusGet(fifoChannel);
717
718 // If message object is available
719 if((uint8_t)CAN_RX_MSG_AVAILABLE == (rxMsgStatus & (uint8_t)CAN_RX_MSG_AVAILABLE))
720 {
721 if((uint16_t *)(*(fifoInfo.address)) != NULL)
722 {
723 CAN1_MessageReadFromFifo((uint16_t *) *fifoInfo.address, rxCanMsg);
724 CAN1_RX_FIFO_IncrementMsgPtr(fifoChannel);
725
726 // Update the RX FIFO Head count for CAN1_ReceivedMessageCountGet function
727 rxFIFOMsg[count].headCount++; // Update the read one message
728 if(rxFIFOMsg[count].headCount >= fifoInfo.msgDeepSize)
729 {
730 rxFIFOMsg[count].headCount = 0; // Reset the read message count
731 }
732
733 // User have to clear manually RX Overflow status
734 if((uint8_t)CAN_RX_MSG_OVERFLOW == (rxMsgStatus & (uint8_t)CAN_RX_MSG_OVERFLOW))
735 {
736 CAN1_RX_FIFO_OverflowStatusFlagClear(fifoChannel);
737 }
738
739 status = true;
740 }
741
742 break;
743 }
744 }
745
746 return status;
747}
748
749 bool CAN1_ReceiveMessageGet(const enum CAN1_RX_FIFO_CHANNELS fifoChannel, struct CAN_MSG_OBJ *rxCanMsg)
750{
751 uint8_t count;
752 uint8_t rxMsgStatus;
753 struct CAN1_FIFO_INFO fifoInfo;
754 bool status = false;
755
756 CAN1_FIFO_InfoGet(fifoChannel, &fifoInfo);
757 rxMsgStatus = CAN1_RX_FIFO_StatusGet(fifoChannel);
758 count = CAN1_RxFifoSearch(fifoChannel);
759
760 // If message object is available
761 if((uint8_t)CAN_RX_MSG_AVAILABLE == (rxMsgStatus & (uint8_t)CAN_RX_MSG_AVAILABLE))
762 {
763 if((uint16_t *)(*(fifoInfo.address)) != NULL)
764 {
765 CAN1_MessageReadFromFifo((uint16_t *) *fifoInfo.address, rxCanMsg);
766 CAN1_RX_FIFO_IncrementMsgPtr(fifoChannel);
767
768 // Update the RX FIFO Head count for CAN1_ReceivedMessageCountGet function
769 rxFIFOMsg[count].headCount++; // Update the read one message
770 if(rxFIFOMsg[count].headCount >= fifoInfo.msgDeepSize)
771 {
772 rxFIFOMsg[count].headCount = 0; // Reset the read message count
773 }
774
775 // User have to clear manually RX Overflow status
776 if((uint8_t)CAN_RX_MSG_OVERFLOW == (rxMsgStatus & (uint8_t)CAN_RX_MSG_OVERFLOW))
777 {
778 CAN1_RX_FIFO_OverflowStatusFlagClear(fifoChannel);
779 }
780
781 status = true;
782 }
783 }
784
785 return status;
786}
787
788 enum CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const enum CAN1_TX_FIFO_CHANNELS fifoChannel, struct CAN_MSG_OBJ *txCanMsg)
789{
790 volatile struct CAN1_FIFO_INFO fifoInfo;
791 CAN1_FIFO_InfoGet(fifoChannel, &fifoInfo);
792 enum CAN_TX_MSG_REQUEST_STATUS txMsgStatus = CAN_TX_MSG_REQUEST_SUCCESS;
793 enum CAN_OP_MODES canOpModeStatus = CAN1_OperationModeGet();
794
795 // If CAN module is configured in Non-BRS mode and TX message object has BRS set
796 if((txCanMsg->field.brs == (bool) 1) && (C1CONLbits.BRSDIS == (bool) 1 || (CAN_NORMAL_2_0_MODE == canOpModeStatus)))
797 {
798 txMsgStatus |= CAN_TX_MSG_REQUEST_BRS_ERROR;
799 }
800
801 // If CAN 2.0 mode, Tx Message object has more than 8 bytes of DLC Size
802 if((CAN_NORMAL_2_0_MODE == canOpModeStatus) || (txCanMsg->field.formatType == (uint8_t) CAN_2_0_FORMAT))
803 {
804 // CAN 2.0 mode DLC supports upto 8 byte
805 if(txCanMsg->field.dlc > (uint8_t) DLC_8)
806 {
807 txMsgStatus |= CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR;
808 }
809 }
810
811 // If any CAN TX message object has DLC size more than CAN TX FIFO Payload size
812 if(CAN1_DlcToDataBytesGet(txCanMsg->field.dlc) > fifoInfo.payloadSize)
813 {
814 txMsgStatus |= CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR;
815 }
816
817 if(CAN_TX_MSG_REQUEST_SUCCESS == txMsgStatus)
818 {
819 if(CAN_TX_FIFO_AVAILABLE == CAN1_TransmitFIFOStatusGet(fifoChannel))
820 {
821 if((uint16_t *)(*(fifoInfo.address)) != NULL)
822 {
823 CAN1_MessageWriteToFifo((uint16_t *) *fifoInfo.address, txCanMsg);
824 CAN1_TX_FIFO_MessageSendRequest(fifoChannel);
825 }
826 }
827 else
828 {
829 txMsgStatus |= CAN_TX_MSG_REQUEST_FIFO_FULL;
830 }
831 }
832
833 return txMsgStatus;
834}
835
836 enum CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const enum CAN1_TX_FIFO_CHANNELS fifoChannel)
837{
838 enum CAN_TX_FIFO_STATUS fifoStatus;
839
840 switch (fifoChannel)
841 {
842 case CAN1_TXQ:
843 fifoStatus = ((C1TXQSTA & 0x1) ? CAN_TX_FIFO_AVAILABLE:CAN_TX_FIFO_FULL);
844 break;
845
846 default:
847 fifoStatus = CAN_TX_FIFO_FULL;
848 break;
849 }
850
851 return fifoStatus;
852}
853
854uint8_t CAN1_ReceivedMessageCountGet(void)
855{
856 uint8_t fifoChannel = 0;
857 uint8_t count = 0;
858 uint8_t numOfMsg = 0;
859 uint8_t totalMsgObj = 0;
860 uint8_t rxMsgStatus;
861 struct CAN1_FIFO_INFO fifoInfo;
862 uint16_t rxfifoMsgTail;
863
864 // Iterate all receive FIFO's and get the message object count
865 for(count = 0; count < CAN1_NUM_OF_RX_FIFO; count++)
866 {
867 fifoChannel = rxFIFOMsg[count].channel;
868 CAN1_FIFO_InfoGet(fifoChannel, &fifoInfo);
869 rxMsgStatus = CAN1_RX_FIFO_StatusGet(fifoChannel);
870
871 // If message object is available
872 if((uint8_t)CAN_RX_MSG_AVAILABLE == (rxMsgStatus & (uint8_t)CAN_RX_MSG_AVAILABLE))
873 {
874 // If receive FIFO overflow has occurred, FIFO is full
875 if((uint8_t)CAN_RX_MSG_OVERFLOW == (rxMsgStatus & (uint8_t)CAN_RX_MSG_OVERFLOW))
876 {
877 numOfMsg = fifoInfo.msgDeepSize;
878 }
879 else
880 {
881 rxfifoMsgTail = CAN1_RX_FIFO_MessageIndexGet(fifoChannel);
882
883 if(rxfifoMsgTail < rxFIFOMsg[count].headCount)
884 {
885 numOfMsg = ((rxfifoMsgTail + fifoInfo.msgDeepSize) - rxFIFOMsg[count].headCount);
886 }
887 else if(rxfifoMsgTail > rxFIFOMsg[count].headCount)
888 {
889 numOfMsg = rxfifoMsgTail - rxFIFOMsg[count].headCount;
890 }
891 else
892 {
893 numOfMsg = fifoInfo.msgDeepSize;
894 }
895 }
896
897 totalMsgObj += numOfMsg;
898 }
899 }
900
901 return totalMsgObj;
902}
903
904uint8_t CAN1_RX_FIFO_StatusGet(const enum CAN1_RX_FIFO_CHANNELS fifoNum)
905{
906 uint8_t rxFifoStatus;
907
908 switch (fifoNum)
909 {
910 case CAN1_FIFO_1:
911 rxFifoStatus = (uint8_t)(C1FIFOSTA1 & (CAN_RX_MSG_AVAILABLE | CAN_RX_MSG_OVERFLOW));
912 break;
913
914 case CAN1_FIFO_2:
915 rxFifoStatus = (uint8_t)(C1FIFOSTA2 & (CAN_RX_MSG_AVAILABLE | CAN_RX_MSG_OVERFLOW));
916 break;
917
918 default:
919 rxFifoStatus = (uint8_t)CAN_RX_MSG_NOT_AVAILABLE;
920 break;
921 }
922
923 return rxFifoStatus;
924}
925
926 bool CAN1_IsBusOff(void)
927{
928 return C1TRECHbits.TXBO;
929}
930
931 bool CAN1_IsRxErrorPassive(void)
932{
933 return C1TRECHbits.RXBP;
934}
935
936 bool CAN1_IsRxErrorWarning(void)
937{
938 return C1TRECHbits.RXWARN;
939}
940
941 bool CAN1_IsRxErrorActive(void)
942{
943 bool errorState = false;
944 if((0 < C1TRECLbits.RERRCNT) && (C1TRECLbits.RERRCNT < 128))
945 {
946 errorState = true;
947 }
948
949 return errorState;
950}
951
952 bool CAN1_IsTxErrorPassive(void)
953{
954 return C1TRECHbits.TXBP;
955}
956
957 bool CAN1_IsTxErrorWarning(void)
958{
959 return C1TRECHbits.TXWARN;
960}
961
962 bool CAN1_IsTxErrorActive(void)
963{
964 bool errorState = false;
965 if((0 < C1TRECLbits.TERRCNT) && (C1TRECLbits.TERRCNT < 128))
966 {
967 errorState = true;
968 }
969
970 return errorState;
971}
972
973 void CAN1_Sleep(void)
974{
975 C1INTLbits.WAKIF = 0;
976 C1INTHbits.WAKIE = 1;
977
978 // CAN Info Interrupt Enable bit
979 IEC1bits.C1IE = 1;
980
981 /* put the module in disable mode */
982 (void)CAN1_OperationModeSet(CAN_DISABLE_MODE);
983}
984
985 void CAN1_InvalidMessageCallbackRegister(void (*handler)(void))
986{
987 if(NULL != handler)
988 {
989 CAN1_InvalidMessageHandler = handler;
990 }
991}
992
993 void __attribute__ ((weak)) CAN1_InvalidMessageCallback ( void )
994{
995
996}
997
998 void CAN1_BusWakeUpActivityCallbackRegister(void (*handler)(void))
999{
1000 if(NULL != handler)
1001 {
1002 CAN1_BusWakeUpActivityHandler = handler;
1003 }
1004}
1005
1006void __attribute__ ((weak)) CAN1_BusWakeUpActivityCallback ( void )
1007{
1008
1009}
1010
1011 void CAN1_BusErrorCallbackRegister(void (*handler)(void))
1012{
1013 if(NULL != handler)
1014 {
1015 CAN1_BusErrorHandler = handler;
1016 }
1017}
1018
1019void __attribute__ ((weak)) CAN1_BusErrorCallback ( void )
1020{
1021
1022}
1023
1024 void CAN1_ModeChangeCallbackRegister(void (*handler)(void))
1025{
1026 if(NULL != handler)
1027 {
1028 CAN1_ModeChangeHandler = handler;
1029 }
1030}
1031
1032void __attribute__ ((weak)) CAN1_ModeChangeCallback ( void )
1033{
1034
1035}
1036
1037 void CAN1_SystemErrorCallbackRegister(void (*handler)(void))
1038{
1039 if(NULL != handler)
1040 {
1041 CAN1_SystemErrorHandler = handler;
1042 }
1043}
1044
1045void __attribute__ ((weak)) CAN1_SystemErrorCallback ( void )
1046{
1047
1048}
1049
1050 void CAN1_TxAttemptCallbackRegister(void (*handler)(void))
1051{
1052 if(NULL != handler)
1053 {
1054 CAN1_TxAttemptHandler = handler;
1055 }
1056}
1057
1058void __attribute__ ((weak)) CAN1_TxAttemptCallback(void)
1059{
1060
1061}
1062
1063 void CAN1_RxBufferOverFlowCallbackRegister(void (*handler)(void))
1064{
1065 if(NULL != handler)
1066 {
1067 CAN1_RxBufferOverFlowHandler = handler;
1068 }
1069}
1070
1071void __attribute__ ((weak)) CAN1_RxBufferOverFlowCallback(void)
1072{
1073
1074}
1075
1076 void __attribute__((__interrupt__, no_auto_psv)) _C1Interrupt(void)
1077{
1078 // Bus Wake-up Activity Interrupt
1079 if(1 == C1INTLbits.WAKIF)
1080 {
1081 if(CAN1_BusWakeUpActivityHandler != NULL)
1082 {
1083 CAN1_BusWakeUpActivityHandler();
1084 }
1085
1086 C1INTLbits.WAKIF = 0;
1087 }
1088
1089 IFS1bits.C1IF = 0;
1090}
1091
1092 void CAN1_Tasks(void)
1093{
1094 if(1 == C1INTLbits.IVMIF)
1095 {
1096 if(CAN1_InvalidMessageHandler != NULL)
1097 {
1098 CAN1_InvalidMessageHandler();
1099 }
1100
1101 C1INTLbits.IVMIF = 0;
1102 }
1103
1104 if(1 == C1INTLbits.CERRIF)
1105 {
1106 if(CAN1_BusErrorHandler != NULL)
1107 {
1108 CAN1_BusErrorHandler();
1109 }
1110
1111 C1INTLbits.CERRIF = 0;
1112 }
1113
1114 if(1 == C1INTLbits.MODIF)
1115 {
1116 if(CAN1_ModeChangeHandler != NULL)
1117 {
1118 CAN1_ModeChangeHandler();
1119 }
1120
1121 C1INTLbits.MODIF = 0;
1122 }
1123
1124 if(1 == C1INTLbits.SERRIF)
1125 {
1126 if(CAN1_SystemErrorHandler != NULL)
1127 {
1128 CAN1_SystemErrorHandler();
1129 }
1130
1131 C1INTLbits.SERRIF = 0;
1132 }
1133
1134 if(1 == C1INTLbits.TXATIF)
1135 {
1136 if(CAN1_TxAttemptHandler != NULL)
1137 {
1138 CAN1_TxAttemptHandler();
1139 }
1140 }
1141
1142 if(1 == C1FIFOSTA1bits.RXOVIF)
1143 {
1144 if(CAN1_RxBufferOverFlowHandler != NULL)
1145 {
1146 CAN1_RxBufferOverFlowHandler();
1147 }
1148
1149 C1FIFOSTA1bits.RXOVIF = 0;
1150 }
1151
1152 if(1 == C1FIFOSTA2bits.RXOVIF)
1153 {
1154 if(CAN1_RxBufferOverFlowHandler != NULL)
1155 {
1156 CAN1_RxBufferOverFlowHandler();
1157 }
1158
1159 C1FIFOSTA2bits.RXOVIF = 0;
1160 }
1161
1162}
1163
CAN1_TX_FIFO_CHANNELS
CAN1_TX_FIFO_CHANNELS
Definition can1.h:216
CAN1_TXQ
@ CAN1_TXQ
Definition can1.h:217
CAN1_RX_FIFO_CHANNELS
CAN1_RX_FIFO_CHANNELS
Definition can1.h:226
CAN1_FIFO_2
@ CAN1_FIFO_2
Definition can1.h:228
CAN1_FIFO_1
@ CAN1_FIFO_1
Definition can1.h:227
CAN_DLC
CAN_DLC
Definition can_types.h:177
DLC_8
@ DLC_8
Definition can_types.h:187
CAN_FRAME_STD
@ CAN_FRAME_STD
Definition can_types.h:92
CAN_FRAME_DATA
@ CAN_FRAME_DATA
Definition can_types.h:103
CAN_TX_FIFO_STATUS
CAN_TX_FIFO_STATUS
Definition can_types.h:166
CAN_TX_FIFO_AVAILABLE
@ CAN_TX_FIFO_AVAILABLE
Definition can_types.h:168
CAN_TX_FIFO_FULL
@ CAN_TX_FIFO_FULL
Definition can_types.h:167
CAN_2_0_FORMAT
@ CAN_2_0_FORMAT
Definition can_types.h:114
CAN_OP_MODE_STATUS
CAN_OP_MODE_STATUS
Definition can_types.h:154
CAN_OP_MODE_SYS_ERROR_OCCURED
@ CAN_OP_MODE_SYS_ERROR_OCCURED
Definition can_types.h:157
CAN_OP_MODE_REQUEST_FAIL
@ CAN_OP_MODE_REQUEST_FAIL
Definition can_types.h:156
CAN_OP_MODE_REQUEST_SUCCESS
@ CAN_OP_MODE_REQUEST_SUCCESS
Definition can_types.h:155
CAN_TX_MSG_REQUEST_STATUS
CAN_TX_MSG_REQUEST_STATUS
Definition can_types.h:124
CAN_TX_MSG_REQUEST_BRS_ERROR
@ CAN_TX_MSG_REQUEST_BRS_ERROR
Definition can_types.h:127
CAN_TX_MSG_REQUEST_SUCCESS
@ CAN_TX_MSG_REQUEST_SUCCESS
Definition can_types.h:125
CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR
@ CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR
Definition can_types.h:126
CAN_TX_MSG_REQUEST_FIFO_FULL
@ CAN_TX_MSG_REQUEST_FIFO_FULL
Definition can_types.h:128
CAN_RX_MSG_OVERFLOW
@ CAN_RX_MSG_OVERFLOW
Definition can_types.h:209
CAN_RX_MSG_NOT_AVAILABLE
@ CAN_RX_MSG_NOT_AVAILABLE
Definition can_types.h:207
CAN_RX_MSG_AVAILABLE
@ CAN_RX_MSG_AVAILABLE
Definition can_types.h:208
CAN_OP_MODES
CAN_OP_MODES
Definition can_types.h:137
CAN_DISABLE_MODE
@ CAN_DISABLE_MODE
Definition can_types.h:139
CAN_NORMAL_FD_MODE
@ CAN_NORMAL_FD_MODE
Definition can_types.h:138
CAN_NORMAL_2_0_MODE
@ CAN_NORMAL_2_0_MODE
Definition can_types.h:144
CAN_CONFIGURATION_MODE
@ CAN_CONFIGURATION_MODE
Definition can_types.h:142
CAN_RX_FIFO_WORD_1
#define CAN_RX_FIFO_WORD_1
Definition can1.c:51
CAN_MSG_OBJ_EID_LOW_SHIFT_POS
#define CAN_MSG_OBJ_EID_LOW_SHIFT_POS
Definition can1.c:79
CAN_MSG_OBJ_FORMAT_TYPE_SHIFT_POS
#define CAN_MSG_OBJ_FORMAT_TYPE_SHIFT_POS
Definition can1.c:74
CAN1_RX_FIFO_MSG_DATA
#define CAN1_RX_FIFO_MSG_DATA
Definition can1.c:49
CAN_MSG_OBJ_BRS_SHIFT_POS
#define CAN_MSG_OBJ_BRS_SHIFT_POS
Definition can1.c:72
__attribute__
void __attribute__((weak))
Definition can1.c:993
CAN_MSG_OBJ_RTR_FIELD_POS
#define CAN_MSG_OBJ_RTR_FIELD_POS
Definition can1.c:68
CAN_MSG_OBJ_FORMAT_TYPE_FIELD_POS
#define CAN_MSG_OBJ_FORMAT_TYPE_FIELD_POS
Definition can1.c:73
CAN_TX_FIFO_WORD_1
#define CAN_TX_FIFO_WORD_1
Definition can1.c:59
CAN1_FIFO_ALLOCATE_RAM_SIZE
#define CAN1_FIFO_ALLOCATE_RAM_SIZE
Definition can1.c:45
CAN_TX_FIFO_WORD_4
#define CAN_TX_FIFO_WORD_4
Definition can1.c:61
CAN_MSG_OBJ_ID_TYPE_FIELD_POS
#define CAN_MSG_OBJ_ID_TYPE_FIELD_POS
Definition can1.c:65
CAN_STD_MSG_ID_MAX_SIZE
#define CAN_STD_MSG_ID_MAX_SIZE
Definition can1.c:75
CAN_RX_FIFO_WORD_2
#define CAN_RX_FIFO_WORD_2
Definition can1.c:52
CAN_MSG_OBJ_FRAME_TYPE_SHIFT_POS
#define CAN_MSG_OBJ_FRAME_TYPE_SHIFT_POS
Definition can1.c:70
rxFIFOMsg
static volatile struct CAN1_RX_FIFO_MSG rxFIFOMsg[CAN1_NUM_OF_RX_FIFO]
Definition can1.c:140
CAN_TX_FIFO_WORD_0
#define CAN_TX_FIFO_WORD_0
Definition can1.c:58
CAN1_TX_MSG_SEND_REQ_BIT_POS
#define CAN1_TX_MSG_SEND_REQ_BIT_POS
Definition can1.c:56
CAN_EXT_MSG_ID_LOW_MAX_SIZE
#define CAN_EXT_MSG_ID_LOW_MAX_SIZE
Definition can1.c:78
CAN_MSG_OBJ_DLC_FIELD_SIZE
#define CAN_MSG_OBJ_DLC_FIELD_SIZE
Definition can1.c:64
CAN_MSG_OBJ_BRS_FIELD_POS
#define CAN_MSG_OBJ_BRS_FIELD_POS
Definition can1.c:71
CAN1_TX_INC_FIFO_PTR_BIT_POS
#define CAN1_TX_INC_FIFO_PTR_BIT_POS
Definition can1.c:57
CAN_MSG_OBJ_FRAME_TYPE_FIELD_POS
#define CAN_MSG_OBJ_FRAME_TYPE_FIELD_POS
Definition can1.c:69
CAN_MSG_OBJ_EID_HIGH_SHIFT_POS
#define CAN_MSG_OBJ_EID_HIGH_SHIFT_POS
Definition can1.c:80
CAN1_NUM_OF_RX_FIFO
#define CAN1_NUM_OF_RX_FIFO
Definition can1.c:48
CAN_RX_FIFO_WORD_0
#define CAN_RX_FIFO_WORD_0
Definition can1.c:50
CAN_EXT_MSG_ID_HIGH_MAX_SIZE
#define CAN_EXT_MSG_ID_HIGH_MAX_SIZE
Definition can1.c:77
CAN_RX_FIFO_WORD_4
#define CAN_RX_FIFO_WORD_4
Definition can1.c:53
CAN_MSG_OBJ_RTR_SHIFT_POS
#define CAN_MSG_OBJ_RTR_SHIFT_POS
Definition can1.c:67
CAN_MSG_OBJ_SID_SHIFT_POS
#define CAN_MSG_OBJ_SID_SHIFT_POS
Definition can1.c:76
CAN_MSG_OBJ_ID_TYPE_SHIFT_POS
#define CAN_MSG_OBJ_ID_TYPE_SHIFT_POS
Definition can1.c:66
CAN_TX_FIFO_WORD_2
#define CAN_TX_FIFO_WORD_2
Definition can1.c:60
status
size_t status
Definition uart1.c:99
CAN1_MessageWriteToFifo
static void CAN1_MessageWriteToFifo(uint16_t *txFifoObj, struct CAN_MSG_OBJ *txCanMsg)
This function Read the message object from user input and update to the CAN1 TX FIFO.
Definition can1.c:413
CAN1_RX_FIFO_IncrementMsgPtr
static void CAN1_RX_FIFO_IncrementMsgPtr(const uint8_t fifoNum)
This function Update the receive FIFO message increment tail position.
Definition can1.c:277
CAN1_ModeChangeCallbackRegister
void CAN1_ModeChangeCallbackRegister(void(*handler)(void))
This function can be used to override default callback and to define custom callback for CAN1_ModeCha...
Definition can1.c:1024
CAN1_RxBufferOverFlowCallbackRegister
void CAN1_RxBufferOverFlowCallbackRegister(void(*handler)(void))
This function can be used to override default callback and to define custom callback for CAN1_RxBuffe...
Definition can1.c:1063
CAN1_TransmitFIFOStatusGet
enum CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const enum CAN1_TX_FIFO_CHANNELS fifoChannel)
Returns the CAN1 transmitter FIFO status.
Definition can1.c:836
CAN1_RX_FIFO_OverflowStatusFlagClear
static void CAN1_RX_FIFO_OverflowStatusFlagClear(const enum CAN1_RX_FIFO_CHANNELS fifoNum)
This function is used to clear the CAN1 receive FIFO overflow status bit.
Definition can1.c:255
CAN1_RX_FIFO_ResetInfo
static void CAN1_RX_FIFO_ResetInfo(void)
This function reset the CAN1 receive message head count.
Definition can1.c:214
CAN1_ReceiveMessageGet
bool CAN1_ReceiveMessageGet(const enum CAN1_RX_FIFO_CHANNELS fifoChannel, struct CAN_MSG_OBJ *rxCanMsg)
Reads the received single message object from the CAN1 receive FIFO.
Definition can1.c:749
CAN1_IsTxErrorActive
bool CAN1_IsTxErrorActive(void)
Returns the transmit error active state.
Definition can1.c:962
CAN1_IsRxErrorWarning
bool CAN1_IsRxErrorWarning(void)
Returns the receive error warning state. If Receiver error counter is above 95 to below 128,...
Definition can1.c:936
CAN1_TxAttemptCallback
void CAN1_TxAttemptCallback(void)
This is the default callback with weak attribute. The user can override and implement the default cal...
CAN_FD1
const struct CAN_INTERFACE CAN_FD1
Structure object of type CAN_INTERFACE with the custom name given by the user in the Melody Driver Us...
Definition can1.c:83
CAN1_Sleep
void CAN1_Sleep(void)
Sets the CAN node in sleep mode.
Definition can1.c:973
CAN1_RX_FIFO_StatusGet
uint8_t CAN1_RX_FIFO_StatusGet(const enum CAN1_RX_FIFO_CHANNELS fifoNum)
This returns the CAN1 receive FIFO status.
Definition can1.c:904
CAN1_Receive
bool CAN1_Receive(struct CAN_MSG_OBJ *rxCanMsg)
Reads the received single message object.
Definition can1.c:703
CAN1_RX_FIFO_MessageIndexGet
static uint16_t CAN1_RX_FIFO_MessageIndexGet(const enum CAN1_RX_FIFO_CHANNELS fifoNum)
This function get the Receiver FIFO message index value.
Definition can1.c:299
CAN1_BusErrorCallbackRegister
void CAN1_BusErrorCallbackRegister(void(*handler)(void))
This function can be used to override default callback and to define custom callback for CAN1_BusErro...
Definition can1.c:1011
CAN1_FIFO_InfoGet
static void CAN1_FIFO_InfoGet(const uint8_t fifoNum, volatile struct CAN1_FIFO_INFO *fifoInfo)
This function get the FIFO user address, message depth and payload size information.
Definition can1.c:179
CAN1_SystemErrorCallbackRegister
void CAN1_SystemErrorCallbackRegister(void(*handler)(void))
This function can be used to override default callback and to define custom callback for CAN1_SystemE...
Definition can1.c:1037
CAN1_DlcToDataBytesGet
static uint8_t CAN1_DlcToDataBytesGet(const enum CAN_DLC dlc)
This function get the DLC enum based decimal value.
Definition can1.c:166
CAN1_BusWakeUpActivityCallback
void CAN1_BusWakeUpActivityCallback(void)
This is the default callback with weak attribute. The user can override and implement the default cal...
CAN1_IsRxErrorActive
bool CAN1_IsRxErrorActive(void)
Returns the receive error active state.
Definition can1.c:941
CAN1_TX_FIFO_Configuration
static void CAN1_TX_FIFO_Configuration(void)
This function configure the CAN1 transmit FIFO settings.
Definition can1.c:480
CAN1_RX_FIFO_Configuration
static void CAN1_RX_FIFO_Configuration(void)
This function configure the CAN1 receive FIFO settings.
Definition can1.c:494
CAN1_RX_FIFO_FilterMaskConfiguration
static void CAN1_RX_FIFO_FilterMaskConfiguration(void)
This function configure the CAN1 filter and mask settings.
Definition can1.c:511
CAN1_Tasks
void CAN1_Tasks(void)
This routine is used to implement the tasks for polled implementations.
Definition can1.c:1092
CAN1_SystemErrorCallback
void CAN1_SystemErrorCallback(void)
This is the default callback with weak attribute. The user can override and implement the default cal...
CAN1_IsRxErrorPassive
bool CAN1_IsRxErrorPassive(void)
Returns the receive error passive state.
Definition can1.c:931
CAN1_ModeChangeCallback
void CAN1_ModeChangeCallback(void)
This is the default callback with weak attribute. The user can override and implement the default cal...
CAN1_InvalidMessageCallback
void CAN1_InvalidMessageCallback(void)
This is the default callback with weak attribute. The user can override and implement the default cal...
CAN1_RxFifoSearch
static uint8_t CAN1_RxFifoSearch(uint8_t fifoNum)
This function Search the CAN1 receive FIFO channel index.
Definition can1.c:229
CAN1_IsTxErrorWarning
bool CAN1_IsTxErrorWarning(void)
Returns the transmit error warning state. If Transmitter error counter is above 95 to below 128,...
Definition can1.c:957
CAN1_ErrorNotificationEnable
static void CAN1_ErrorNotificationEnable(void)
This function enables the CAN1 error notification interrupt.
Definition can1.c:568
CAN1_MessageReadFromFifo
static void CAN1_MessageReadFromFifo(uint16_t *rxFifoObj, struct CAN_MSG_OBJ *rxCanMsg)
This function read the message object from receive FIFO and update to the user message object point...
Definition can1.c:347
CAN1_IsTxErrorPassive
bool CAN1_IsTxErrorPassive(void)
Returns the transmit error passive state.
Definition can1.c:952
CAN1_BitRateConfiguration
static void CAN1_BitRateConfiguration(void)
This function configure the CAN1 bit rate settings.
Definition can1.c:547
CAN1_ReceivedMessageCountGet
uint8_t CAN1_ReceivedMessageCountGet(void)
Returns the number of CAN messages received in all the FIFO.
Definition can1.c:854
CAN1_IsBusOff
bool CAN1_IsBusOff(void)
Returns the bus off status.
Definition can1.c:926
CAN1_BusErrorCallback
void CAN1_BusErrorCallback(void)
This is the default callback with weak attribute. The user can override and implement the default cal...
CAN1_RxBufferOverFlowCallback
void CAN1_RxBufferOverFlowCallback(void)
This is the default callback with weak attribute. The user can override and implement the default cal...
CAN1_Transmit
enum CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const enum CAN1_TX_FIFO_CHANNELS fifoChannel, struct CAN_MSG_OBJ *txCanMsg)
Writes the CAN message object to specified transmit FIFO channel.
Definition can1.c:788
CAN1_Initialize
void CAN1_Initialize(void)
Initializes CAN1 module.
Definition can1.c:581
CAN1_InvalidMessageCallbackRegister
void CAN1_InvalidMessageCallbackRegister(void(*handler)(void))
This function can be used to override default callback and to define custom callback for CAN1_Invalid...
Definition can1.c:985
CAN1_BusWakeUpActivityCallbackRegister
void CAN1_BusWakeUpActivityCallbackRegister(void(*handler)(void))
This function can be used to override default callback and to define custom callback for CAN1_BusWake...
Definition can1.c:998
CAN1_Deinitialize
void CAN1_Deinitialize(void)
Deinitializes CAN1 to POR values.
Definition can1.c:624
CAN1_TX_FIFO_MessageSendRequest
static void CAN1_TX_FIFO_MessageSendRequest(const enum CAN1_TX_FIFO_CHANNELS fifoChannel)
This function enables The FIFO transmit message send request bit.
Definition can1.c:326
CAN1_OperationModeGet
enum CAN_OP_MODES CAN1_OperationModeGet(void)
Get the CAN1 operation mode.
Definition can1.c:698
CAN1_TxAttemptCallbackRegister
void CAN1_TxAttemptCallbackRegister(void(*handler)(void))
This function can be used to override default callback and to define custom callback for CAN1_TxAttem...
Definition can1.c:1050
CAN1_OperationModeSet
enum CAN_OP_MODE_STATUS CAN1_OperationModeSet(const enum CAN_OP_MODES requestMode)
Sets the CAN1 operation mode.
Definition can1.c:671
CAN_INTERFACE
Structure containing the function pointers of CAN driver.
Definition can_interface.h:55
CAN_INTERFACE::Initialize
void(* Initialize)(void)
Pointer to CANx_Initialize e.g. CAN1_Initialize.
Definition can_interface.h:56
CAN_MSG_FIELD::frameType
unsigned int frameType
Definition can_types.h:55
CAN_MSG_FIELD::formatType
unsigned int formatType
Definition can_types.h:57
CAN_MSG_FIELD::dlc
unsigned int dlc
Definition can_types.h:56
CAN_MSG_FIELD::idType
unsigned int idType
Definition can_types.h:54
CAN_MSG_FIELD::brs
unsigned int brs
Definition can_types.h:58
CAN_MSG_OBJ
This data structure used to configure the CAN FD message object.
Definition can_types.h:68
CAN_MSG_OBJ::field
struct CAN_MSG_FIELD field
Definition can_types.h:70
CAN_MSG_OBJ::msgId
uint32_t msgId
Definition can_types.h:69
CAN_MSG_OBJ::data
uint8_t * data
Definition can_types.h:71
CAN1_FIFO_INFO
Definition can1.c:153
CAN1_FIFO_INFO::msgDeepSize
uint8_t msgDeepSize
Definition can1.c:155
CAN1_FIFO_INFO::payloadSize
uint8_t payloadSize
Definition can1.c:154
CAN1_FIFO_INFO::address
uint16_t * address
Definition can1.c:156