|  | Dual Active Bridge Development Board (Part-No. ) |
Content |  |  |  |  |  |

Loading...
Searching...
No Matches
clock.c
Go to the documentation of this file.
1
17/*
18© [2024] Microchip Technology Inc. and its subsidiaries.
19
20 Subject to your compliance with these terms, you may use Microchip
21 software and any derivatives exclusively with Microchip products.
22 You are responsible for complying with 3rd party license terms
23 applicable to your use of 3rd party software (including open source
24 software) that may accompany Microchip software. SOFTWARE IS ?AS IS.?
25 NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS
26 SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT,
27 MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
28 WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
29 INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY
30 KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
31 MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE
32 FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP?S
33 TOTAL LIABILITY ON ALL CLAIMS RELATED TO THE SOFTWARE WILL NOT
34 EXCEED AMOUNT OF FEES, IF ANY, YOU PAID DIRECTLY TO MICROCHIP FOR
35 THIS SOFTWARE.
36*/
37
38// Section: Includes
39#include <xc.h>
40#include <stdint.h>
41#include "../clock.h"
42
43 void CLOCK_Initialize(void)
44{
45 /*
46 Input frequency : 8.00 MHz
47 Clock source : FRC Oscillator with PLL
48 System frequency (Fosc) : 200.00 MHz [(8.00 MHz / 1) * 50 / 1 / 2 = 200.00 MHz]
49 PLL VCO frequency (Fvco) : 400.00 MHz [(8.00 MHz / 1) * 50 = 400.00 MHz]
50 PLL output frequency (Fpllo) : 400.00 MHz [(8.00 MHz / 1) * 50 / 1 = 400.00 MHz]
51 PLL VCO divider frequency (Fvcodiv) : 200.00 MHz [400.00 MHz / 2 = 200.00 MHz]
52 Clock switching enabled : true
53 Clock source when device boots : FRC Oscillator
54 Auxiliary clock source : FRC Oscillator with PLL
55 Auxiliary clock input frequency : 8.00 MHz
56 Auxiliary PLL VCO frequency (AFvco) : 1000.00 MHz [(8.00 MHz / 1) * 125 = 1000.00 MHz]
57 Auxiliary clock PLL output frequency (AFpllo) : 500.00 MHz [(8.00 MHz / 1) * 125 / 2 = 500.00 MHz]
58 Auxiliary PLL VCO divider frequency (AFvcodiv): 500.00 MHz [1000.00 MHz / 2 = 500.00 MHz]
59 */
60 // RCDIV FRC/1; PLLPRE 1:1; DOZE 1:8; DOZEN disabled; ROI disabled;
61 CLKDIV = 0x3001;
62 // PLLDIV 50;
63 PLLFBD = 0x32;
64 // TUN Center frequency;
65 OSCTUN = 0x0;
66 // PLLPOST 1:1; VCODIV FVCO/2; POST2DIV 1:1;
67 PLLDIV = 0x211;
68 // ENAPLL enabled; FRCSEL FRC Oscillator; APLLPRE 1:1;
69 ACLKCON1 = 0x8101;
70 // APLLFBDIV 125;
71 APLLFBD1 = 0x7D;
72 // APSTSCLR 1:2; APOST2DIV 1:1; AVCODIV FVCO/2;
73 APLLDIV1 = 0x221;
74 // CANCLKEN enabled; CANCLKSEL FPLLO; CANCLKDIV Divide by 10;
75 CANCLKCON = 0x8209;
76 // ROEN disabled; DIVSWEN disabled; ROSLP disabled; ROSEL ; OE disabled; ROSIDL disabled;
77 REFOCONL = 0x0;
78 // RODIV 0;
79 REFOCONH = 0x0;
80 // ROTRIM 0;
81 REFOTRIMH = 0x0;
82 // IOLOCK disabled;
83 RPCON = 0x0;
84 // PMDLOCK disabled;
85 PMDCON = 0x0;
86 // ADC1MD enabled; T1MD enabled; U2MD enabled; U1MD enabled; SPI2MD enabled; SPI1MD enabled; QEIMD enabled; PWMMD enabled; I2C1MD enabled; C1MD enabled;
87 PMD1 = 0x0;
88 // CCP2MD enabled; CCP1MD enabled; CCP4MD enabled; CCP3MD enabled; CCP7MD enabled; CCP8MD enabled; CCP5MD enabled; CCP6MD enabled; CCP9MD enabled;
89 PMD2 = 0x0;
90 // U3MD enabled; CRCMD enabled; I2C2MD enabled; I2C3MD enabled; QEI2MD enabled; PMPMD enabled;
91 PMD3 = 0x0;
92 // REFOMD enabled;
93 PMD4 = 0x0;
94 // DMA1MD enabled; DMA2MD enabled; DMA3MD enabled; DMA0MD enabled; SPI3MD enabled;
95 PMD6 = 0x0;
96 // PTGMD enabled; CMP1MD enabled; CMP3MD enabled; CMP2MD enabled;
97 PMD7 = 0x0;
98 // DMTMD enabled; CLC3MD enabled; OPAMPMD enabled; BIASMD enabled; CLC4MD enabled; SENT1MD enabled; CLC1MD enabled; CLC2MD enabled; SENT2MD enabled;
99 PMD8 = 0x0;
100 // CF no clock failure; NOSC FRCPLL; CLKLOCK unlocked; OSWEN Switch is Complete;
101 __builtin_write_OSCCONH((uint8_t) (0x01));
102 __builtin_write_OSCCONL((uint8_t) (0x01));
103 // Wait for Clock switch to occur
104 while (OSCCONbits.OSWEN != 0);
105 while (OSCCONbits.LOCK != 1);
106}
107
108 bool CLOCK_AuxPllLockStatusGet(void)
109{
110 return ACLKCON1bits.APLLCK;
111}
112
CLOCK_AuxPllLockStatusGet
bool CLOCK_AuxPllLockStatusGet(void)
Returns Auxiliary PLL status.
Definition clock.c:108
CLOCK_Initialize
void CLOCK_Initialize(void)
Initializes all the INTERNAL OSCILLATOR sources and clock switch configurations.
Definition clock.c:43