|  | Dual Active Bridge Development Board (Part-No. ) |
Content |  |  |  |  |  |

Loading...
Searching...
No Matches
drv_mcc_extension_pwm.h
Go to the documentation of this file.
1
8#ifndef DRV_MCC_EXTENSION_PWM_H
9#define DRV_MCC_EXTENSION_PWM_H
10
11#include <xc.h>
12#include <stdint.h> // include standard integer data types
13#include <stdbool.h> // include standard boolean data types
14#include <stddef.h> // include standard definition data types
15
16// Identify the number of PWM in the device selected
17#if defined (PG8CONL)
18#define PWM_MAX_COUNT 8
19#elif defined (PG4CONL)
20#define PWM_MAX_COUNT 4
21#else
22#pragma message "selected device has no supported PWM generators"
23#endif
24
25
29 enum PWM_PCI_ACCEPTANCE_CRITERIA_e
30{
31 PWM_PCI_ACCEPT_LEVEL_SENSITIVE = 0,
32 PWM_PCI_ACCEPT_RISING_EDGE = 1,
33 PWM_PCI_ACCEPT_ANY_EDGE = 2,
34 PWM_PCI_ACCEPT_LATCHED = 3,
35 PWM_PCI_ACCEPT_LATCHED_RISING_EDGE = 4,
36 PWM_PCI_ACCEPT_LATCHED_ANY_EDGE = 5
37};
38
39 typedef enum PWM_PCI_ACCEPTANCE_CRITERIA_e PWM_PCI_ACCEPTANCE_CRITERIA_t;
40
41
42
51 inline static void PWM_PCI_Fault_AcceptanceCriteria(uint16_t pwmIndex,
52 PWM_PCI_ACCEPTANCE_CRITERIA_t acpSetting)
53{
54
55 switch (pwmIndex)
56 {
57 case 1:
58 PG1FPCIHbits.ACP = acpSetting;
59 break;
60 case 2:
61 PG2FPCIHbits.ACP = acpSetting;
62 break;
63 case 3:
64 PG3FPCIHbits.ACP = acpSetting;
65 break;
66 case 4:
67 PG4FPCIHbits.ACP = acpSetting;
68 break;
69 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
70 case 5:
71 PG5FPCIHbits.ACP = acpSetting;
72 break;
73 case 6:
74 PG6FPCIHbits.ACP = acpSetting;
75 break;
76 case 7:
77 PG7FPCIHbits.ACP = acpSetting;
78 break;
79 case 8:
80 PG8FPCIHbits.ACP = acpSetting;
81 break;
82 #endif
83 default:
84 break;
85 };
86}
87
88
98 inline static void PWM_PCI_Fault_AcceptanceQualiferInvert(uint16_t pwmIndex, bool invert)
99{
100 switch (pwmIndex)
101 {
102 case 1:
103 PG1FPCILbits.AQPS = (uint16_t)invert;
104 break;
105 case 2:
106 PG2FPCILbits.AQPS = (uint16_t)invert;
107 break;
108 case 3:
109 PG3FPCILbits.AQPS = (uint16_t)invert;
110 break;
111 case 4:
112 PG4FPCILbits.AQPS = (uint16_t)invert;
113 break;
114 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
115 case 5:
116 PG5FPCILbits.AQPS = (uint16_t)invert;
117 break;
118 case 6:
119 PG6FPCILbits.AQPS = (uint16_t)invert;
120 break;
121 case 7:
122 PG7FPCILbits.AQPS = (uint16_t)invert;
123 break;
124 case 8:
125 PG8FPCILbits.AQPS = (uint16_t)invert;
126 break;
127 #endif
128 default:
129 break;
130 };
131}
132
133
142 inline static void PWM_PCI_Sync_AcceptanceCriteria(uint16_t pwmIndex, PWM_PCI_ACCEPTANCE_CRITERIA_t acpSetting)
143{
144 switch (pwmIndex)
145 {
146 case 1:
147 PG1SPCIHbits.ACP = acpSetting;
148 break;
149 case 2:
150 PG2SPCIHbits.ACP = acpSetting;
151 break;
152 case 3:
153 PG3SPCIHbits.ACP = acpSetting;
154 break;
155 case 4:
156 PG4SPCIHbits.ACP = acpSetting;
157 break;
158 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
159 case 5:
160 PG5SPCIHbits.ACP = acpSetting;
161 break;
162 case 6:
163 PG6SPCIHbits.ACP = acpSetting;
164 break;
165 case 7:
166 PG7SPCIHbits.ACP = acpSetting;
167 break;
168 case 8:
169 PG8SPCIHbits.ACP = acpSetting;
170 break;
171 #endif
172 default:
173 break;
174
175 };
176}
177
178
182 enum PWM_PCI_TERMTIME_AFTER_EVENT_e
183{
184 PWM_PCI_TERMTIME_AFTER_EVENT_AT_EOC = 0,
185 PWM_PCI_TERMTIME_AFTER_EVENT_IMMEDIATE = 1
186};
187 typedef enum PWM_PCI_TERMTIME_AFTER_EVENT_e PWM_PCI_TERMTIME_AFTER_EVENT_t;
188
189
199 inline static void PWM_PCI_Fault_TimetoTerminateAfterEvent(uint16_t pwmIndex, PWM_PCI_TERMTIME_AFTER_EVENT_t faultTerm)
200{
201 switch (pwmIndex)
202 {
203 case 1:
204 PG1FPCILbits.TSYNCDIS = faultTerm;
205 break;
206 case 2:
207 PG2FPCILbits.TSYNCDIS = faultTerm;
208 break;
209 case 3:
210 PG3FPCILbits.TSYNCDIS = faultTerm;
211 break;
212 case 4:
213 PG4FPCILbits.TSYNCDIS = faultTerm;
214 break;
215 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
216 case 5:
217 PG5FPCILbits.TSYNCDIS = faultTerm;
218 break;
219 case 6:
220 PG6FPCILbits.TSYNCDIS = faultTerm;
221 break;
222 case 7:
223 PG7FPCILbits.TSYNCDIS = faultTerm;
224 break;
225 case 8:
226 PG8FPCILbits.TSYNCDIS = faultTerm;
227 break;
228 #endif
229 default:
230 break;
231
232 };
233}
234
235
245 inline static void PWM_PCI_Sync_TimetoTerminateAfterEvent(uint16_t pwmIndex, PWM_PCI_TERMTIME_AFTER_EVENT_t faultTerm)
246{
247 switch (pwmIndex)
248 {
249 case 1:
250 PG1SPCILbits.TSYNCDIS = faultTerm;
251 break;
252 case 2:
253 PG2SPCILbits.TSYNCDIS = faultTerm;
254 break;
255 case 3:
256 PG3SPCILbits.TSYNCDIS = faultTerm;
257 break;
258 case 4:
259 PG4SPCILbits.TSYNCDIS = faultTerm;
260 break;
261 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
262 case 5:
263 PG5SPCILbits.TSYNCDIS = faultTerm;
264 break;
265 case 6:
266 PG6SPCILbits.TSYNCDIS = faultTerm;
267 break;
268 case 7:
269 PG7SPCILbits.TSYNCDIS = faultTerm;
270 break;
271 case 8:
272 PG8SPCILbits.TSYNCDIS = faultTerm;
273 break;
274 #endif
275 default:
276 break;
277
278 };
279}
280
281
285 enum PWM_SOCS_e
286{
287 PWM_SOCS_SELF_TRIGGER = 0,
288 PWM_SOCS_PG1_OR_PG5 = 1,
289 PWM_SOCS_PG2_OR_PG6 = 2,
290 PWM_SOCS_PG3_OR_PG7 = 3,
291 PWM_SOCS_PG4_OR_PG8 = 4,
292 PWM_SOCS_TRIG_OR_PCI_SYNC = 15
293};
294 typedef enum PWM_SOCS_e PWM_SOCS_t;
295
296
305 inline static void PWM_StartOfCycleTrigger(uint16_t pwmIndex, PWM_SOCS_t triggerSource)
306{
307 switch (pwmIndex)
308 {
309 case 1:
310 PG1CONHbits.SOCS = triggerSource;
311 break;
312 case 2:
313 PG2CONHbits.SOCS = triggerSource;
314 break;
315 case 3:
316 PG3CONHbits.SOCS = triggerSource;
317 break;
318 case 4:
319 PG4CONHbits.SOCS = triggerSource;
320 break;
321 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
322 case 5:
323 PG5CONHbits.SOCS = triggerSource;
324 break;
325 case 6:
326 PG6CONHbits.SOCS = triggerSource;
327 break;
328 case 7:
329 PG7CONHbits.SOCS = triggerSource;
330 break;
331 case 8:
332 PG8CONHbits.SOCS = triggerSource;
333 break;
334 #endif
335 default:
336 break;
337 }
338}
339
340
353 inline static void PWM_UPDREQ_Broadcast_Enable(uint16_t pwmIndex, bool enable)
354{
355 uint16_t enable_ = (uint16_t)enable;
356 PG1CONHbits.MSTEN = enable_;
357
358 switch (pwmIndex)
359 {
360 case 1:
361 PG1CONHbits.MSTEN = enable_;
362 break;
363 case 2:
364 PG2CONHbits.MSTEN = enable_;
365 break;
366 case 3:
367 PG3CONHbits.MSTEN = enable_;
368 break;
369 case 4:
370 PG4CONHbits.MSTEN = enable_;
371 break;
372 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
373 case 5:
374 PG5CONHbits.MSTEN = enable_;
375 break;
376 case 6:
377 PG6CONHbits.MSTEN = enable_;
378 break;
379 case 7:
380 PG7CONHbits.MSTEN = enable_;
381 break;
382 case 8:
383 PG8CONHbits.MSTEN = enable_;
384 break;
385 #endif
386 default:
387 break;
388 }
389}
390
391
395 enum PWM_UPDMOD_e
396{
397 PWM_UPDMOD_SOC = 0,
398 PWM_UPDMOD_IMMEDIATE = 1,
399 PWM_UPDMOD_CLIENT_SOC = 2,
400 PWM_UPDMOD_CLIENT_IMMEDIATE = 3
401};
402 typedef enum PWM_UPDMOD_e PWM_UPDMOD_t;
403
404
417 inline static void PWM_Data_Update_Mode(uint16_t pwmIndex, PWM_UPDMOD_t updateMode)
418{
419 switch (pwmIndex)
420 {
421 case 1:
422 PG1CONHbits.UPDMOD = updateMode;
423 break;
424 case 2:
425 PG2CONHbits.UPDMOD = updateMode;
426 break;
427 case 3:
428 PG3CONHbits.UPDMOD = updateMode;
429 break;
430 case 4:
431 PG4CONHbits.UPDMOD = updateMode;
432 break;
433 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
434 case 5:
435 PG5CONHbits.UPDMOD = updateMode;
436 break;
437 case 6:
438 PG6CONHbits.UPDMOD = updateMode;
439 break;
440 case 7:
441 PG7CONHbits.UPDMOD = updateMode;
442 break;
443 case 8:
444 PG8CONHbits.UPDMOD = updateMode;
445 break;
446 #endif
447 default:
448 break;
449 }
450}
451
452
456 enum PWM_PCI_SOURCE_e
457{
458 PWM_PCI_SOURCE_PWM1 = 0,
459 PWM_PCI_SOURCE_PWM2 = 1,
460 PWM_PCI_SOURCE_PWM3 = 2,
461 PWM_PCI_SOURCE_PWM4 = 3,
462 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
463 PWM_PCI_SOURCE_PWM5 = 4,
464 PWM_PCI_SOURCE_PWM6 = 5,
465 PWM_PCI_SOURCE_PWM7 = 6,
466 PWM_PCI_SOURCE_PWM8 = 7
467 #endif
468};
469 typedef enum PWM_PCI_SOURCE_e PWM_PCI_SOURCE_t;
470
471
481 inline static void PWM_PCI_Source1(uint16_t pwmIndex, PWM_PCI_SOURCE_t pciSource)
482{
483 switch (pwmIndex)
484 {
485 case 1:
486 PG1LEBHbits.PWMPCI = (uint16_t)pciSource;
487 break;
488 case 2:
489 PG2LEBHbits.PWMPCI = (uint16_t)pciSource;
490 break;
491 case 3:
492 PG3LEBHbits.PWMPCI = (uint16_t)pciSource;
493 break;
494 case 4:
495 PG4LEBHbits.PWMPCI = (uint16_t)pciSource;
496 break;
497 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
498 case 5:
499 PG5LEBHbits.PWMPCI = (uint16_t)pciSource;
500 break;
501 case 6:
502 PG6LEBHbits.PWMPCI = (uint16_t)pciSource;
503 break;
504 case 7:
505 PG7LEBHbits.PWMPCI = (uint16_t)pciSource;
506 break;
507 case 8:
508 PG8LEBHbits.PWMPCI = (uint16_t)pciSource;
509 break;
510 #endif
511 default:
512 break;
513 }
514}
515
516
520 enum RPnR_SOURCE_e
521{
522 RPnR_SOURCE_DefaultPORT = 0,
523 RPnR_SOURCE_U1TX = 1,
524 RPnR_SOURCE_U1RTS = 2,
525 RPnR_SOURCE_U2TX = 3,
526 RPnR_SOURCE_U2RTS = 4,
527 RPnR_SOURCE_SDO1 = 5,
528 RPnR_SOURCE_SCK1 = 6,
529 RPnR_SOURCE_SS1 = 7,
530 RPnR_SOURCE_SDO2 = 8,
531 RPnR_SOURCE_SCK2 = 9,
532 RPnR_SOURCE_SS2 = 10,
533 RPnR_SOURCE_SDO3 = 11,
534 RPnR_SOURCE_SCK3 = 12,
535 RPnR_SOURCE_SS3 = 13,
536 RPnR_SOURCE_REFCLKO = 14,
537 RPnR_SOURCE_OCM1 = 15,
538 RPnR_SOURCE_OCM2 = 16,
539 RPnR_SOURCE_OCM3 = 17,
540 RPnR_SOURCE_OCM4 = 18,
541 RPnR_SOURCE_OCM5 = 19,
542 RPnR_SOURCE_OCM6 = 20,
543 RPnR_SOURCE_CAN1TX = 21,
544 RPnR_SOURCE_CMP1 = 23,
545 RPnR_SOURCE_CMP2 = 24,
546 RPnR_SOURCE_CMP3 = 25,
547 RPnR_SOURCE_U3TX = 27,
548 RPnR_SOURCE_U3RTS = 28,
549 RPnR_SOURCE_PWM4H = 34,
550 RPnR_SOURCE_PWM4L = 35,
551 RPnR_SOURCE_PWMEA = 36,
552 RPnR_SOURCE_PWMEB = 37,
553 RPnR_SOURCE_QEICMP1 = 38,
554 RPnR_SOURCE_QEICMP2 = 39,
555 RPnR_SOURCE_CLC1OUT = 40,
556 RPnR_SOURCE_CLC2OUT = 41,
557 RPnR_SOURCE_OCM7 = 42,
558 RPnR_SOURCE_OCM8 = 43,
559 RPnR_SOURCE_PWMEC = 44,
560 RPnR_SOURCE_PWMED = 45,
561 RPnR_SOURCE_PTGTRG24 = 46,
562 RPnR_SOURCE_PTGTRG25 = 47,
563 RPnR_SOURCE_SENT1OUT = 48,
564 RPnR_SOURCE_SENT2OUT = 49,
565 RPnR_SOURCE_MCCP9A = 50,
566 RPnR_SOURCE_MCCP9B = 51,
567 RPnR_SOURCE_MCCP9C = 52,
568 RPnR_SOURCE_MCCP9D = 53,
569 RPnR_SOURCE_MCCP9E = 54,
570 RPnR_SOURCE_MCCP9F = 55,
571 RPnR_SOURCE_CLC3OUT = 59,
572 RPnR_SOURCE_CLC4OUT = 60,
573 RPnR_SOURCE_U1DTR = 61,
574 RPnR_SOURCE_U2DTR = 62,
575 RPnR_SOURCE_U3DTR = 63
576};
577 typedef enum RPnR_SOURCE_e RPnR_SOURCE_t;
578
579
580
584 enum RPnR_VIRTUAL_PIN_e
585{
586 RPnR_VIRTUAL_PIN_RP176 = 0,
587 RPnR_VIRTUAL_PIN_RP177 = 1,
588 RPnR_VIRTUAL_PIN_RP178 = 2,
589 RPnR_VIRTUAL_PIN_RP179 = 3,
590 RPnR_VIRTUAL_PIN_RP180 = 4,
591 RPnR_VIRTUAL_PIN_RP181 = 5
592};
593 typedef enum RPnR_VIRTUAL_PIN_e RPnR_VIRTUAL_PIN_t;
594
595
610 inline static void RPnR_VirtualPin_Source(RPnR_VIRTUAL_PIN_t virtualPin, RPnR_SOURCE_t peripheral)
611{
612
613 __builtin_write_RPCON(0x0000); // unlock PPS
614
615 switch (virtualPin)
616 {
617 case RPnR_VIRTUAL_PIN_RP176:
618 RPOR24bits.RP176R = peripheral;
619 break;
620
621 case RPnR_VIRTUAL_PIN_RP177:
622 RPOR24bits.RP177R = peripheral;
623 break;
624
625 case RPnR_VIRTUAL_PIN_RP178:
626 RPOR25bits.RP178R = peripheral;
627 break;
628
629 case RPnR_VIRTUAL_PIN_RP179:
630 RPOR25bits.RP179R = peripheral;
631 break;
632
633 case RPnR_VIRTUAL_PIN_RP180:
634 RPOR26bits.RP180R = peripheral;
635 break;
636
637 case RPnR_VIRTUAL_PIN_RP181:
638 RPOR26bits.RP181R = peripheral;
639 break;
640
641 default:
642 break;
643 };
644
645 __builtin_write_RPCON(0x0800); // lock PPS
646}
647
648
652 enum RPx_INPUT_e
653{
654 RPx_INPUT_VSS = 0,
655 RPx_INPUT_CMP1 = 1,
656 RPx_INPUT_CMP2 = 2,
657 RPx_INPUT_CMP3 = 3,
658 RPx_INPUT_PTG_TRIG_26 = 6,
659 RPx_INPUT_PTG_TRIG_27 = 7,
660 RPx_INPUT_PWM_EVENT_C = 11,
661 RPx_INPUT_PWM_EVENT_D = 12,
662 RPx_INPUT_PWM_EVENT_E = 13,
663 RPx_INPUT_RP32 = 32,
664 RPx_INPUT_RP33 = 33,
665 RPx_INPUT_RP34 = 34,
666 RPx_INPUT_RP35 = 35,
667 RPx_INPUT_RP36 = 36,
668 RPx_INPUT_RP37 = 37,
669 RPx_INPUT_RP38 = 38,
670 RPx_INPUT_RP39 = 39,
671 RPx_INPUT_RP40 = 40,
672 RPx_INPUT_RP41 = 41,
673 RPx_INPUT_RP42 = 42,
674 RPx_INPUT_RP43 = 43,
675 RPx_INPUT_RP44 = 44,
676 RPx_INPUT_RP45 = 45,
677 RPx_INPUT_RP46 = 46,
678 RPx_INPUT_RP47 = 47,
679 RPx_INPUT_RP48 = 48,
680 RPx_INPUT_RP49 = 49,
681 RPx_INPUT_RP50 = 50,
682 RPx_INPUT_RP51 = 51,
683 RPx_INPUT_RP52 = 52,
684 RPx_INPUT_RP53 = 53,
685 RPx_INPUT_RP54 = 54,
686 RPx_INPUT_RP55 = 55,
687 RPx_INPUT_RP56 = 56,
688 RPx_INPUT_RP57 = 57,
689 RPx_INPUT_RP58 = 58,
690 RPx_INPUT_RP59 = 59,
691 RPx_INPUT_RP60 = 60,
692 RPx_INPUT_RP61 = 61,
693 RPx_INPUT_RP62 = 62,
694 RPx_INPUT_RP63 = 63,
695 RPx_INPUT_RP64 = 64,
696 RPx_INPUT_RP65 = 65,
697 RPx_INPUT_RP66 = 66,
698 RPx_INPUT_RP67 = 67,
699 RPx_INPUT_RP68 = 68,
700 RPx_INPUT_RP69 = 69,
701 RPx_INPUT_RP70 = 70,
702 RPx_INPUT_RP71 = 71,
703 RPx_INPUT_RP72 = 72,
704 RPx_INPUT_RP73 = 73,
705 RPx_INPUT_RP74 = 74,
706 RPx_INPUT_RP75 = 75,
707 RPx_INPUT_RP76 = 76,
708 RPx_INPUT_RP77 = 77,
709 RPx_INPUT_RP78 = 78,
710 RPx_INPUT_RP79 = 79,
711 RPx_INPUT_DAC3_pwm_req_on = 164,
712 RPx_INPUT_DAC3_pwm_req_off = 165,
713 RPx_INPUT_DAC2_pwm_req_on = 166,
714 RPx_INPUT_DAC2_pwm_req_off = 167,
715 RPx_INPUT_DAC1_pwm_req_on = 168,
716 RPx_INPUT_DAC1_pwm_req_off = 169,
717 RPx_INPUT_RP176 = 176,
718 RPx_INPUT_RP177 = 177,
719 RPx_INPUT_RP178 = 178,
720 RPx_INPUT_RP179 = 179,
721 RPx_INPUT_RP180 = 180,
722 RPx_INPUT_RP181 = 181
723};
724 typedef enum RPx_INPUT_e RPx_INPUT_t;
725
726
730 enum PWM_PCI_INPUT_e
731{
732 PWM_PCI_INPUT8 = 0,
733 PWM_PCI_INPUT9 = 1,
734 PWM_PCI_INPUT10 = 2,
735 PWM_PCI_INPUT11 = 3
736};
737 typedef enum PWM_PCI_INPUT_e PWM_PCI_INPUT_t;
738
739
748 inline static void PWM_PCI_INPUT_MaptoPin(PWM_PCI_INPUT_t pciIndex, RPx_INPUT_t pin)
749{
750 __builtin_write_RPCON(0x0000); // unlock PPS
751 switch (pciIndex)
752 {
753 case PWM_PCI_INPUT8:
754 RPINR12bits.PCI8R = pin;
755 break;
756
757 case PWM_PCI_INPUT9:
758 RPINR12bits.PCI9R = pin;
759 break;
760
761 case PWM_PCI_INPUT10:
762 RPINR13bits.PCI10R = pin;
763 break;
764
765 case PWM_PCI_INPUT11:
766 RPINR13bits.PCI11R = pin;
767 break;
768
769 default:
770 break;
771 };
772 __builtin_write_RPCON(0x0800); // lock PPS
773}
774
775
779 enum PWM_PCI_SOURCE_SELECT_e
780{
781 PWM_PCI_SOURCE_SELECT_CLC1 = 31,
782 // 30 is reserved
783 PWM_PCI_SOURCE_SELECT_CMP3 = 29,
784 PWM_PCI_SOURCE_SELECT_CMP2 = 28,
785 PWM_PCI_SOURCE_SELECT_CMP1 = 27,
786 PWM_PCI_SOURCE_SELECT_PWM_EVENT_D = 26,
787 PWM_PCI_SOURCE_SELECT_PWM_EVENT_C = 25,
788 PWM_PCI_SOURCE_SELECT_PWM_EVENT_B = 24,
789 PWM_PCI_SOURCE_SELECT_PWM_EVENT_A = 23,
790 PWM_PCI_SOURCE_SELECT_PCI22 = 22,
791 PWM_PCI_SOURCE_SELECT_PCI21 = 21,
792 PWM_PCI_SOURCE_SELECT_PCI20 = 20,
793 PWM_PCI_SOURCE_SELECT_PCI19 = 19,
794 PWM_PCI_SOURCE_SELECT_PCI18R = 18,
795 PWM_PCI_SOURCE_SELECT_PCI17R = 17,
796 PWM_PCI_SOURCE_SELECT_PCI16R = 16,
797 PWM_PCI_SOURCE_SELECT_PCI15R = 15,
798 PWM_PCI_SOURCE_SELECT_PCI14R = 14,
799 PWM_PCI_SOURCE_SELECT_PCI13R = 13,
800 PWM_PCI_SOURCE_SELECT_PCI12R = 12,
801 PWM_PCI_SOURCE_SELECT_PCI11R = 11,
802 PWM_PCI_SOURCE_SELECT_PCI10R = 10,
803 PWM_PCI_SOURCE_SELECT_PCI9R = 9,
804 PWM_PCI_SOURCE_SELECT_PCI8R = 8,
805 // 7 is reserved,
806 // 6 is reserved,
807 // 5 is reserved,
808 // 4 is reserved,
809 PWM_PCI_SOURCE_SELECT_COMBO_TRIG_B = 3,
810 PWM_PCI_SOURCE_SELECT_COMBO_TRIG_A = 2,
811 PWM_PCI_SOURCE_SELECT_PWMPCI_MUX = 1,
812 PWM_PCI_SOURCE_SELECT_TIED_TO_0 = 0
813};
814
815 typedef enum PWM_PCI_SOURCE_SELECT_e PWM_PCI_SOURCE_SELECT_t;
816
817
818
827 inline static void PWM_PCI_Sync_Source_Select(uint16_t pwmIndex, PWM_PCI_SOURCE_SELECT_t pciSource)
828{
829 switch (pwmIndex)
830 {
831 case 1:
832 PG1SPCILbits.PSS = pciSource;
833 break;
834 case 2:
835 PG2SPCILbits.PSS = pciSource;
836 break;
837 case 3:
838 PG3SPCILbits.PSS = pciSource;
839 break;
840 case 4:
841 PG4SPCILbits.PSS = pciSource;
842 break;
843 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
844 case 5:
845 PG5SPCILbits.PSS = pciSource;
846 break;
847 case 6:
848 PG6SPCILbits.PSS = pciSource;
849 break;
850 case 7:
851 PG7SPCILbits.PSS = pciSource;
852 break;
853 case 8:
854 PG8SPCILbits.PSS = pciSource;
855 break;
856 #endif
857 default:
858 break;
859 };
860}
861
862
863
868 enum PWM_PCI_ACCEPTANCE_QUALIFER_e
869{
870 PWM_PCI_ACCEPTANCE_QUALIFER_NONE = 0,
871 PWM_PCI_ACCEPTANCE_QUALIFER_DUTY = 1,
872 PWM_PCI_ACCEPTANCE_QUALIFER_LEB = 2,
873 PWM_PCI_ACCEPTANCE_QUALIFER_PWM = 3,
874 PWM_PCI_ACCEPTANCE_QUALIFER_PCI_PWMPCI = 4,
875 PWM_PCI_ACCEPTANCE_QUALIFER_PCI_SOURCE8 = 5,
876 PWM_PCI_ACCEPTANCE_QUALIFER_PCI_SOURCE9 = 6,
877 PWM_PCI_ACCEPTANCE_QUALIFER_SWPCI = 7
878};
879 typedef enum PWM_PCI_ACCEPTANCE_QUALIFER_e PWM_PCI_ACCEPTANCE_QUALIFER_t;
880
881
882
892 inline static void PWM_PCI_Fault_AcceptanceQualifierSource(uint16_t pwmIndex, PWM_PCI_ACCEPTANCE_QUALIFER_t source)
893{
894 switch (pwmIndex)
895 {
896 case 1:
897 PG1FPCILbits.AQSS = source;
898 break;
899 case 2:
900 PG2FPCILbits.AQSS = source;
901 break;
902 case 3:
903 PG3FPCILbits.AQSS = source;
904 break;
905 case 4:
906 PG4FPCILbits.AQSS = source;
907 break;
908 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
909 case 5:
910 PG5FPCILbits.AQSS = source;
911 break;
912 case 6:
913 PG6FPCILbits.AQSS = source;
914 break;
915 case 7:
916 PG7FPCILbits.AQSS = source;
917 break;
918 case 8:
919 PG8FPCILbits.AQSS = source;
920 break;
921 #endif
922 default:
923 break;
924 };
925}
926
927
931 enum PWM_TRIG_MODE_e
932{
933 PWM_TRIG_MODE_SINGLE = 0,
934 PWM_TRIG_MODE_RETRIGGERABLE = 1
935};
936 typedef enum PWM_TRIG_MODE_e PWM_TRIG_MODE_t;
937
938
947 inline static void PWM_Trigger_Mode(uint16_t pwmIndex, PWM_TRIG_MODE_t trigMode)
948{
949 switch (pwmIndex)
950 {
951 case 1:
952 PG1CONHbits.TRGMOD = trigMode;
953 break;
954 case 2:
955 PG2CONHbits.TRGMOD = trigMode;
956 break;
957 case 3:
958 PG3CONHbits.TRGMOD = trigMode;
959 break;
960 case 4:
961 PG4CONHbits.TRGMOD = trigMode;
962 break;
963 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
964 case 5:
965 PG5CONHbits.TRGMOD = trigMode;
966 break;
967 case 6:
968 PG6CONHbits.TRGMOD = trigMode;
969 break;
970 case 7:
971 PG7CONHbits.TRGMOD = trigMode;
972 break;
973 case 8:
974 PG8CONHbits.TRGMOD = trigMode;
975 break;
976 #endif
977 default:
978 break;
979 };
980}
981
982
986 enum PWM_PCI_TERM_e
987{
988 PWM_PCI_TERM_MANUAL = 0,
989 PWM_PCI_TERM_AUTO = 1,
990 PWM_PCI_TERM_PGxTRIGA = 2,
991 PWM_PCI_TERM_PGxTRIGB = 3,
992 PWM_PCI_TERM_PGxTRIGC = 4,
993 PWM_PCI_TERM_PCI_SOURCE1 = 5,
994 PWM_PCI_TERM_PCI_SOURCE8 = 6,
995 PWM_PCI_TERM_PCI_SOURCE9 = 7
996};
997 typedef enum PWM_PCI_TERM_e PWM_PCI_TERM_t;
998
999
1008 inline static void PWM_PCI_Sync_TerminationEventSelect(uint16_t pwmIndex, PWM_PCI_TERM_t termEvent)
1009{
1010 switch (pwmIndex)
1011 {
1012 case 1:
1013 PG1SPCILbits.TERM = termEvent;
1014 break;
1015 case 2:
1016 PG2SPCILbits.TERM = termEvent;
1017 break;
1018 case 3:
1019 PG3SPCILbits.TERM = termEvent;
1020 break;
1021 case 4:
1022 PG4SPCILbits.TERM = termEvent;
1023 break;
1024 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
1025 case 5:
1026 PG5SPCILbits.TERM = termEvent;
1027 break;
1028 case 6:
1029 PG6SPCILbits.TERM = termEvent;
1030 break;
1031 case 7:
1032 PG7SPCILbits.TERM = termEvent;
1033 break;
1034 case 8:
1035 PG8SPCILbits.TERM = termEvent;
1036 break;
1037 #endif
1038 default:
1039 break;
1040 };
1041}
1042
1043
1053 inline static void PWM_Swap_PWMxL_and_PWMxH(uint16_t pwmIndex, bool swapPWMH_PWML)
1054{
1055 switch (pwmIndex)
1056 {
1057 case 1:
1058 PG1IOCONLbits.SWAP = swapPWMH_PWML;
1059 break;
1060 case 2:
1061 PG2IOCONLbits.SWAP = swapPWMH_PWML;
1062 break;
1063 case 3:
1064 PG3IOCONLbits.SWAP = swapPWMH_PWML;
1065 break;
1066 case 4:
1067 PG4IOCONLbits.SWAP = swapPWMH_PWML;
1068 break;
1069 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
1070 case 5:
1071 PG5IOCONLbits.SWAP = swapPWMH_PWML;
1072 break;
1073 case 6:
1074 PG6IOCONLbits.SWAP = swapPWMH_PWML;
1075 break;
1076 case 7:
1077 PG7IOCONLbits.SWAP = swapPWMH_PWML;
1078 break;
1079 case 8:
1080 PG8IOCONLbits.SWAP = swapPWMH_PWML;
1081 break;
1082 #endif
1083 default:
1084 break;
1085 };
1086}
1087
1088
1092 enum PWM_EVENT_SOURCE_e
1093{
1094 PWM_EVENT_SOURCE_PGTRGSEL = 0,
1095 PWM_EVENT_SOURCE_PWM_GEN_OUTPUT = 1,
1096 PWM_EVENT_SOURCE_PCI_SYNC_ACTIVE = 2,
1097 PWM_EVENT_SOURCE_PCI_FF_ACTIVE = 3,
1098 PWM_EVENT_SOURCE_PCI_FF_CL_ACTIVE = 4,
1099 PWM_EVENT_SOURCE_PCI_FAULT_ACTIVE = 5,
1100 PWM_EVENT_SOURCE_CAHALF = 6,
1101 PWM_EVENT_SOURCE_STEER = 7,
1102 PWM_EVENT_SOURCE_ADC_TRIG1 = 8,
1103 PWM_EVENT_SOURCE_ADC_TRIG2 = 9,
1104 PWM_EVENT_SOURCE_HR_ERROR_EVENT = 15
1105};
1106 typedef enum PWM_EVENT_SOURCE_e PWM_EVENT_SOURCE_t;
1107
1108
1121 inline static void PWM_EVENTA_Configure( uint16_t pwmSource,
1122 PWM_EVENT_SOURCE_t eventSource,
1123 bool invert,
1124 bool outputEnable,
1125 bool stretchDisable,
1126 bool outputSync)
1127{
1128 {
1129 PWMEVTAbits.EVTAPGS = (pwmSource-1);
1130 PWMEVTAbits.EVTAOEN = outputEnable;
1131 PWMEVTAbits.EVTAPOL = invert;
1132 PWMEVTAbits.EVTASTRD = stretchDisable;
1133 PWMEVTAbits.EVTASYNC = outputSync;
1134 PWMEVTAbits.EVTASEL = eventSource;
1135 };
1136}
1137
1138
1142 enum PWM_UPDTRG_e
1143{
1144 PWM_UPDTRG_MANUAL = 0,
1145 PWM_UPDTRG_PGxDC = 1,
1146 PWM_UPDTRG_PGxPHASE = 2,
1147 PWM_UPDTRG_PGxTRIGA = 3
1148};
1149 typedef enum PWM_UPDTRG_e PWM_UPDTRG_t;
1150
1151
1161 inline static void PWM_Data_Update_Trigger(uint16_t pwmIndex, PWM_UPDTRG_t updateTrigger)
1162{
1163 switch (pwmIndex)
1164 {
1165 case 1:
1166 PG1EVTLbits.UPDTRG = (uint16_t)updateTrigger;
1167 break;
1168 case 2:
1169 PG2EVTLbits.UPDTRG = (uint16_t)updateTrigger;
1170 break;
1171 case 3:
1172 PG3EVTLbits.UPDTRG = (uint16_t)updateTrigger;
1173 break;
1174 case 4:
1175 PG4EVTLbits.UPDTRG = (uint16_t)updateTrigger;
1176 break;
1177 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
1178 case 5:
1179 PG5EVTLbits.UPDTRG = (uint16_t)updateTrigger;
1180 break;
1181 case 6:
1182 PG6EVTLbits.UPDTRG = (uint16_t)updateTrigger;
1183 break;
1184 case 7:
1185 PG7EVTLbits.UPDTRG = (uint16_t)updateTrigger;
1186 break;
1187 case 8:
1188 PG8EVTLbits.UPDTRG = (uint16_t)updateTrigger;
1189 break;
1190 #endif
1191 default:
1192 break;
1193 }
1194}
1195
1196
1200 enum PWM_LATCH_MODE_e
1201{
1202 PWM_SET_DOMINANT_MODE = 0,
1203 PWM_RESET_DOMINANT_MODE = 1
1204};
1205 typedef enum PWM_LATCH_MODE_e PWM_LATCH_MODE_t;
1206
1207
1216 inline static void PWM_Fault_LatchMode(uint16_t pwmIndex, PWM_LATCH_MODE_t latchMode)
1217{
1218 switch (pwmIndex)
1219 {
1220 case 1:
1221 PG1FPCIHbits.LATMOD = latchMode;
1222 break;
1223 case 2:
1224 PG2FPCIHbits.LATMOD = latchMode;
1225 break;
1226 case 3:
1227 PG3FPCIHbits.LATMOD = latchMode;
1228 break;
1229 case 4:
1230 PG4FPCIHbits.LATMOD = latchMode;
1231 break;
1232 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
1233 case 5:
1234 PG5FPCIHbits.LATMOD = latchMode;
1235 break;
1236 case 6:
1237 PG6FPCIHbits.LATMOD = latchMode;
1238 break;
1239 case 7:
1240 PG7FPCIHbits.LATMOD = latchMode;
1241 break;
1242 case 8:
1243 PG8FPCIHbits.LATMOD = latchMode;
1244 break;
1245 #endif
1246 default:
1247 break;
1248 };
1249}
1250
1251
1255 enum PWM_FAULT_DATA_e
1256{
1257 PWM_FAULT_EVENT_PWMH = 0,
1258 PWM_FAULT_EVENT_PWML = 1
1259};
1260 typedef enum PWM_FAULT_DATA_e PWM_FAULT_DATA_t;
1261
1262
1271 inline static void PWM_Fault_DataMode(uint16_t pwmIndex, PWM_FAULT_DATA_t faultDataMode)
1272{
1273 switch (pwmIndex)
1274 {
1275 case 1:
1276 PG1IOCONLbits.FLTDAT = faultDataMode;
1277 break;
1278 case 2:
1279 PG2IOCONLbits.FLTDAT = faultDataMode;
1280 break;
1281 case 3:
1282 PG3IOCONLbits.FLTDAT = faultDataMode;
1283 break;
1284 case 4:
1285 PG4IOCONLbits.FLTDAT= faultDataMode;
1286 break;
1287 #if defined(PWM_MAX_COUNT) && (PWM_MAX_COUNT == 8)
1288 case 5:
1289 PG5IOCONLbits.FLTDAT = faultDataMode;
1290 break;
1291 case 6:
1292 PG6IOCONLbits.FLTDAT = faultDataMode;
1293 break;
1294 case 7:
1295 PG7IOCONLbits.FLTDAT = faultDataMode;
1296 break;
1297 case 8:
1298 PG8IOCONLbits.FLTDAT = faultDataMode;
1299 break;
1300 #endif
1301 default:
1302 break;
1303 };
1304}
1305
1306#endif /* DRV_MCC_EXTENSION_PWM_H */
1307
PWM_PCI_TERM_t
enum PWM_PCI_TERM_e PWM_PCI_TERM_t
Definition drv_mcc_extension_pwm.h:997
PWM_PCI_SOURCE_t
enum PWM_PCI_SOURCE_e PWM_PCI_SOURCE_t
Definition drv_mcc_extension_pwm.h:469
PWM_SOCS_t
enum PWM_SOCS_e PWM_SOCS_t
Definition drv_mcc_extension_pwm.h:294
PWM_PCI_ACCEPTANCE_CRITERIA_t
enum PWM_PCI_ACCEPTANCE_CRITERIA_e PWM_PCI_ACCEPTANCE_CRITERIA_t
Definition drv_mcc_extension_pwm.h:39
PWM_PCI_ACCEPTANCE_QUALIFER_t
enum PWM_PCI_ACCEPTANCE_QUALIFER_e PWM_PCI_ACCEPTANCE_QUALIFER_t
Definition drv_mcc_extension_pwm.h:879
PWM_PCI_INPUT_t
enum PWM_PCI_INPUT_e PWM_PCI_INPUT_t
Definition drv_mcc_extension_pwm.h:737
RPnR_VIRTUAL_PIN_t
enum RPnR_VIRTUAL_PIN_e RPnR_VIRTUAL_PIN_t
Definition drv_mcc_extension_pwm.h:593
RPnR_SOURCE_t
enum RPnR_SOURCE_e RPnR_SOURCE_t
Definition drv_mcc_extension_pwm.h:577
RPx_INPUT_t
enum RPx_INPUT_e RPx_INPUT_t
Definition drv_mcc_extension_pwm.h:724
PWM_PCI_SOURCE_SELECT_t
enum PWM_PCI_SOURCE_SELECT_e PWM_PCI_SOURCE_SELECT_t
Definition drv_mcc_extension_pwm.h:815
PWM_UPDTRG_t
enum PWM_UPDTRG_e PWM_UPDTRG_t
Definition drv_mcc_extension_pwm.h:1149
PWM_TRIG_MODE_t
enum PWM_TRIG_MODE_e PWM_TRIG_MODE_t
Definition drv_mcc_extension_pwm.h:936
PWM_LATCH_MODE_t
enum PWM_LATCH_MODE_e PWM_LATCH_MODE_t
Definition drv_mcc_extension_pwm.h:1205
PWM_FAULT_DATA_t
enum PWM_FAULT_DATA_e PWM_FAULT_DATA_t
Definition drv_mcc_extension_pwm.h:1260
PWM_PCI_TERMTIME_AFTER_EVENT_t
enum PWM_PCI_TERMTIME_AFTER_EVENT_e PWM_PCI_TERMTIME_AFTER_EVENT_t
Definition drv_mcc_extension_pwm.h:187
PWM_UPDMOD_t
enum PWM_UPDMOD_e PWM_UPDMOD_t
Definition drv_mcc_extension_pwm.h:402
PWM_EVENT_SOURCE_t
enum PWM_EVENT_SOURCE_e PWM_EVENT_SOURCE_t
Definition drv_mcc_extension_pwm.h:1106
PWM_UPDMOD_e
PWM_UPDMOD_e
settings for PWM Buffer Update Mode Selection bits
Definition drv_mcc_extension_pwm.h:396
RPx_INPUT_e
RPx_INPUT_e
List of output selection for re-mappable pins (taken from dsPIC33CK256MP508 datasheet)
Definition drv_mcc_extension_pwm.h:653
PWM_PCI_Sync_TerminationEventSelect
static void PWM_PCI_Sync_TerminationEventSelect(uint16_t pwmIndex, PWM_PCI_TERM_t termEvent)
Select termination event for SYNC PCI.
Definition drv_mcc_extension_pwm.h:1008
PWM_SOCS_e
PWM_SOCS_e
Settings for PWM Start-of_cycle Selection bit.
Definition drv_mcc_extension_pwm.h:286
PWM_Data_Update_Mode
static void PWM_Data_Update_Mode(uint16_t pwmIndex, PWM_UPDMOD_t updateMode)
Sets the PWM Data Update Mode.
Definition drv_mcc_extension_pwm.h:417
PWM_StartOfCycleTrigger
static void PWM_StartOfCycleTrigger(uint16_t pwmIndex, PWM_SOCS_t triggerSource)
Set SOCS field to determine start of cycle trigger.
Definition drv_mcc_extension_pwm.h:305
RPnR_VirtualPin_Source
static void RPnR_VirtualPin_Source(RPnR_VIRTUAL_PIN_t virtualPin, RPnR_SOURCE_t peripheral)
Set source for a virtual pin.
Definition drv_mcc_extension_pwm.h:610
PWM_PCI_Fault_AcceptanceCriteria
static void PWM_PCI_Fault_AcceptanceCriteria(uint16_t pwmIndex, PWM_PCI_ACCEPTANCE_CRITERIA_t acpSetting)
Set PCI fault acceptance criteria.
Definition drv_mcc_extension_pwm.h:51
PWM_Fault_LatchMode
static void PWM_Fault_LatchMode(uint16_t pwmIndex, PWM_LATCH_MODE_t latchMode)
Set the latch mode of fault PCI.
Definition drv_mcc_extension_pwm.h:1216
PWM_PCI_Fault_TimetoTerminateAfterEvent
static void PWM_PCI_Fault_TimetoTerminateAfterEvent(uint16_t pwmIndex, PWM_PCI_TERMTIME_AFTER_EVENT_t faultTerm)
Set TSYNCDIS bit to determine when PWM should stop after a fault occurs.
Definition drv_mcc_extension_pwm.h:199
PWM_EVENTA_Configure
static void PWM_EVENTA_Configure(uint16_t pwmSource, PWM_EVENT_SOURCE_t eventSource, bool invert, bool outputEnable, bool stretchDisable, bool outputSync)
Configure PWM Event A register.
Definition drv_mcc_extension_pwm.h:1121
PWM_PCI_TERMTIME_AFTER_EVENT_e
PWM_PCI_TERMTIME_AFTER_EVENT_e
Settings for Termination Synchronization bit.
Definition drv_mcc_extension_pwm.h:183
PWM_PCI_INPUT_MaptoPin
static void PWM_PCI_INPUT_MaptoPin(PWM_PCI_INPUT_t pciIndex, RPx_INPUT_t pin)
Map PWM PCI input to a pin.
Definition drv_mcc_extension_pwm.h:748
PWM_Trigger_Mode
static void PWM_Trigger_Mode(uint16_t pwmIndex, PWM_TRIG_MODE_t trigMode)
Set source of fault PCI acceptance qualifier.
Definition drv_mcc_extension_pwm.h:947
PWM_LATCH_MODE_e
PWM_LATCH_MODE_e
Set PWM trigger mode.
Definition drv_mcc_extension_pwm.h:1201
PWM_PCI_Sync_TimetoTerminateAfterEvent
static void PWM_PCI_Sync_TimetoTerminateAfterEvent(uint16_t pwmIndex, PWM_PCI_TERMTIME_AFTER_EVENT_t faultTerm)
Set TSYNCDIS bit to determine when PWM should stop after a sync event occurs.
Definition drv_mcc_extension_pwm.h:245
PWM_PCI_Source1
static void PWM_PCI_Source1(uint16_t pwmIndex, PWM_PCI_SOURCE_t pciSource)
Set PWM source for PCI selection bits (for PCI source 1)
Definition drv_mcc_extension_pwm.h:481
PWM_FAULT_DATA_e
PWM_FAULT_DATA_e
Set PWM fault data.
Definition drv_mcc_extension_pwm.h:1256
PWM_PCI_SOURCE_e
PWM_PCI_SOURCE_e
Settings for PWM Source for PCI Selection bits.
Definition drv_mcc_extension_pwm.h:457
RPnR_SOURCE_e
RPnR_SOURCE_e
Peripheral output for re-mappable pins.
Definition drv_mcc_extension_pwm.h:521
PWM_PCI_TERM_e
PWM_PCI_TERM_e
PWM Termination event selection.
Definition drv_mcc_extension_pwm.h:987
PWM_UPDREQ_Broadcast_Enable
static void PWM_UPDREQ_Broadcast_Enable(uint16_t pwmIndex, bool enable)
Enable broadcasting of UPDREQ bit to other PWMs.
Definition drv_mcc_extension_pwm.h:353
PWM_Data_Update_Trigger
static void PWM_Data_Update_Trigger(uint16_t pwmIndex, PWM_UPDTRG_t updateTrigger)
Set PWM Register update trigger.
Definition drv_mcc_extension_pwm.h:1161
PWM_Swap_PWMxL_and_PWMxH
static void PWM_Swap_PWMxL_and_PWMxH(uint16_t pwmIndex, bool swapPWMH_PWML)
Enable/Disable the PWM instance output swap bit.
Definition drv_mcc_extension_pwm.h:1053
PWM_PCI_Sync_Source_Select
static void PWM_PCI_Sync_Source_Select(uint16_t pwmIndex, PWM_PCI_SOURCE_SELECT_t pciSource)
Set PCI source (PSS field) for PCI Synchronization.
Definition drv_mcc_extension_pwm.h:827
PWM_Fault_DataMode
static void PWM_Fault_DataMode(uint16_t pwmIndex, PWM_FAULT_DATA_t faultDataMode)
Set the data mode of fault PCI.
Definition drv_mcc_extension_pwm.h:1271
PWM_PCI_Sync_AcceptanceCriteria
static void PWM_PCI_Sync_AcceptanceCriteria(uint16_t pwmIndex, PWM_PCI_ACCEPTANCE_CRITERIA_t acpSetting)
Sets PCI Synchronization Acceptance Criteria.
Definition drv_mcc_extension_pwm.h:142
PWM_EVENT_SOURCE_e
PWM_EVENT_SOURCE_e
Select event source for PWMEVTx register.
Definition drv_mcc_extension_pwm.h:1093
PWM_PCI_ACCEPTANCE_QUALIFER_e
PWM_PCI_ACCEPTANCE_QUALIFER_e
List of sources of PWM acceptance qualifiers.
Definition drv_mcc_extension_pwm.h:869
PWM_PCI_SOURCE_SELECT_e
PWM_PCI_SOURCE_SELECT_e
List of PWM PCI inputs.
Definition drv_mcc_extension_pwm.h:780
PWM_PCI_Fault_AcceptanceQualifierSource
static void PWM_PCI_Fault_AcceptanceQualifierSource(uint16_t pwmIndex, PWM_PCI_ACCEPTANCE_QUALIFER_t source)
Set source of fault PCI acceptance qualifier.
Definition drv_mcc_extension_pwm.h:892
PWM_PCI_Fault_AcceptanceQualiferInvert
static void PWM_PCI_Fault_AcceptanceQualiferInvert(uint16_t pwmIndex, bool invert)
Set PCI polarity of PCI fault acceptance input.
Definition drv_mcc_extension_pwm.h:98
PWM_PCI_INPUT_e
PWM_PCI_INPUT_e
list of PWM PCI inputs
Definition drv_mcc_extension_pwm.h:731
PWM_UPDTRG_e
PWM_UPDTRG_e
Settings for Update Trigger Event.
Definition drv_mcc_extension_pwm.h:1143
RPnR_VIRTUAL_PIN_e
RPnR_VIRTUAL_PIN_e
List of re-mappable pins for dsPIC33CK256MP508.
Definition drv_mcc_extension_pwm.h:585
PWM_PCI_ACCEPTANCE_CRITERIA_e
PWM_PCI_ACCEPTANCE_CRITERIA_e
Set PCI fault acceptance criteria.
Definition drv_mcc_extension_pwm.h:30
PWM_TRIG_MODE_e
PWM_TRIG_MODE_e
Set PWM trigger mode.
Definition drv_mcc_extension_pwm.h:932
PWM_UPDMOD_SOC
@ PWM_UPDMOD_SOC
Definition drv_mcc_extension_pwm.h:397
PWM_UPDMOD_IMMEDIATE
@ PWM_UPDMOD_IMMEDIATE
Definition drv_mcc_extension_pwm.h:398
PWM_UPDMOD_CLIENT_SOC
@ PWM_UPDMOD_CLIENT_SOC
Definition drv_mcc_extension_pwm.h:399
PWM_UPDMOD_CLIENT_IMMEDIATE
@ PWM_UPDMOD_CLIENT_IMMEDIATE
Definition drv_mcc_extension_pwm.h:400
RPx_INPUT_RP74
@ RPx_INPUT_RP74
Port Pin RD10.
Definition drv_mcc_extension_pwm.h:705
RPx_INPUT_RP62
@ RPx_INPUT_RP62
Port Pin RC14.
Definition drv_mcc_extension_pwm.h:693
RPx_INPUT_RP63
@ RPx_INPUT_RP63
Port Pin RC15.
Definition drv_mcc_extension_pwm.h:694
RPx_INPUT_RP67
@ RPx_INPUT_RP67
Port Pin RD3.
Definition drv_mcc_extension_pwm.h:698
RPx_INPUT_RP65
@ RPx_INPUT_RP65
Port Pin RD1.
Definition drv_mcc_extension_pwm.h:696
RPx_INPUT_RP46
@ RPx_INPUT_RP46
Port Pin RB14.
Definition drv_mcc_extension_pwm.h:677
RPx_INPUT_RP181
@ RPx_INPUT_RP181
Virtual RPV5.
Definition drv_mcc_extension_pwm.h:722
RPx_INPUT_RP79
@ RPx_INPUT_RP79
Port Pin RD15.
Definition drv_mcc_extension_pwm.h:710
RPx_INPUT_RP35
@ RPx_INPUT_RP35
Port Pin RB3.
Definition drv_mcc_extension_pwm.h:666
RPx_INPUT_RP178
@ RPx_INPUT_RP178
Virtual RPV2.
Definition drv_mcc_extension_pwm.h:719
RPx_INPUT_RP44
@ RPx_INPUT_RP44
Port Pin RB12.
Definition drv_mcc_extension_pwm.h:675
RPx_INPUT_RP51
@ RPx_INPUT_RP51
Port Pin RC3.
Definition drv_mcc_extension_pwm.h:682
RPx_INPUT_CMP1
@ RPx_INPUT_CMP1
Internal.
Definition drv_mcc_extension_pwm.h:655
RPx_INPUT_RP39
@ RPx_INPUT_RP39
Port Pin RB7.
Definition drv_mcc_extension_pwm.h:670
RPx_INPUT_RP34
@ RPx_INPUT_RP34
Port Pin RB2.
Definition drv_mcc_extension_pwm.h:665
RPx_INPUT_RP180
@ RPx_INPUT_RP180
Virtual RPV4.
Definition drv_mcc_extension_pwm.h:721
RPx_INPUT_PWM_EVENT_D
@ RPx_INPUT_PWM_EVENT_D
Internal.
Definition drv_mcc_extension_pwm.h:661
RPx_INPUT_RP50
@ RPx_INPUT_RP50
Port Pin RC2.
Definition drv_mcc_extension_pwm.h:681
RPx_INPUT_RP73
@ RPx_INPUT_RP73
Port Pin RD9.
Definition drv_mcc_extension_pwm.h:704
RPx_INPUT_DAC1_pwm_req_on
@ RPx_INPUT_DAC1_pwm_req_on
Internal.
Definition drv_mcc_extension_pwm.h:715
RPx_INPUT_RP68
@ RPx_INPUT_RP68
Port Pin RD4.
Definition drv_mcc_extension_pwm.h:699
RPx_INPUT_RP43
@ RPx_INPUT_RP43
Port Pin RB11.
Definition drv_mcc_extension_pwm.h:674
RPx_INPUT_DAC1_pwm_req_off
@ RPx_INPUT_DAC1_pwm_req_off
Internal.
Definition drv_mcc_extension_pwm.h:716
RPx_INPUT_RP179
@ RPx_INPUT_RP179
Virtual RPV3.
Definition drv_mcc_extension_pwm.h:720
RPx_INPUT_RP71
@ RPx_INPUT_RP71
Port Pin RD7.
Definition drv_mcc_extension_pwm.h:702
RPx_INPUT_RP60
@ RPx_INPUT_RP60
Port Pin RC12.
Definition drv_mcc_extension_pwm.h:691
RPx_INPUT_RP37
@ RPx_INPUT_RP37
Port Pin RB5.
Definition drv_mcc_extension_pwm.h:668
RPx_INPUT_RP76
@ RPx_INPUT_RP76
Port Pin RD12.
Definition drv_mcc_extension_pwm.h:707
RPx_INPUT_RP33
@ RPx_INPUT_RP33
Port Pin RB1.
Definition drv_mcc_extension_pwm.h:664
RPx_INPUT_RP53
@ RPx_INPUT_RP53
Port Pin RC5.
Definition drv_mcc_extension_pwm.h:684
RPx_INPUT_RP36
@ RPx_INPUT_RP36
Port Pin RB4.
Definition drv_mcc_extension_pwm.h:667
RPx_INPUT_RP41
@ RPx_INPUT_RP41
Port Pin RB9.
Definition drv_mcc_extension_pwm.h:672
RPx_INPUT_RP52
@ RPx_INPUT_RP52
Port Pin RC4.
Definition drv_mcc_extension_pwm.h:683
RPx_INPUT_VSS
@ RPx_INPUT_VSS
Internal.
Definition drv_mcc_extension_pwm.h:654
RPx_INPUT_RP45
@ RPx_INPUT_RP45
Port Pin RB13.
Definition drv_mcc_extension_pwm.h:676
RPx_INPUT_CMP2
@ RPx_INPUT_CMP2
Internal.
Definition drv_mcc_extension_pwm.h:656
RPx_INPUT_RP70
@ RPx_INPUT_RP70
Port Pin RD6.
Definition drv_mcc_extension_pwm.h:701
RPx_INPUT_RP64
@ RPx_INPUT_RP64
Port Pin RD0.
Definition drv_mcc_extension_pwm.h:695
RPx_INPUT_RP59
@ RPx_INPUT_RP59
Port Pin RC11.
Definition drv_mcc_extension_pwm.h:690
RPx_INPUT_RP57
@ RPx_INPUT_RP57
Port Pin RC9.
Definition drv_mcc_extension_pwm.h:688
RPx_INPUT_RP40
@ RPx_INPUT_RP40
Port Pin RB8.
Definition drv_mcc_extension_pwm.h:671
RPx_INPUT_CMP3
@ RPx_INPUT_CMP3
Internal.
Definition drv_mcc_extension_pwm.h:657
RPx_INPUT_DAC2_pwm_req_on
@ RPx_INPUT_DAC2_pwm_req_on
Internal.
Definition drv_mcc_extension_pwm.h:713
RPx_INPUT_DAC2_pwm_req_off
@ RPx_INPUT_DAC2_pwm_req_off
Internal.
Definition drv_mcc_extension_pwm.h:714
RPx_INPUT_PTG_TRIG_27
@ RPx_INPUT_PTG_TRIG_27
Internal.
Definition drv_mcc_extension_pwm.h:659
RPx_INPUT_DAC3_pwm_req_off
@ RPx_INPUT_DAC3_pwm_req_off
Internal.
Definition drv_mcc_extension_pwm.h:712
RPx_INPUT_PTG_TRIG_26
@ RPx_INPUT_PTG_TRIG_26
Internal.
Definition drv_mcc_extension_pwm.h:658
RPx_INPUT_RP77
@ RPx_INPUT_RP77
Port Pin RD13.
Definition drv_mcc_extension_pwm.h:708
RPx_INPUT_RP72
@ RPx_INPUT_RP72
Port Pin RD8.
Definition drv_mcc_extension_pwm.h:703
RPx_INPUT_RP38
@ RPx_INPUT_RP38
Port Pin RB6.
Definition drv_mcc_extension_pwm.h:669
RPx_INPUT_RP47
@ RPx_INPUT_RP47
Port Pin RB15.
Definition drv_mcc_extension_pwm.h:678
RPx_INPUT_RP58
@ RPx_INPUT_RP58
Port Pin RC10.
Definition drv_mcc_extension_pwm.h:689
RPx_INPUT_RP32
@ RPx_INPUT_RP32
Port Pin RB0.
Definition drv_mcc_extension_pwm.h:663
RPx_INPUT_RP48
@ RPx_INPUT_RP48
Port Pin RC0.
Definition drv_mcc_extension_pwm.h:679
RPx_INPUT_RP78
@ RPx_INPUT_RP78
Port Pin RD14.
Definition drv_mcc_extension_pwm.h:709
RPx_INPUT_RP177
@ RPx_INPUT_RP177
Virtual RPV1.
Definition drv_mcc_extension_pwm.h:718
RPx_INPUT_RP176
@ RPx_INPUT_RP176
Virtual RPV0.
Definition drv_mcc_extension_pwm.h:717
RPx_INPUT_RP56
@ RPx_INPUT_RP56
Port Pin RC8.
Definition drv_mcc_extension_pwm.h:687
RPx_INPUT_RP61
@ RPx_INPUT_RP61
Port Pin RC13.
Definition drv_mcc_extension_pwm.h:692
RPx_INPUT_RP66
@ RPx_INPUT_RP66
Port Pin RD2.
Definition drv_mcc_extension_pwm.h:697
RPx_INPUT_DAC3_pwm_req_on
@ RPx_INPUT_DAC3_pwm_req_on
Internal.
Definition drv_mcc_extension_pwm.h:711
RPx_INPUT_RP69
@ RPx_INPUT_RP69
Port Pin RD5.
Definition drv_mcc_extension_pwm.h:700
RPx_INPUT_RP49
@ RPx_INPUT_RP49
Port Pin RC1.
Definition drv_mcc_extension_pwm.h:680
RPx_INPUT_RP42
@ RPx_INPUT_RP42
Port Pin RB10.
Definition drv_mcc_extension_pwm.h:673
RPx_INPUT_RP75
@ RPx_INPUT_RP75
Port Pin RD11.
Definition drv_mcc_extension_pwm.h:706
RPx_INPUT_PWM_EVENT_E
@ RPx_INPUT_PWM_EVENT_E
Internal.
Definition drv_mcc_extension_pwm.h:662
RPx_INPUT_RP55
@ RPx_INPUT_RP55
Port Pin RC7.
Definition drv_mcc_extension_pwm.h:686
RPx_INPUT_PWM_EVENT_C
@ RPx_INPUT_PWM_EVENT_C
Internal.
Definition drv_mcc_extension_pwm.h:660
RPx_INPUT_RP54
@ RPx_INPUT_RP54
Port Pin RC6.
Definition drv_mcc_extension_pwm.h:685
PWM_SOCS_PG3_OR_PG7
@ PWM_SOCS_PG3_OR_PG7
Definition drv_mcc_extension_pwm.h:290
PWM_SOCS_SELF_TRIGGER
@ PWM_SOCS_SELF_TRIGGER
Definition drv_mcc_extension_pwm.h:287
PWM_SOCS_PG2_OR_PG6
@ PWM_SOCS_PG2_OR_PG6
Definition drv_mcc_extension_pwm.h:289
PWM_SOCS_PG4_OR_PG8
@ PWM_SOCS_PG4_OR_PG8
Definition drv_mcc_extension_pwm.h:291
PWM_SOCS_PG1_OR_PG5
@ PWM_SOCS_PG1_OR_PG5
Definition drv_mcc_extension_pwm.h:288
PWM_SOCS_TRIG_OR_PCI_SYNC
@ PWM_SOCS_TRIG_OR_PCI_SYNC
Definition drv_mcc_extension_pwm.h:292
PWM_PCI_TERMTIME_AFTER_EVENT_AT_EOC
@ PWM_PCI_TERMTIME_AFTER_EVENT_AT_EOC
Definition drv_mcc_extension_pwm.h:184
PWM_PCI_TERMTIME_AFTER_EVENT_IMMEDIATE
@ PWM_PCI_TERMTIME_AFTER_EVENT_IMMEDIATE
Definition drv_mcc_extension_pwm.h:185
PWM_RESET_DOMINANT_MODE
@ PWM_RESET_DOMINANT_MODE
Definition drv_mcc_extension_pwm.h:1203
PWM_SET_DOMINANT_MODE
@ PWM_SET_DOMINANT_MODE
Definition drv_mcc_extension_pwm.h:1202
PWM_FAULT_EVENT_PWML
@ PWM_FAULT_EVENT_PWML
Definition drv_mcc_extension_pwm.h:1258
PWM_FAULT_EVENT_PWMH
@ PWM_FAULT_EVENT_PWMH
Definition drv_mcc_extension_pwm.h:1257
PWM_PCI_SOURCE_PWM3
@ PWM_PCI_SOURCE_PWM3
Definition drv_mcc_extension_pwm.h:460
PWM_PCI_SOURCE_PWM1
@ PWM_PCI_SOURCE_PWM1
Definition drv_mcc_extension_pwm.h:458
PWM_PCI_SOURCE_PWM4
@ PWM_PCI_SOURCE_PWM4
Definition drv_mcc_extension_pwm.h:461
PWM_PCI_SOURCE_PWM2
@ PWM_PCI_SOURCE_PWM2
Definition drv_mcc_extension_pwm.h:459
RPnR_SOURCE_SS2
@ RPnR_SOURCE_SS2
RPn tied to SPI2 Client Select.
Definition drv_mcc_extension_pwm.h:532
RPnR_SOURCE_CLC4OUT
@ RPnR_SOURCE_CLC4OUT
RPn tied to CLC4 Output.
Definition drv_mcc_extension_pwm.h:572
RPnR_SOURCE_CMP1
@ RPnR_SOURCE_CMP1
RPn tied to Comparator 1 Output.
Definition drv_mcc_extension_pwm.h:544
RPnR_SOURCE_CMP3
@ RPnR_SOURCE_CMP3
RPn tied to Comparator 3 Output.
Definition drv_mcc_extension_pwm.h:546
RPnR_SOURCE_SDO3
@ RPnR_SOURCE_SDO3
RPn tied to SPI3 Data Output.
Definition drv_mcc_extension_pwm.h:533
RPnR_SOURCE_OCM6
@ RPnR_SOURCE_OCM6
RPn tied to SCCP6 Output.
Definition drv_mcc_extension_pwm.h:542
RPnR_SOURCE_SDO2
@ RPnR_SOURCE_SDO2
RPn tied to SPI2 Data Output.
Definition drv_mcc_extension_pwm.h:530
RPnR_SOURCE_OCM2
@ RPnR_SOURCE_OCM2
RPn tied to SCCP2 Output.
Definition drv_mcc_extension_pwm.h:538
RPnR_SOURCE_SS3
@ RPnR_SOURCE_SS3
RPn tied to SPI3 Client Select.
Definition drv_mcc_extension_pwm.h:535
RPnR_SOURCE_SENT1OUT
@ RPnR_SOURCE_SENT1OUT
RPn tied to SENT1 Output.
Definition drv_mcc_extension_pwm.h:563
RPnR_SOURCE_PTGTRG25
@ RPnR_SOURCE_PTGTRG25
PTG Trigger Output 25.
Definition drv_mcc_extension_pwm.h:562
RPnR_SOURCE_OCM1
@ RPnR_SOURCE_OCM1
RPn tied to SCCP1 Output.
Definition drv_mcc_extension_pwm.h:537
RPnR_SOURCE_SDO1
@ RPnR_SOURCE_SDO1
RPn tied to SPI1 Data Output.
Definition drv_mcc_extension_pwm.h:527
RPnR_SOURCE_MCCP9B
@ RPnR_SOURCE_MCCP9B
RPn tied to MCCP9 Output B.
Definition drv_mcc_extension_pwm.h:566
RPnR_SOURCE_MCCP9E
@ RPnR_SOURCE_MCCP9E
RPn tied to MCCP9 Output E.
Definition drv_mcc_extension_pwm.h:569
RPnR_SOURCE_OCM5
@ RPnR_SOURCE_OCM5
RPn tied to SCCP5 Output.
Definition drv_mcc_extension_pwm.h:541
RPnR_SOURCE_PWMED
@ RPnR_SOURCE_PWMED
RPn tied to PWM Event D Output.
Definition drv_mcc_extension_pwm.h:560
RPnR_SOURCE_SENT2OUT
@ RPnR_SOURCE_SENT2OUT
RPn tied to SENT2 Output.
Definition drv_mcc_extension_pwm.h:564
RPnR_SOURCE_CAN1TX
@ RPnR_SOURCE_CAN1TX
RPn tied to CAN1 Transmit.
Definition drv_mcc_extension_pwm.h:543
RPnR_SOURCE_OCM4
@ RPnR_SOURCE_OCM4
RPn tied to SCCP4 Output.
Definition drv_mcc_extension_pwm.h:540
RPnR_SOURCE_PTGTRG24
@ RPnR_SOURCE_PTGTRG24
PTG Trigger Output 24.
Definition drv_mcc_extension_pwm.h:561
RPnR_SOURCE_PWM4H
@ RPnR_SOURCE_PWM4H
RPn tied to PWM4H Output.
Definition drv_mcc_extension_pwm.h:549
RPnR_SOURCE_U3TX
@ RPnR_SOURCE_U3TX
RPn tied to UART3 Transmit.
Definition drv_mcc_extension_pwm.h:547
RPnR_SOURCE_REFCLKO
@ RPnR_SOURCE_REFCLKO
RPn tied to Reference Clock Output.
Definition drv_mcc_extension_pwm.h:536
RPnR_SOURCE_CLC3OUT
@ RPnR_SOURCE_CLC3OUT
RPn tied to CLC4 Output.
Definition drv_mcc_extension_pwm.h:571
RPnR_SOURCE_MCCP9A
@ RPnR_SOURCE_MCCP9A
RPn tied to MCCP9 Output A.
Definition drv_mcc_extension_pwm.h:565
RPnR_SOURCE_U2TX
@ RPnR_SOURCE_U2TX
RPn tied to UART2 Transmit.
Definition drv_mcc_extension_pwm.h:525
RPnR_SOURCE_QEICMP1
@ RPnR_SOURCE_QEICMP1
RPn tied to QEI1 Comparator Output.
Definition drv_mcc_extension_pwm.h:553
RPnR_SOURCE_U3DTR
@ RPnR_SOURCE_U3DTR
RPn tied to UART3 DTR
Definition drv_mcc_extension_pwm.h:575
RPnR_SOURCE_CLC2OUT
@ RPnR_SOURCE_CLC2OUT
RPn tied to CLC2 Output.
Definition drv_mcc_extension_pwm.h:556
RPnR_SOURCE_PWMEC
@ RPnR_SOURCE_PWMEC
RPn tied to PWM Event C Output.
Definition drv_mcc_extension_pwm.h:559
RPnR_SOURCE_SCK2
@ RPnR_SOURCE_SCK2
RPn tied to SPI2 Clock Output.
Definition drv_mcc_extension_pwm.h:531
RPnR_SOURCE_U3RTS
@ RPnR_SOURCE_U3RTS
RPn tied to UART3 Request-to-Send.
Definition drv_mcc_extension_pwm.h:548
RPnR_SOURCE_CMP2
@ RPnR_SOURCE_CMP2
RPn tied to Comparator 2 Output.
Definition drv_mcc_extension_pwm.h:545
RPnR_SOURCE_SS1
@ RPnR_SOURCE_SS1
RPn tied to SPI1 Client Select.
Definition drv_mcc_extension_pwm.h:529
RPnR_SOURCE_OCM7
@ RPnR_SOURCE_OCM7
RPn tied to SCCP7 Output.
Definition drv_mcc_extension_pwm.h:557
RPnR_SOURCE_OCM8
@ RPnR_SOURCE_OCM8
RPn tied to SCCP8 Output.
Definition drv_mcc_extension_pwm.h:558
RPnR_SOURCE_U1RTS
@ RPnR_SOURCE_U1RTS
RPn tied to UART1 Request-to-Send.
Definition drv_mcc_extension_pwm.h:524
RPnR_SOURCE_SCK3
@ RPnR_SOURCE_SCK3
RPn tied to SPI3 Clock Output.
Definition drv_mcc_extension_pwm.h:534
RPnR_SOURCE_QEICMP2
@ RPnR_SOURCE_QEICMP2
RPn tied to QEI2 Comparator Output.
Definition drv_mcc_extension_pwm.h:554
RPnR_SOURCE_PWMEB
@ RPnR_SOURCE_PWMEB
RPn tied to PWM Event B Output.
Definition drv_mcc_extension_pwm.h:552
RPnR_SOURCE_MCCP9F
@ RPnR_SOURCE_MCCP9F
RPn tied to MCCP9 Output F.
Definition drv_mcc_extension_pwm.h:570
RPnR_SOURCE_PWM4L
@ RPnR_SOURCE_PWM4L
RPn tied to PWM4L Output.
Definition drv_mcc_extension_pwm.h:550
RPnR_SOURCE_CLC1OUT
@ RPnR_SOURCE_CLC1OUT
RPn tied to CLC1 Output.
Definition drv_mcc_extension_pwm.h:555
RPnR_SOURCE_DefaultPORT
@ RPnR_SOURCE_DefaultPORT
RPn tied to Default Pin.
Definition drv_mcc_extension_pwm.h:522
RPnR_SOURCE_U1DTR
@ RPnR_SOURCE_U1DTR
RPn tied to UART1 DTR.
Definition drv_mcc_extension_pwm.h:573
RPnR_SOURCE_SCK1
@ RPnR_SOURCE_SCK1
RPn tied to SPI1 Clock Output.
Definition drv_mcc_extension_pwm.h:528
RPnR_SOURCE_U2RTS
@ RPnR_SOURCE_U2RTS
RPn tied to UART2 Request-to-Send.
Definition drv_mcc_extension_pwm.h:526
RPnR_SOURCE_MCCP9C
@ RPnR_SOURCE_MCCP9C
RPn tied to MCCP9 Output C.
Definition drv_mcc_extension_pwm.h:567
RPnR_SOURCE_U2DTR
@ RPnR_SOURCE_U2DTR
RPn tied to UART2 DTR.
Definition drv_mcc_extension_pwm.h:574
RPnR_SOURCE_OCM3
@ RPnR_SOURCE_OCM3
RPn tied to SCCP3 Output.
Definition drv_mcc_extension_pwm.h:539
RPnR_SOURCE_U1TX
@ RPnR_SOURCE_U1TX
RPn tied to UART1 Transmit.
Definition drv_mcc_extension_pwm.h:523
RPnR_SOURCE_PWMEA
@ RPnR_SOURCE_PWMEA
RPn tied to PWM Event A Output.
Definition drv_mcc_extension_pwm.h:551
RPnR_SOURCE_MCCP9D
@ RPnR_SOURCE_MCCP9D
RPn tied to MCCP9 Output D.
Definition drv_mcc_extension_pwm.h:568
PWM_PCI_TERM_PCI_SOURCE8
@ PWM_PCI_TERM_PCI_SOURCE8
Selects PCI Source #8.
Definition drv_mcc_extension_pwm.h:994
PWM_PCI_TERM_PGxTRIGB
@ PWM_PCI_TERM_PGxTRIGB
PGxTRIGB trigger event.
Definition drv_mcc_extension_pwm.h:991
PWM_PCI_TERM_PCI_SOURCE9
@ PWM_PCI_TERM_PCI_SOURCE9
Selects PCI Source #9.
Definition drv_mcc_extension_pwm.h:995
PWM_PCI_TERM_PGxTRIGA
@ PWM_PCI_TERM_PGxTRIGA
PGxTRIGA trigger event.
Definition drv_mcc_extension_pwm.h:990
PWM_PCI_TERM_PCI_SOURCE1
@ PWM_PCI_TERM_PCI_SOURCE1
Selects PCI Source #1 (PWM Generator output selected by the PWMPCI[2:0] bits)
Definition drv_mcc_extension_pwm.h:993
PWM_PCI_TERM_PGxTRIGC
@ PWM_PCI_TERM_PGxTRIGC
PGxTRIGC trigger event.
Definition drv_mcc_extension_pwm.h:992
PWM_PCI_TERM_MANUAL
@ PWM_PCI_TERM_MANUAL
Manual Terminate: Terminate on a write of ?1? to the SWTERM bit location.
Definition drv_mcc_extension_pwm.h:988
PWM_PCI_TERM_AUTO
@ PWM_PCI_TERM_AUTO
Auto-Terminate: Terminate when PCI source transitions from active to inactive.
Definition drv_mcc_extension_pwm.h:989
PWM_EVENT_SOURCE_CAHALF
@ PWM_EVENT_SOURCE_CAHALF
Definition drv_mcc_extension_pwm.h:1100
PWM_EVENT_SOURCE_PCI_FF_ACTIVE
@ PWM_EVENT_SOURCE_PCI_FF_ACTIVE
Definition drv_mcc_extension_pwm.h:1097
PWM_EVENT_SOURCE_PCI_SYNC_ACTIVE
@ PWM_EVENT_SOURCE_PCI_SYNC_ACTIVE
Definition drv_mcc_extension_pwm.h:1096
PWM_EVENT_SOURCE_PCI_FAULT_ACTIVE
@ PWM_EVENT_SOURCE_PCI_FAULT_ACTIVE
Definition drv_mcc_extension_pwm.h:1099
PWM_EVENT_SOURCE_ADC_TRIG2
@ PWM_EVENT_SOURCE_ADC_TRIG2
Definition drv_mcc_extension_pwm.h:1103
PWM_EVENT_SOURCE_HR_ERROR_EVENT
@ PWM_EVENT_SOURCE_HR_ERROR_EVENT
Definition drv_mcc_extension_pwm.h:1104
PWM_EVENT_SOURCE_PWM_GEN_OUTPUT
@ PWM_EVENT_SOURCE_PWM_GEN_OUTPUT
Definition drv_mcc_extension_pwm.h:1095
PWM_EVENT_SOURCE_PGTRGSEL
@ PWM_EVENT_SOURCE_PGTRGSEL
Definition drv_mcc_extension_pwm.h:1094
PWM_EVENT_SOURCE_STEER
@ PWM_EVENT_SOURCE_STEER
Definition drv_mcc_extension_pwm.h:1101
PWM_EVENT_SOURCE_ADC_TRIG1
@ PWM_EVENT_SOURCE_ADC_TRIG1
Definition drv_mcc_extension_pwm.h:1102
PWM_EVENT_SOURCE_PCI_FF_CL_ACTIVE
@ PWM_EVENT_SOURCE_PCI_FF_CL_ACTIVE
Definition drv_mcc_extension_pwm.h:1098
PWM_PCI_ACCEPTANCE_QUALIFER_DUTY
@ PWM_PCI_ACCEPTANCE_QUALIFER_DUTY
Duty cycle is active (base PWM Generator signal)
Definition drv_mcc_extension_pwm.h:871
PWM_PCI_ACCEPTANCE_QUALIFER_LEB
@ PWM_PCI_ACCEPTANCE_QUALIFER_LEB
LEB is active.
Definition drv_mcc_extension_pwm.h:872
PWM_PCI_ACCEPTANCE_QUALIFER_PCI_PWMPCI
@ PWM_PCI_ACCEPTANCE_QUALIFER_PCI_PWMPCI
Selects PCI Source #1 (PWM Generator output selected by the PWMPCI[2:0] bits)
Definition drv_mcc_extension_pwm.h:874
PWM_PCI_ACCEPTANCE_QUALIFER_NONE
@ PWM_PCI_ACCEPTANCE_QUALIFER_NONE
No acceptance qualifier is used (qualifier forced to ?1?)
Definition drv_mcc_extension_pwm.h:870
PWM_PCI_ACCEPTANCE_QUALIFER_PWM
@ PWM_PCI_ACCEPTANCE_QUALIFER_PWM
PWM Generator is triggered.
Definition drv_mcc_extension_pwm.h:873
PWM_PCI_ACCEPTANCE_QUALIFER_SWPCI
@ PWM_PCI_ACCEPTANCE_QUALIFER_SWPCI
SWPCI control bit only (qualifier forced to ?0?)
Definition drv_mcc_extension_pwm.h:877
PWM_PCI_ACCEPTANCE_QUALIFER_PCI_SOURCE8
@ PWM_PCI_ACCEPTANCE_QUALIFER_PCI_SOURCE8
Selects PCI Source #8.
Definition drv_mcc_extension_pwm.h:875
PWM_PCI_ACCEPTANCE_QUALIFER_PCI_SOURCE9
@ PWM_PCI_ACCEPTANCE_QUALIFER_PCI_SOURCE9
Selects PCI Source #9.
Definition drv_mcc_extension_pwm.h:876
PWM_PCI_SOURCE_SELECT_PCI13R
@ PWM_PCI_SOURCE_SELECT_PCI13R
‍RPn input
Definition drv_mcc_extension_pwm.h:799
PWM_PCI_SOURCE_SELECT_PCI16R
@ PWM_PCI_SOURCE_SELECT_PCI16R
‍RPn input
Definition drv_mcc_extension_pwm.h:796
PWM_PCI_SOURCE_SELECT_PCI17R
@ PWM_PCI_SOURCE_SELECT_PCI17R
‍RPn input
Definition drv_mcc_extension_pwm.h:795
PWM_PCI_SOURCE_SELECT_PCI14R
@ PWM_PCI_SOURCE_SELECT_PCI14R
‍RPn input
Definition drv_mcc_extension_pwm.h:798
PWM_PCI_SOURCE_SELECT_PCI22
@ PWM_PCI_SOURCE_SELECT_PCI22
Definition drv_mcc_extension_pwm.h:790
PWM_PCI_SOURCE_SELECT_PWM_EVENT_B
@ PWM_PCI_SOURCE_SELECT_PWM_EVENT_B
Definition drv_mcc_extension_pwm.h:788
PWM_PCI_SOURCE_SELECT_CLC1
@ PWM_PCI_SOURCE_SELECT_CLC1
Definition drv_mcc_extension_pwm.h:781
PWM_PCI_SOURCE_SELECT_CMP3
@ PWM_PCI_SOURCE_SELECT_CMP3
Definition drv_mcc_extension_pwm.h:783
PWM_PCI_SOURCE_SELECT_COMBO_TRIG_B
@ PWM_PCI_SOURCE_SELECT_COMBO_TRIG_B
Definition drv_mcc_extension_pwm.h:809
PWM_PCI_SOURCE_SELECT_PCI10R
@ PWM_PCI_SOURCE_SELECT_PCI10R
‍RPn input
Definition drv_mcc_extension_pwm.h:802
PWM_PCI_SOURCE_SELECT_PCI18R
@ PWM_PCI_SOURCE_SELECT_PCI18R
‍device pin
Definition drv_mcc_extension_pwm.h:794
PWM_PCI_SOURCE_SELECT_PCI15R
@ PWM_PCI_SOURCE_SELECT_PCI15R
‍RPn input
Definition drv_mcc_extension_pwm.h:797
PWM_PCI_SOURCE_SELECT_CMP1
@ PWM_PCI_SOURCE_SELECT_CMP1
Definition drv_mcc_extension_pwm.h:785
PWM_PCI_SOURCE_SELECT_PWM_EVENT_D
@ PWM_PCI_SOURCE_SELECT_PWM_EVENT_D
Definition drv_mcc_extension_pwm.h:786
PWM_PCI_SOURCE_SELECT_PCI21
@ PWM_PCI_SOURCE_SELECT_PCI21
‍device pin
Definition drv_mcc_extension_pwm.h:791
PWM_PCI_SOURCE_SELECT_PCI20
@ PWM_PCI_SOURCE_SELECT_PCI20
‍device pin
Definition drv_mcc_extension_pwm.h:792
PWM_PCI_SOURCE_SELECT_TIED_TO_0
@ PWM_PCI_SOURCE_SELECT_TIED_TO_0
Definition drv_mcc_extension_pwm.h:812
PWM_PCI_SOURCE_SELECT_PCI8R
@ PWM_PCI_SOURCE_SELECT_PCI8R
‍RPn input
Definition drv_mcc_extension_pwm.h:804
PWM_PCI_SOURCE_SELECT_CMP2
@ PWM_PCI_SOURCE_SELECT_CMP2
Definition drv_mcc_extension_pwm.h:784
PWM_PCI_SOURCE_SELECT_PCI12R
@ PWM_PCI_SOURCE_SELECT_PCI12R
‍RPn input
Definition drv_mcc_extension_pwm.h:800
PWM_PCI_SOURCE_SELECT_PCI19
@ PWM_PCI_SOURCE_SELECT_PCI19
‍device pin
Definition drv_mcc_extension_pwm.h:793
PWM_PCI_SOURCE_SELECT_COMBO_TRIG_A
@ PWM_PCI_SOURCE_SELECT_COMBO_TRIG_A
Definition drv_mcc_extension_pwm.h:810
PWM_PCI_SOURCE_SELECT_PWMPCI_MUX
@ PWM_PCI_SOURCE_SELECT_PWMPCI_MUX
Definition drv_mcc_extension_pwm.h:811
PWM_PCI_SOURCE_SELECT_PCI11R
@ PWM_PCI_SOURCE_SELECT_PCI11R
‍RPn input
Definition drv_mcc_extension_pwm.h:801
PWM_PCI_SOURCE_SELECT_PWM_EVENT_A
@ PWM_PCI_SOURCE_SELECT_PWM_EVENT_A
Definition drv_mcc_extension_pwm.h:789
PWM_PCI_SOURCE_SELECT_PCI9R
@ PWM_PCI_SOURCE_SELECT_PCI9R
‍RPn input
Definition drv_mcc_extension_pwm.h:803
PWM_PCI_SOURCE_SELECT_PWM_EVENT_C
@ PWM_PCI_SOURCE_SELECT_PWM_EVENT_C
Definition drv_mcc_extension_pwm.h:787
PWM_PCI_INPUT10
@ PWM_PCI_INPUT10
Definition drv_mcc_extension_pwm.h:734
PWM_PCI_INPUT8
@ PWM_PCI_INPUT8
Definition drv_mcc_extension_pwm.h:732
PWM_PCI_INPUT11
@ PWM_PCI_INPUT11
Definition drv_mcc_extension_pwm.h:735
PWM_PCI_INPUT9
@ PWM_PCI_INPUT9
Definition drv_mcc_extension_pwm.h:733
PWM_UPDTRG_PGxDC
@ PWM_UPDTRG_PGxDC
a write to PGxDC will update
Definition drv_mcc_extension_pwm.h:1145
PWM_UPDTRG_PGxTRIGA
@ PWM_UPDTRG_PGxTRIGA
a write to PGxTRIGA will update
Definition drv_mcc_extension_pwm.h:1147
PWM_UPDTRG_PGxPHASE
@ PWM_UPDTRG_PGxPHASE
a write to PGxPHASE will update
Definition drv_mcc_extension_pwm.h:1146
PWM_UPDTRG_MANUAL
@ PWM_UPDTRG_MANUAL
user must manual set UPDREQ bit to update
Definition drv_mcc_extension_pwm.h:1144
RPnR_VIRTUAL_PIN_RP177
@ RPnR_VIRTUAL_PIN_RP177
Definition drv_mcc_extension_pwm.h:587
RPnR_VIRTUAL_PIN_RP181
@ RPnR_VIRTUAL_PIN_RP181
Definition drv_mcc_extension_pwm.h:591
RPnR_VIRTUAL_PIN_RP176
@ RPnR_VIRTUAL_PIN_RP176
Definition drv_mcc_extension_pwm.h:586
RPnR_VIRTUAL_PIN_RP179
@ RPnR_VIRTUAL_PIN_RP179
Definition drv_mcc_extension_pwm.h:589
RPnR_VIRTUAL_PIN_RP178
@ RPnR_VIRTUAL_PIN_RP178
Definition drv_mcc_extension_pwm.h:588
RPnR_VIRTUAL_PIN_RP180
@ RPnR_VIRTUAL_PIN_RP180
Definition drv_mcc_extension_pwm.h:590
PWM_PCI_ACCEPT_ANY_EDGE
@ PWM_PCI_ACCEPT_ANY_EDGE
Definition drv_mcc_extension_pwm.h:33
PWM_PCI_ACCEPT_LEVEL_SENSITIVE
@ PWM_PCI_ACCEPT_LEVEL_SENSITIVE
Definition drv_mcc_extension_pwm.h:31
PWM_PCI_ACCEPT_RISING_EDGE
@ PWM_PCI_ACCEPT_RISING_EDGE
Definition drv_mcc_extension_pwm.h:32
PWM_PCI_ACCEPT_LATCHED
@ PWM_PCI_ACCEPT_LATCHED
Definition drv_mcc_extension_pwm.h:34
PWM_PCI_ACCEPT_LATCHED_ANY_EDGE
@ PWM_PCI_ACCEPT_LATCHED_ANY_EDGE
Definition drv_mcc_extension_pwm.h:36
PWM_PCI_ACCEPT_LATCHED_RISING_EDGE
@ PWM_PCI_ACCEPT_LATCHED_RISING_EDGE
Definition drv_mcc_extension_pwm.h:35
PWM_TRIG_MODE_RETRIGGERABLE
@ PWM_TRIG_MODE_RETRIGGERABLE
Definition drv_mcc_extension_pwm.h:934
PWM_TRIG_MODE_SINGLE
@ PWM_TRIG_MODE_SINGLE
Definition drv_mcc_extension_pwm.h:933