package embox.arch.riscv.kernel

module conf {
	option boolean smode = false
}

module locore extends embox.arch.locore {
	depends entry
	depends interrupt
	depends exception
}

module interrupt extends embox.arch.interrupt {
	option number plic_addr=0x0C000000

	source "ipl_impl.c"
	source "ipl_impl.h"
	source "interrupt.c"

	depends embox.kernel.irq
}

module no_interrupt extends embox.arch.interrupt {
	source "ipl_impl.c"
	source "ipl_impl.h"
	source "no_interrupt.c"
}

module entry extends embox.arch.entry {
	source "entry.S"
}

module context extends embox.arch.context {
	source "context.c"
	source "context.h"
	source "context_switch.S"
}

module exception {
	@IncludeExport(path="riscv")
	source "exception.h"

	source "exception.c"
}

module cpu_idle extends embox.arch.cpu_idle {
	source "cpu_idle.h"
}

module fpu {
	source "fpu.c"
}

module ipi {
	@IncludeExport(path="riscv")
	source "ipi.h"

	source "ipi.c"

}
