| Project Settings |
|---|
| Project Name | my_pll_64mhz | Device Name | syn_results: Lattice ECP5U : LFE5U_12F |
| Implementation Name | syn_results | Top Module | my_pll_64mhz |
| Pipelining | 0 | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 50 |
| Disable I/O Insertion | 1 | Disable Sequential Optimizations | 0 |
| Clock Conversion | 1 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
8 |
1 |
0 |
- |
00m:02s |
- |
4/5/2019
11:20:54 AM |
| (premap) | Complete |
2 |
0 |
0 |
0m:00s |
0m:01s |
142MB |
4/5/2019
11:20:57 AM |
| (fpga_mapper) | Complete |
8 |
2 |
0 |
0m:01s |
0m:01s |
145MB |
4/5/2019
11:20:59 AM |
| Multi-srs Generator |
Complete | | | | | | | 4/5/2019
11:20:55 AM |
| Area Summary |
|---|
|
| Register bits | 0 |
I/O cells | 0 |
| Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
| ORCA LUTs
(total_luts) | 0 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| System | 100.0 MHz | NA | 10.000 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 0 / 0 |
| |
|