#--  Synopsys, Inc.
#--  Version M-2017.03L-SP1-1
#--  Project file C:\work\tinysdr_fpga_lora_tx\lora_tx_clarity\my_pll_64mhz\syn_results\run_options.txt
#--  Written on Fri Apr  5 11:20:52 2019


#project files
add_file -verilog "C:/lscc/diamond/3.10_x64/cae_library/synthesis/verilog/ecp5u.v"
add_file -verilog "C:/lscc/diamond/3.10_x64/cae_library/synthesis/verilog/pmi_def.v"
add_file -verilog "C:/work/tinysdr_fpga_lora_tx/lora_tx_clarity/my_pll_64mhz/my_pll_64mhz.v"
add_file -fpga_constraint "C:/work/tinysdr_fpga_lora_tx/lora_tx_clarity/my_pll_64mhz/my_pll_64mhz.fdc"



#implementation: "syn_results"
impl -add syn_results -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology ecp5u
set_option -part LFE5U_12F
set_option -package MG285C
set_option -speed_grade -6
set_option -part_companion ""

#compilation/mapping options
set_option -top_module "my_pll_64mhz"

# hdl_compiler_options
set_option -distributed_compile 0

# mapper_without_write_options
set_option -frequency 100
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 1
set_option -write_vhdl 1

# Lattice XP
set_option -maxfan 50
set_option -disable_io_insertion 1
set_option -retiming 0
set_option -pipe 0
set_option -forcegsr false
set_option -fix_gated_and_generated_clocks 1
set_option -rw_check_on_ram 1
set_option -update_models_cp 0
set_option -syn_edif_array_rename 1
set_option -Write_declared_clocks_only 1

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./my_pll_64mhz.edn"

#set log file 
set_option log_file "C:/work/tinysdr_fpga_lora_tx/lora_tx_clarity/my_pll_64mhz/syn_results/my_pll_64mhz.srf" 
impl -active "syn_results"
