
#  Three phase (3-PH) DSOGI Phase Lock Loop (PLL) 



## Dependencies


![Static Badge](https://img.shields.io/badge/Matlab2023a-Requiered-red)
![Static Badge](https://img.shields.io/badge/build-STM32F7?style=flat&label=STM32F7)




## Roadmap

- [x]  Angle Lock
- [x]  Phase Swap Detection
- [x]  Realtime Phase Fault Detection
- [x]  Generated Code
- [x]  Code Tested on STM32F7 (code on stm32.zip)
- [x]  Not using Volder's algorithm instead using approximations requiering a sampling of 10kHz  

## Demo
Worse case, when the phase of the Voltage phase is pi radians of offset at the start, thus having the maximum error. 

65Hz input 
![image](https://github.com/user-attachments/assets/7559c034-e5eb-44b9-83ff-a9a808543a0d)

55Hz input
![image](https://github.com/user-attachments/assets/7c88165c-4e5b-4e19-8780-866d3a438f46)

45Hz input
![image](https://github.com/user-attachments/assets/5316a938-6ae5-4108-a774-b37587ab0b86)





## Authors

- Angel Rodriguez [ang.rodr97@gmail.com]
## Acknowledgements

 - [[1] Pinto J, Carvalho A, Rocha A, Araújo A. Comparison of DSOGI-Based PLL for Phase Estimation in Three-Phase Weak Grids. Electricity. 2021; 2(3):244-270. ](https://doi.org/10.3390/electricity2030015)


