<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CORECORDIC</name><vendor>Actel</vendor><library>DirectCore</library><version>4.0.102</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>coreparameters.vhd</name><userFileType>VHDL</userFileType></file><file fileid="1"><name>rtl\vhdl\test\user\bhv_pack.vhd</name><fileType>VHDLSource</fileType></file><file fileid="2"><name>rtl\vhdl\test\user\bhvKit.vhd</name><fileType>VHDLSource</fileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="3"><name>rtl\vhdl\core\cordic_kit.vhd</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file><file fileid="4"><name>rtl\vhdl\core\cordic_rtl_pack.vhd</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>