#===========================================================
#
# Syntax:
# -------
#
# memmap    resource_name base_address;
#
# write     width resource_name byte_offset data;
# read      width resource_name byte_offset;
# readcheck width resource_name byte_offset data;
#
#===========================================================


#-----------------------------------------------------------
# Memory Map
# Define name and base address of each resource.
#-----------------------------------------------------------

memmap FLASH    0x00000000;
memmap SSRAM    0x08000000;

procedure main
    call mem_test
return


procedure mem_test
    # Set debug level (controls verbosity of simulation trace)
    debug 3;

    #-----------------------------------------------------------
    # Test FLASH access
    #-----------------------------------------------------------
    print "============================================";
    print "FLASH test";
    print "============================================";

    write     w FLASH   0x00    0xdeadbeef;
    write     w FLASH   0x04    0x45454545;
    write     w FLASH   0x08    0x12345678;
    readcheck w FLASH   0x08    0x12345678;
    read      w FLASH   0x00;
    read      w FLASH   0x04;
    read      w FLASH   0x08;
    write     w FLASH   0x10    0xabcd1234;

    write     w FLASH   0x50    0x3d681acf;
    write     w FLASH   0x54    0x82db74a9;
    write     w FLASH   0x58    0xe81d93be;
    readcheck w FLASH   0x50    0x3d681acf;
    readcheck w FLASH   0x54    0x82db74a9;
    readcheck w FLASH   0x58    0xe81d93be;

    #-----------------------------------------------------------
    # Test SSRAM access
    #-----------------------------------------------------------
    print "============================================";
    print "SRAM test";
    print "============================================";
    write     w SSRAM   0x00    0x11111111;
    write     w SSRAM   0x04    0x22222222;
    write     w SSRAM   0x08    0x33333333;
    readcheck w SSRAM   0x00    0x11111111;
    readcheck w SSRAM   0x04    0x22222222;
    readcheck w SSRAM   0x08    0x33333333;

    write     b SSRAM   0x24    0x41;
    write     b SSRAM   0x3c    0xa5;
    write     b SSRAM   0x28    0xcd;
    readcheck b SSRAM   0x3c    0xa5;
    readcheck b SSRAM   0x24    0x41;
    readcheck b SSRAM   0x28    0xcd;

    write     b SSRAM   0x42    0xae;
    write     b SSRAM   0x43    0x67;
    write     b SSRAM   0x4a    0x14;
    readcheck b SSRAM   0x42    0xae;
    readcheck b SSRAM   0x43    0x67;
    readcheck b SSRAM   0x4a    0x14;

    write     w SSRAM   0x50    0x3d681acf;
    write     w SSRAM   0x54    0x82db74a9;
    write     w SSRAM   0x58    0xe81d93be;
    readcheck w SSRAM   0x50    0x3d681acf;
    readcheck w SSRAM   0x54    0x82db74a9;
    readcheck w SSRAM   0x58    0xe81d93be;

    write     h SSRAM   0x12    0x368c;
    write     h SSRAM   0x10    0x8dba;
    write     h SSRAM   0x16    0xe1db;
    readcheck h SSRAM   0x12    0x368c;
    readcheck h SSRAM   0x10    0x8dba;
    readcheck h SSRAM   0x16    0xe1db;

return
