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LIST REVISIONS
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ENDLIST
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CORECORDIC_LIB
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ENDLIST
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BEGIN_USE_CONSTRAINT
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BEGIN_USE_CONSTRAINT
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ENDLIST
LIST UsedFile
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LIST AssociatedStimulus
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ENDLIST
LIST ProjectState5.1
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ENDLIST
Used_File_List
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ENDLIST
ENDLIST
ENDLIST
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ENDLIST
LIST ProjectState5.1
LIST Impl1
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LIST FlowOptions
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ENDLIST
Used_File_List
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ENDLIST
ENDLIST
ENDLIST
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ENDLIST
ENDLIST
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VALUE "<project>\component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\test\user\coreCordic_tb.vhd,tb_hdl"
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST Alpha_Max_plus_Beta_Min
VALUE "<project>\stimulus\Alpha_Max_plus_Beta_Min_tb.vhd,tb_hdl"
ENDLIST
LIST CORECORDIC_C0
VALUE "<project>\component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\test\user\coreCordic_tb.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST CORELNSQRT
VALUE "<project>\component\Actel\DirectCore\CORELNSQRT\2.0.104\user\CoreLNSQRT_tb.v,tb_hdl"
ENDLIST
LIST CORECORDIC_C0_CORECORDIC_C0_0_CORECORDIC
VALUE "<project>\component\work\CORECORDIC_C0\CORECORDIC_C0_0\inpTestVect.vhd,tb_hdl"
VALUE "<project>\component\work\CORECORDIC_C0\CORECORDIC_C0_0\outpTestVect.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORECORDIC\4.0.102\coreparameters.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhv_pack.vhd,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd,tb_hdl"
VALUE "<project>\component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\test\user\coreCordic_tb.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=10000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DisablePulseFiltering=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
TimeUnit=1
TimeUnitBase=ns
Precision=100
PrecisionBase=ps
ENDLIST
LIST ModelSimLibPath
UseCustomPath=TRUE
LibraryPath=C:/Microsemi/Libero_SoC_v12.1/Designer/lib/modelsimpro/precompiled\vlog\SmartFusion2
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
PeriInitStandalone=FALSE
OnDemandBuildDH=TRUE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
VmNetlistFlowOn=TRUE
EnableDesignSeparationOn=FALSE
EnableSETMitigationOn=FALSE
DisplayFanoutLimit=10
AbortFlowOnPDCErrorsOn=TRUE
AbortFlowOnSDCErrorsOn=TRUE
InstantiateInSmartDesign=FALSE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="eclipse.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="SynplifyProME"
FUNCTION="Synthesis"
TOOL="Synplify Pro ME"
LOCATION="C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\bin\synplify_pro.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="ModelSimME"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Microsemi\Libero_SoC_v12.1\ModelSim\win32acoem\modelsim.exe"
PARAM=" -l testbench_presynth_simulation.log "
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="FPExpress"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Microsemi\Libero_SoC_v12.1\Designer\binfp\FPExpress.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="IdentifyDebugger"
FUNCTION="IdentifyDebugger"
TOOL="Identify Debugger"
LOCATION="C:\Microsemi\Libero_SoC_v12.1\Identify\bin\identify_debugger.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "Alpha_Max_plus_Beta_Min::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "CORECORDIC_C0::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
ORIENTATION;HORIZONTAL
Reports;Reports;0
ReportsCurrentItem;Pre-Synthesis Simulate:testbench_presynth_simulation.log
StartPage;StartPage;0
SmartDesign;test_sd;0
HDL;hdl\Alpha_Max_plus_Beta_Min.vhd;0
ACTIVEVIEW;Reports
ENDLIST
LIST ModuleSubBlockList
LIST "Abs_Val_Cmplx_CORDIC_sd::work","component\work\Abs_Val_Cmplx_CORDIC_sd\Abs_Val_Cmplx_CORDIC_sd.cxf","TRUE","FALSE"
SUBBLOCK "CORECORDIC_C0::work","component\work\CORECORDIC_C0\CORECORDIC_C0.vhd","TRUE","FALSE"
ENDLIST
LIST "Abs_Val_Cmplx_CoreLnSqrt_sd::work","component\work\Abs_Val_Cmplx_CoreLnSqrt_sd\Abs_Val_Cmplx_CoreLnSqrt_sd.cxf","TRUE","FALSE"
SUBBLOCK "CORELNSQRT_C0::work","component\work\CORELNSQRT_C0\CORELNSQRT_C0.vhd","TRUE","FALSE"
SUBBLOCK "HARD_MULT_ADDSUB_C0::work","component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0.vhd","TRUE","FALSE"
ENDLIST
LIST "Absolute_Value_Complex_sd::work","","FALSE","FALSE"
ENDLIST
LIST "Absolute_Value_Complex_test_sd::work","component\work\Absolute_Value_Complex_test_sd\Absolute_Value_Complex_test_sd.cxf","TRUE","FALSE"
SUBBLOCK "Absolute_Value_Complex_sd::work","","FALSE","FALSE"
SUBBLOCK "FCCC_C0::work","component\work\FCCC_C0\FCCC_C0.vhd","TRUE","FALSE"
SUBBLOCK "OSC_C0::work","component\work\OSC_C0\OSC_C0.vhd","TRUE","FALSE"
ENDLIST
LIST "Alpha_Max_plus_Beta_Min::work","hdl\Alpha_Max_plus_Beta_Min.vhd","FALSE","FALSE"
SUBBLOCK "HARD_MULT_ADDSUB_C1::work","component\work\HARD_MULT_ADDSUB_C1\HARD_MULT_ADDSUB_C1.vhd","TRUE","FALSE"
ENDLIST
LIST "CORECORDIC_C0::work","component\work\CORECORDIC_C0\CORECORDIC_C0.vhd","TRUE","FALSE"
SUBBLOCK "CORECORDIC_C0_CORECORDIC_C0_0_CORECORDIC::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\core\CORECORDIC.vhd","FALSE","FALSE"
ENDLIST
LIST "CORELNSQRT::work","component\Actel\DirectCore\CORELNSQRT\2.0.104\Encrypted\CoreLNSQRT.v","FALSE","FALSE"
ENDLIST
LIST "CORELNSQRT_C0::work","component\work\CORELNSQRT_C0\CORELNSQRT_C0.vhd","TRUE","FALSE"
SUBBLOCK "CORELNSQRT::work","component\Actel\DirectCore\CORELNSQRT\2.0.104\Encrypted\CoreLNSQRT.v","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "FCCC_C0::work","component\work\FCCC_C0\FCCC_C0.vhd","TRUE","FALSE"
SUBBLOCK "FCCC_C0_FCCC_C0_0_FCCC::work","component\work\FCCC_C0\FCCC_C0_0\FCCC_C0_FCCC_C0_0_FCCC.vhd","FALSE","FALSE"
ENDLIST
LIST "FCCC_C0_FCCC_C0_0_FCCC::work","component\work\FCCC_C0\FCCC_C0_0\FCCC_C0_FCCC_C0_0_FCCC.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_package::work","C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\FFT_Core\hdl\FFT_Package.vhd","FALSE","FALSE"
ENDLIST
LIST "HARD_MULT_ADDSUB_C0::work","component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0.vhd","TRUE","FALSE"
SUBBLOCK "HARD_MULT_ADDSUB_C0_HARD_MULT_ADDSUB_C0_0_HARD_MULT_ADDSUB::work","component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0_0\HARD_MULT_ADDSUB_C0_HARD_MULT_ADDSUB_C0_0_HARD_MULT_ADDSUB.vhd","FALSE","FALSE"
ENDLIST
LIST "HARD_MULT_ADDSUB_C0_HARD_MULT_ADDSUB_C0_0_HARD_MULT_ADDSUB::work","component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0_0\HARD_MULT_ADDSUB_C0_HARD_MULT_ADDSUB_C0_0_HARD_MULT_ADDSUB.vhd","FALSE","FALSE"
ENDLIST
LIST "HARD_MULT_ADDSUB_C1::work","component\work\HARD_MULT_ADDSUB_C1\HARD_MULT_ADDSUB_C1.vhd","TRUE","FALSE"
SUBBLOCK "HARD_MULT_ADDSUB_C1_HARD_MULT_ADDSUB_C1_0_HARD_MULT_ADDSUB::work","component\work\HARD_MULT_ADDSUB_C1\HARD_MULT_ADDSUB_C1_0\HARD_MULT_ADDSUB_C1_HARD_MULT_ADDSUB_C1_0_HARD_MULT_ADDSUB.vhd","FALSE","FALSE"
ENDLIST
LIST "HARD_MULT_ADDSUB_C1_HARD_MULT_ADDSUB_C1_0_HARD_MULT_ADDSUB::work","component\work\HARD_MULT_ADDSUB_C1\HARD_MULT_ADDSUB_C1_0\HARD_MULT_ADDSUB_C1_HARD_MULT_ADDSUB_C1_0_HARD_MULT_ADDSUB.vhd","FALSE","FALSE"
ENDLIST
LIST "OSC_C0::work","component\work\OSC_C0\OSC_C0.vhd","TRUE","FALSE"
SUBBLOCK "OSC_C0_OSC_C0_0_OSC::work","component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd","FALSE","FALSE"
ENDLIST
LIST "OSC_C0_OSC_C0_0_OSC::work","component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd","FALSE","FALSE"
SUBBLOCK "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ_FAB::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ_FAB::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "test_sd::work","component\work\test_sd\test_sd.cxf","TRUE","FALSE"
SUBBLOCK "HARD_MULT_ADDSUB_C1::work","component\work\HARD_MULT_ADDSUB_C1\HARD_MULT_ADDSUB_C1.vhd","TRUE","FALSE"
ENDLIST
LIST "XTLOSC::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "XTLOSC_FAB::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "bhv_kitDelay_reg::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
ENDLIST
LIST "bhv_pack::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhv_pack.vhd","FALSE","TRUE"
ENDLIST
LIST "bhvClockGen::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
ENDLIST
LIST "bhvDelay::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
ENDLIST
LIST "bhvEdge::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
ENDLIST
LIST "cordic_bhvInpVect::corecordic_lib","","FALSE","FALSE"
ENDLIST
LIST "cordic_bhvOutpVect::corecordic_lib","","FALSE","FALSE"
ENDLIST
LIST "CORELNSQRT_TB::work","component\Actel\DirectCore\CORELNSQRT\2.0.104\user\CoreLNSQRT_tb.v","FALSE","TRUE"
SUBBLOCK "CORELNSQRT::work","component\Actel\DirectCore\CORELNSQRT\2.0.104\Encrypted\CoreLNSQRT.v","FALSE","FALSE"
ENDLIST
LIST "coreparameters::work","component\Actel\DirectCore\CORECORDIC\4.0.102\coreparameters.vhd","FALSE","TRUE"
ENDLIST
LIST "Alpha_Max_plus_Beta_Min::work","hdl\Alpha_Max_plus_Beta_Min.vhd","FALSE","FALSE"
SUBBLOCK "HARD_MULT_ADDSUB_C1::work","component\work\HARD_MULT_ADDSUB_C1\HARD_MULT_ADDSUB_C1.vhd","TRUE","FALSE"
ENDLIST
LIST "bhv_kitDelay_bit_reg::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
ENDLIST
LIST "bhvClkGen::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
SUBBLOCK "bhv_kitDelay_bit_reg::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
ENDLIST
LIST "bhvCountS::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
ENDLIST
LIST "bhvCountS::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
ENDLIST
LIST "bhvCountS::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
ENDLIST
LIST "testbench::work","stimulus\Alpha_Max_plus_Beta_Min_tb.vhd","FALSE","TRUE"
SUBBLOCK "Alpha_Max_plus_Beta_Min::work","hdl\Alpha_Max_plus_Beta_Min.vhd","FALSE","FALSE"
ENDLIST
LIST "testbench::work","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\test\user\coreCordic_tb.vhd","FALSE","TRUE"
SUBBLOCK "CORECORDIC_C0_CORECORDIC_C0_0_CORECORDIC::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\core\CORECORDIC.vhd","FALSE","FALSE"
SUBBLOCK "bhvEdge::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
SUBBLOCK "bhv_kitDelay_reg::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
SUBBLOCK "cordic_bhvInpVect::corecordic_lib","","FALSE","FALSE"
SUBBLOCK "cordic_bhvOutpVect::corecordic_lib","","FALSE","FALSE"
SUBBLOCK "bhvClkGen::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
SUBBLOCK "bhvCountS::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
SUBBLOCK "bhvCountS::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
SUBBLOCK "bhvCountS::work","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd","FALSE","TRUE"
ENDLIST
LIST "cordic_coarse_post_rotator::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_coarse_pre_rotator::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_dp_bits_trans::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_signExt::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_init_kickstart::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitCountS::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitRndEven::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitRndSymm::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitRndUp::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitRoundTop::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRndEven::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRndSymm::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRndUp::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_signExt::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_par_calc::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_rtl_pack::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_rtl_pack.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_signExt::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "CORECORDIC_C0_CORECORDIC_C0_0_cordic_par::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\core\cordic_par.vhd","FALSE","FALSE"
SUBBLOCK "CORECORDIC_C0_CORECORDIC_C0_0_cordic_par_uRotator::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\core\cordic_par.vhd","FALSE","FALSE"
SUBBLOCK "cordic_coarse_post_rotator::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_coarse_pre_rotator::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_dp_bits_trans::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRoundTop::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_signExt::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "CORECORDIC_C0_CORECORDIC_C0_0_cordic_par_uRotator::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\core\cordic_par.vhd","FALSE","FALSE"
SUBBLOCK "CORECORDIC_C0_CORECORDIC_C0_0_cROM_par::corecordic_lib","","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_par_calc::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "CORECORDIC_C0_CORECORDIC_C0_0_CORECORDIC::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\core\CORECORDIC.vhd","FALSE","FALSE"
SUBBLOCK "CORECORDIC_C0_CORECORDIC_C0_0_cordic_par::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\core\cordic_par.vhd","FALSE","FALSE"
SUBBLOCK "cordic_init_kickstart::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "CORECORDIC_C0_CORECORDIC_C0_0_cordic_word::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\core\cordic_word.vhd","FALSE","FALSE"
ENDLIST
LIST "CORECORDIC_C0_CORECORDIC_C0_0_cROM_par::corecordic_lib","","FALSE","FALSE"
ENDLIST
LIST "CORECORDIC_C0_CORECORDIC_C0_0_word_cROM::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\CORECORDIC_C0_CORECORDIC_C0_0_CordicLUT_word.vhd","FALSE","FALSE"
ENDLIST
LIST "coreparameters::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\coreparameters.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_coarse_post_rotator::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_coarse_pre_rotator::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_dp_bits_trans::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_signExt::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitCountS::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitRndEven::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitRoundTop::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRndSymm::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRndUp::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_signExt::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRndEven::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_signExt::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_word_calc::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordicSm::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitCountS::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "CORECORDIC_C0_CORECORDIC_C0_0_cordic_word::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\core\cordic_word.vhd","FALSE","FALSE"
SUBBLOCK "cordic_signExt::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "CORECORDIC_C0_CORECORDIC_C0_0_cordic_word_uRotator::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\core\cordic_word.vhd","FALSE","FALSE"
SUBBLOCK "cordicSm::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_coarse_post_rotator::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_coarse_pre_rotator::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_dp_bits_trans::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRoundTop::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRoundTop::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "CORECORDIC_C0_CORECORDIC_C0_0_cordic_word_uRotator::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\rtl\vhdl\core\cordic_word.vhd","FALSE","FALSE"
SUBBLOCK "CORECORDIC_C0_CORECORDIC_C0_0_word_cROM::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\CORECORDIC_C0_CORECORDIC_C0_0_CordicLUT_word.vhd","FALSE","FALSE"
SUBBLOCK "cordic_word_calc::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitCountS::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitRoundTop::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_bit_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRndSymm::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRndUp::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_signExt::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
SUBBLOCK "cordic_kitRndEven::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_kitDelay_reg::corecordic_lib","component\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\core\cordic_kit.vhd","FALSE","FALSE"
ENDLIST
LIST "cordic_bhvInpVect::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\inpTestVect.vhd","FALSE","TRUE"
ENDLIST
LIST "cordic_bhvOutpVect::corecordic_lib","component\work\CORECORDIC_C0\CORECORDIC_C0_0\outpTestVect.vhd","FALSE","TRUE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
ENDLIST
LIST IOTabList
ENDLIST
LIST FPTabList
ENDLIST
LIST TimingTabList
VALUE "synthesis\AutoConstraint_Alpha_Max_plus_Beta_Min.sdc"
ENDLIST
LIST FDCTabList
ENDLIST
