KEY LIBERO "12.600"
KEY CAPTURE "12.600.0.14"
KEY DEFAULT_IMPORT_LOC "D:\Appsnotes\2010\User_Logic_to_MSS\design_files\User_Logic_MSS_DF_old\APB_master_fabric\hdl"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "0"
KEY HDLTechnology "VHDL"
KEY VERILOGMODE "VERILOG2001"
KEY VHDLMODE "VHDL2008"
KEY UseConstraintFlowTechnology "TRUE"
KEY VendorTechnology_Family "SmartFusion2"
KEY VendorTechnology_Die "PA4M1000_N"
KEY VendorTechnology_Package "tq144"
KEY VendorTechnology_Speed "STD"
KEY VendorTechnology_DieVoltage "1.2"
KEY VendorTechnology_PART_RANGE "COM"
KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE "100_MS"
KEY VendorTechnology_IO_DEFT_STD "LVCMOS25"
KEY VendorTechnology_OPCONR ""
KEY VendorTechnology_PLL_SUPPLY "PLL_SUPPLY_25"
KEY VendorTechnology_RAD_EXPOSURE ""
KEY VendorTechnology_RESERVEMIGRATIONPINS "1"
KEY VendorTechnology_RESTRICTPROBEPINS "1"
KEY VendorTechnology_RESTRICTSPIPINS "0"
KEY VendorTechnology_SYSTEM_CONTROLLER_SUSPEND_MODE "0"
KEY VendorTechnology_TARGETDEVICESFORMIGRATION "PA4M1000_N"
KEY VendorTechnology_TEMPR "COM"
KEY VendorTechnology_UNUSED_MSS_IO_RESISTOR_PULL "None"
KEY VendorTechnology_VCCI_1.2_VOLTR "COM"
KEY VendorTechnology_VCCI_1.5_VOLTR "COM"
KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
KEY VendorTechnology_VOLTR "COM"
KEY ProjectLocation "C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\FFT_Core"
KEY ProjectDescription ""
KEY Pa4PeripheralNewSeq "GOOD"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "FFT_Butterfly_HW_MATHDSP::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST FileManager
VALUE "<project>\component\Actel\SgCore\DPSRAM\1.0.101\DPSRAM.cxf,actgen_cxf"
STATE="utd"
TIME="1582868796"
SIZE="243"
PARENT="<project>\component\work\DPSRAM_C0\DPSRAM_C0.cxf"
ENDFILE
VALUE "<project>\component\Actel\SgCore\FCCC\2.0.201\FCCC.cxf,actgen_cxf"
STATE="utd"
TIME="1582014068"
SIZE="241"
PARENT="<project>\component\work\FCCC_C0\FCCC_C0.cxf"
ENDFILE
VALUE "<project>\component\Actel\SgCore\HARD_MULT\1.0.100\HARD_MULT.cxf,actgen_cxf"
STATE="utd"
TIME="1581973983"
SIZE="246"
PARENT="<project>\component\work\HARD_MULT_C0\HARD_MULT_C0.cxf"
ENDFILE
VALUE "<project>\component\Actel\SgCore\HARD_MULT_ADDSUB\1.0.100\HARD_MULT_ADDSUB.cxf,actgen_cxf"
STATE="utd"
TIME="1581986819"
SIZE="253"
PARENT="<project>\component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0.cxf"
ENDFILE
VALUE "<project>\component\Actel\SgCore\OSC\2.0.101\OSC.cxf,actgen_cxf"
STATE="utd"
TIME="1582014057"
SIZE="682"
PARENT="<project>\component\work\OSC_C0\OSC_C0.cxf"
ENDFILE
VALUE "<project>\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd,hdl"
STATE="utd"
TIME="1573066799"
SIZE="2164"
PARENT="<project>\component\Actel\SgCore\OSC\2.0.101\OSC.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="SYNPLIFY7_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\SgCore\OSC\2.0.101\osc_comps_pre.vhd,hdl"
STATE="utd"
TIME="1573066799"
SIZE="2108"
PARENT="<project>\component\Actel\SgCore\OSC\2.0.101\OSC.cxf"
BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideSYNTHESIS"
TOOL_CONSTRAINT_USE="PRECISION_EXT"
END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\Complex_Mult_test_sd\Complex_Mult_test_sd.cxf,actgen_cxf"
STATE="utd"
TIME="1582062235"
SIZE="2515"
ENDFILE
VALUE "<project>\component\work\Complex_Mult_test_sd\Complex_Mult_test_sd.vhd,hdl"
STATE="utd"
TIME="1582682683"
SIZE="7069"
PARENT="<project>\component\work\Complex_Mult_test_sd\Complex_Mult_test_sd.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\DPSRAM_C0\DPSRAM_C0.cxf,actgen_cxf"
STATE="utd"
TIME="1582868797"
SIZE="5867"
ENDFILE
VALUE "<project>\component\work\DPSRAM_C0\DPSRAM_C0.vhd,hdl"
STATE="utd"
TIME="1582868796"
SIZE="3889"
PARENT="<project>\component\work\DPSRAM_C0\DPSRAM_C0.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\DPSRAM_C0\DPSRAM_C0_0\DPSRAM_C0_DPSRAM_C0_0_DPSRAM.cxf,actgen_cxf"
STATE="utd"
TIME="1582868796"
SIZE="753"
PARENT="<project>\component\work\DPSRAM_C0\DPSRAM_C0.cxf"
ENDFILE
VALUE "<project>\component\work\DPSRAM_C0\DPSRAM_C0_0\DPSRAM_C0_DPSRAM_C0_0_DPSRAM.vhd,hdl"
STATE="utd"
TIME="1582868796"
SIZE="7136"
PARENT="<project>\component\work\DPSRAM_C0\DPSRAM_C0_0\DPSRAM_C0_DPSRAM_C0_0_DPSRAM.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\FCCC_C0\FCCC_C0.cxf,actgen_cxf"
STATE="utd"
TIME="1582014068"
SIZE="10451"
ENDFILE
VALUE "<project>\component\work\FCCC_C0\FCCC_C0.vhd,hdl"
STATE="utd"
TIME="1582014068"
SIZE="3205"
PARENT="<project>\component\work\FCCC_C0\FCCC_C0.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\FCCC_C0\FCCC_C0_0\FCCC_C0_FCCC_C0_0_FCCC.cxf,actgen_cxf"
STATE="utd"
TIME="1582014068"
SIZE="705"
PARENT="<project>\component\work\FCCC_C0\FCCC_C0.cxf"
ENDFILE
VALUE "<project>\component\work\FCCC_C0\FCCC_C0_0\FCCC_C0_FCCC_C0_0_FCCC.vhd,hdl"
STATE="utd"
TIME="1582014068"
SIZE="5573"
PARENT="<project>\component\work\FCCC_C0\FCCC_C0_0\FCCC_C0_FCCC_C0_0_FCCC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\FFT_Butterfly_test_sd\FFT_Butterfly_test_sd.cxf,actgen_cxf"
STATE="utd"
TIME="1582698721"
SIZE="3298"
ENDFILE
VALUE "<project>\component\work\FFT_Butterfly_test_sd\FFT_Butterfly_test_sd.vhd,hdl"
STATE="utd"
TIME="1582698721"
SIZE="9619"
PARENT="<project>\component\work\FFT_Butterfly_test_sd\FFT_Butterfly_test_sd.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0.cxf,actgen_cxf"
STATE="utd"
TIME="1581986819"
SIZE="4477"
ENDFILE
VALUE "<project>\component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0.vhd,hdl"
STATE="utd"
TIME="1581986819"
SIZE="3990"
PARENT="<project>\component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0_0\HARD_MULT_ADDSUB_C0_HARD_MULT_ADDSUB_C0_0_HARD_MULT_ADDSUB.cxf,actgen_cxf"
STATE="utd"
TIME="1581986819"
SIZE="538"
PARENT="<project>\component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0.cxf"
ENDFILE
VALUE "<project>\component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0_0\HARD_MULT_ADDSUB_C0_HARD_MULT_ADDSUB_C0_0_HARD_MULT_ADDSUB.vhd,hdl"
STATE="utd"
TIME="1581986819"
SIZE="11253"
PARENT="<project>\component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0_0\HARD_MULT_ADDSUB_C0_HARD_MULT_ADDSUB_C0_0_HARD_MULT_ADDSUB.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\HARD_MULT_C0\HARD_MULT_C0.cxf,actgen_cxf"
STATE="utd"
TIME="1581973984"
SIZE="3534"
ENDFILE
VALUE "<project>\component\work\HARD_MULT_C0\HARD_MULT_C0.vhd,hdl"
STATE="utd"
TIME="1581973983"
SIZE="3602"
PARENT="<project>\component\work\HARD_MULT_C0\HARD_MULT_C0.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\HARD_MULT_C0\HARD_MULT_C0_0\HARD_MULT_C0_HARD_MULT_C0_0_HARD_MULT.cxf,actgen_cxf"
STATE="utd"
TIME="1581973983"
SIZE="496"
PARENT="<project>\component\work\HARD_MULT_C0\HARD_MULT_C0.cxf"
ENDFILE
VALUE "<project>\component\work\HARD_MULT_C0\HARD_MULT_C0_0\HARD_MULT_C0_HARD_MULT_C0_0_HARD_MULT.vhd,hdl"
STATE="utd"
TIME="1581973983"
SIZE="11224"
PARENT="<project>\component\work\HARD_MULT_C0\HARD_MULT_C0_0\HARD_MULT_C0_HARD_MULT_C0_0_HARD_MULT.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\mult_speed_test_sd\mult_speed_test_sd.cxf,actgen_cxf"
STATE="utd"
TIME="1582695573"
SIZE="634"
ENDFILE
VALUE "<project>\component\work\OSC_C0\OSC_C0.cxf,actgen_cxf"
STATE="utd"
TIME="1582014057"
SIZE="2913"
ENDFILE
VALUE "<project>\component\work\OSC_C0\OSC_C0.vhd,hdl"
STATE="utd"
TIME="1582014057"
SIZE="3429"
PARENT="<project>\component\work\OSC_C0\OSC_C0.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.cxf,actgen_cxf"
STATE="utd"
TIME="1582014057"
SIZE="460"
PARENT="<project>\component\work\OSC_C0\OSC_C0.cxf"
ENDFILE
VALUE "<project>\component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd,hdl"
STATE="utd"
TIME="1582014057"
SIZE="896"
PARENT="<project>\component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\vhdl_complex_mult_test_sd\vhdl_complex_mult_test_sd.cxf,actgen_cxf"
STATE="utd"
TIME="1582615153"
SIZE="2568"
ENDFILE
VALUE "<project>\component\work\vhdl_complex_mult_test_sd\vhdl_complex_mult_test_sd.vhd,hdl"
STATE="utd"
TIME="1582615153"
SIZE="6270"
PARENT="<project>\component\work\vhdl_complex_mult_test_sd\vhdl_complex_mult_test_sd.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\designer\impl1\Butterfly_HW_DSP.ide_des,ide_des"
STATE="utd"
TIME="1582009467"
SIZE="219"
ENDFILE
VALUE "<project>\designer\impl1\Complex_Mult_test_sd.ide_des,ide_des"
STATE="utd"
TIME="1582241091"
SIZE="330"
ENDFILE
VALUE "<project>\designer\impl1\DPSRAM_C0.ide_des,ide_des"
STATE="utd"
TIME="1583102902"
SIZE="212"
ENDFILE
VALUE "<project>\designer\impl1\FFT.ide_des,ide_des"
STATE="utd"
TIME="1581661044"
SIZE="206"
ENDFILE
VALUE "<project>\designer\impl1\FFT_Butterfly_HW_MATHDSP.ide_des,ide_des"
STATE="utd"
TIME="1582427661"
SIZE="227"
ENDFILE
VALUE "<project>\designer\impl1\FFT_Butterfly_test_sd.ide_des,ide_des"
STATE="utd"
TIME="1582672066"
SIZE="332"
ENDFILE
VALUE "<project>\designer\impl1\FFT_Sample_Loader.ide_des,ide_des"
STATE="utd"
TIME="1582314316"
SIZE="220"
ENDFILE
VALUE "<project>\designer\impl1\FFT_Sample_Outputer.ide_des,ide_des"
STATE="utd"
TIME="1582405855"
SIZE="222"
ENDFILE
VALUE "<project>\designer\impl1\FFT_Transformer.ide_des,ide_des"
STATE="utd"
TIME="1582870441"
SIZE="218"
ENDFILE
VALUE "<project>\designer\impl1\Twiddle_table.ide_des,ide_des"
STATE="utd"
TIME="1581973550"
SIZE="216"
ENDFILE
VALUE "<project>\designer\impl1\vhdl_complex_mult_test_sd.ide_des,ide_des"
STATE="utd"
TIME="1582318536"
SIZE="228"
ENDFILE
VALUE "<project>\hdl\bit_extender_8_to_35.vhd,hdl"
STATE="utd"
TIME="1581993528"
SIZE="1097"
ENDFILE
VALUE "<project>\hdl\Butterfly_HW_DSP.vhd,hdl"
STATE="utd"
TIME="1582615040"
SIZE="10473"
ENDFILE
VALUE "<project>\hdl\FFT.vhd,hdl"
STATE="utd"
TIME="1582245422"
SIZE="16955"
ENDFILE
VALUE "<project>\hdl\FFT_Butterfly_HW_MATHDSP.vhd,hdl"
STATE="utd"
TIME="1583207640"
SIZE="22238"
ENDFILE
VALUE "<project>\hdl\FFT_Package.vhd,hdl"
STATE="utd"
TIME="1583206646"
SIZE="3272"
ENDFILE
VALUE "<project>\hdl\FFT_Sample_Loader.vhd,hdl"
STATE="utd"
TIME="1582340676"
SIZE="9010"
ENDFILE
VALUE "<project>\hdl\FFT_Sample_Outputer.vhd,hdl"
STATE="utd"
TIME="1582346702"
SIZE="6039"
ENDFILE
VALUE "<project>\hdl\FFT_Transformer.vhd,hdl"
STATE="utd"
TIME="1583131348"
SIZE="18805"
ENDFILE
VALUE "<project>\hdl\FFT_Transform_test.vhd,hdl"
STATE="utd"
TIME="1583103652"
SIZE="12206"
ENDFILE
VALUE "<project>\hdl\LFSR_Fib_Gen.vhd,hdl"
STATE="utd"
TIME="1582615421"
SIZE="1486"
ENDFILE
VALUE "<project>\hdl\Twiddle_table.vhd,hdl"
STATE="utd"
TIME="1582807893"
SIZE="2495408"
ENDFILE
VALUE "<project>\simulation\Butterfly_HW_DSP_tb_presynth_simulation.log,log"
STATE="utd"
TIME="1582320535"
SIZE="3838"
ENDFILE
VALUE "<project>\simulation\FFT_Sample_Outputer_tb_presynth_simulation.log,log"
STATE="utd"
TIME="1582346842"
SIZE="5732"
ENDFILE
VALUE "<project>\simulation\FFT_Transform_tb_presynth_simulation.log,log"
STATE="utd"
TIME="1582874630"
SIZE="7171"
ENDFILE
VALUE "<project>\simulation\FFT_Transform_test_tb_presynth_simulation.log,log"
STATE="utd"
TIME="1583140714"
SIZE="17067"
ENDFILE
VALUE "<project>\simulation\run.do,do"
STATE="utd"
TIME="1583142523"
SIZE="1096"
ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd"
TIME="1583142523"
SIZE="233"
ENDFILE
VALUE "<project>\simulation\tesbench_presynth_simulation.log,log"
STATE="utd"
TIME="1582769926"
SIZE="10558"
ENDFILE
VALUE "<project>\simulation\Twiddle_Table_tb_presynth_simulation.log,log"
STATE="utd"
TIME="1582321775"
SIZE="27040"
ENDFILE
VALUE "<project>\stimulus\Butterfly_HW_DSP_tb.vhd,tb_hdl"
STATE="utd"
TIME="1582016147"
SIZE="7499"
ENDFILE
VALUE "<project>\stimulus\FFT_Butterfly_HW_MATHDSP_tb.vhd,tb_hdl"
STATE="utd"
TIME="1583207589"
SIZE="16769"
ENDFILE
VALUE "<project>\stimulus\FFT_Sample_Loader_tb.vhd,tb_hdl"
STATE="utd"
TIME="1582331754"
SIZE="6393"
ENDFILE
VALUE "<project>\stimulus\FFT_Sample_Outputer_tb.vhd,tb_hdl"
STATE="utd"
TIME="1582346800"
SIZE="6604"
ENDFILE
VALUE "<project>\stimulus\FFT_tb.vhd,tb_hdl"
STATE="utd"
TIME="1581545606"
SIZE="4977"
ENDFILE
VALUE "<project>\stimulus\FFT_Transform_tb.vhd,tb_hdl"
STATE="utd"
TIME="1583041022"
SIZE="23097"
ENDFILE
VALUE "<project>\stimulus\FFT_Transform_test_tb.vhd,tb_hdl"
STATE="utd"
TIME="1583136051"
SIZE="32803"
ENDFILE
VALUE "<project>\stimulus\Twiddle_Table_tb.vhd,tb_hdl"
STATE="utd"
TIME="1582321168"
SIZE="4716"
ENDFILE
VALUE "<project>\synthesis\Butterfly_HW_DSP.so,so"
STATE="utd"
TIME="1582016169"
SIZE="258"
ENDFILE
VALUE "<project>\synthesis\Butterfly_HW_DSP.vm,syn_vm"
STATE="ood"
TIME="1582016168"
SIZE="101761"
ENDFILE
VALUE "<project>\synthesis\Butterfly_HW_DSP_syn.prj,prj"
STATE="utd"
TIME="1582016184"
SIZE="1915"
ENDFILE
VALUE "<project>\synthesis\Butterfly_HW_DSP_vm.sdc,syn_sdc"
STATE="utd"
TIME="1582016168"
SIZE="901"
ENDFILE
VALUE "<project>\synthesis\Complex_Mult_test_sd.so,so"
STATE="utd"
TIME="1582062488"
SIZE="266"
ENDFILE
VALUE "<project>\synthesis\Complex_Mult_test_sd.vm,syn_vm"
STATE="ood"
TIME="1582062488"
SIZE="13650"
ENDFILE
VALUE "<project>\synthesis\Complex_Mult_test_sd_syn.prj,prj"
STATE="utd"
TIME="1582062501"
SIZE="2650"
ENDFILE
VALUE "<project>\synthesis\Complex_Mult_test_sd_vm.sdc,syn_sdc"
STATE="utd"
TIME="1582062488"
SIZE="905"
ENDFILE
VALUE "<project>\synthesis\DPSRAM_C0.so,so"
STATE="utd"
TIME="1583056941"
SIZE="244"
ENDFILE
VALUE "<project>\synthesis\DPSRAM_C0.vm,syn_vm"
STATE="ood"
TIME="1583056940"
SIZE="11592"
ENDFILE
VALUE "<project>\synthesis\FFT_Butterfly_test_sd.so,so"
STATE="utd"
TIME="1582699070"
SIZE="268"
ENDFILE
VALUE "<project>\synthesis\FFT_Butterfly_test_sd.vm,syn_vm"
STATE="ood"
TIME="1582699070"
SIZE="68694"
ENDFILE
VALUE "<project>\synthesis\FFT_Butterfly_test_sd_syn.prj,prj"
STATE="utd"
TIME="1582699174"
SIZE="3059"
ENDFILE
VALUE "<project>\synthesis\FFT_Butterfly_test_sd_vm.sdc,syn_sdc"
STATE="utd"
TIME="1582699070"
SIZE="951"
ENDFILE
VALUE "<project>\synthesis\FFT_Transform_test.so,so"
STATE="utd"
TIME="1583103530"
SIZE="262"
ENDFILE
VALUE "<project>\synthesis\FFT_Transform_test.vm,syn_vm"
STATE="ood"
TIME="1583103529"
SIZE="102277"
ENDFILE
VALUE "<project>\synthesis\FFT_Transform_test_sd.so,so"
STATE="utd"
TIME="1582964536"
SIZE="268"
ENDFILE
VALUE "<project>\synthesis\FFT_Transform_test_sd_syn.prj,prj"
STATE="utd"
TIME="1583057055"
SIZE="2839"
ENDFILE
VALUE "<project>\synthesis\FFT_Transform_test_sd_vm.sdc,syn_sdc"
STATE="utd"
TIME="1582964535"
SIZE="906"
ENDFILE
VALUE "<project>\synthesis\FFT_Transform_test_syn.prj,prj"
STATE="utd"
TIME="1583104195"
SIZE="2780"
ENDFILE
VALUE "<project>\synthesis\FFT_Transform_test_vm.sdc,syn_sdc"
STATE="utd"
TIME="1583103530"
SIZE="903"
ENDFILE
VALUE "<project>\synthesis\HARD_MULT_ADDSUB_C0.so,so"
STATE="utd"
TIME="1582013598"
SIZE="264"
ENDFILE
VALUE "<project>\synthesis\HARD_MULT_ADDSUB_C0.vm,syn_vm"
STATE="ood"
TIME="1582013597"
SIZE="15003"
ENDFILE
VALUE "<project>\synthesis\HARD_MULT_ADDSUB_C0_syn.prj,prj"
STATE="utd"
TIME="1582013598"
SIZE="2331"
ENDFILE
VALUE "<project>\synthesis\HARD_MULT_ADDSUB_C0_vm.sdc,syn_sdc"
STATE="utd"
TIME="1582013597"
SIZE="798"
ENDFILE
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.so,so"
STATE="utd"
TIME="1582615667"
SIZE="276"
ENDFILE
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.vm,syn_vm"
STATE="ood"
TIME="1582615667"
SIZE="61260"
ENDFILE
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd_syn.prj,prj"
STATE="utd"
TIME="1582615683"
SIZE="2756"
ENDFILE
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd_vm.sdc,syn_sdc"
STATE="utd"
TIME="1582615667"
SIZE="952"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "DPSRAM_C0::work"
FILE "<project>\component\work\DPSRAM_C0\DPSRAM_C0.vhd,hdl"
LIST ProjectState5.1
LIST Impl1
ideSYNTHESIS(<project>\synthesis\FFT_Transform_test.vm,syn_vm)=StateSuccess
ideSYNTHESIS(<project>\synthesis\Butterfly_HW_DSP.vm,syn_vm)=StateSuccess
ideSYNTHESIS(<project>\synthesis\Complex_Mult_test_sd.vm,syn_vm)=StateSuccess
ideSYNTHESIS(<project>\synthesis\FFT_Butterfly_test_sd.vm,syn_vm)=StateSuccess
ideSYNTHESIS(<project>\synthesis\HARD_MULT_ADDSUB_C0.vm,syn_vm)=StateSuccess
ideSYNTHESIS(<project>\synthesis\vhdl_complex_mult_test_sd.vm,syn_vm)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\DPSRAM_C0.edn,syn_edn"
VALUE "<project>\synthesis\DPSRAM_C0.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\DPSRAM_C0_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\DPSRAM_C0_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\DPSRAM_C0_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\DPSRAM_C0_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\DPSRAM_C0_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\DPSRAM_C0.adb,adb"
VALUE "<project>\designer\impl1\DPSRAM_C0.fdb,fdb"
VALUE "<project>\designer\impl1\DPSRAM_C0.pdb,pdb"
VALUE "<project>\designer\impl1\DPSRAM_C0.stp,stp"
VALUE "<project>\designer\impl1\DPSRAM_C0_fp\DPSRAM_C0.pro,pro"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.vm,syn_vm"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "Butterfly_HW_DSP::work"
FILE "<project>\hdl\Butterfly_HW_DSP.vhd,hdl"
LIST AssociatedStimulus
VALUE "<project>\stimulus\Butterfly_HW_DSP_tb.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\Butterfly_HW_DSP.edn,syn_edn"
VALUE "<project>\synthesis\Butterfly_HW_DSP.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\Butterfly_HW_DSP_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\Butterfly_HW_DSP_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\Butterfly_HW_DSP_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\Butterfly_HW_DSP_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\Butterfly_HW_DSP_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\Butterfly_HW_DSP.adb,adb"
VALUE "<project>\designer\impl1\Butterfly_HW_DSP.fdb,fdb"
VALUE "<project>\designer\impl1\Butterfly_HW_DSP.pdb,pdb"
VALUE "<project>\designer\impl1\Butterfly_HW_DSP.stp,stp"
VALUE "<project>\designer\impl1\Butterfly_HW_DSP_fp\Butterfly_HW_DSP.pro,pro"
VALUE "<project>\synthesis\Complex_Mult_test_sd.vm,syn_vm"
VALUE "<project>\synthesis\Complex_Mult_test_sd_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "FFT_Butterfly_HW_MATHDSP::work"
FILE "<project>\hdl\FFT_Butterfly_HW_MATHDSP.vhd,hdl"
LIST AssociatedStimulus
VALUE "<project>\stimulus\FFT_Butterfly_HW_MATHDSP_tb.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.vm,syn_vm"
VALUE "<project>\synthesis\FFT_Butterfly_HW_MATHDSP.edn,syn_edn"
VALUE "<project>\synthesis\FFT_Butterfly_HW_MATHDSP.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\FFT_Butterfly_HW_MATHDSP_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\FFT_Butterfly_HW_MATHDSP_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\FFT_Butterfly_HW_MATHDSP_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\FFT_Butterfly_HW_MATHDSP_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\FFT_Butterfly_HW_MATHDSP_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\FFT_Butterfly_HW_MATHDSP.adb,adb"
VALUE "<project>\designer\impl1\FFT_Butterfly_HW_MATHDSP.fdb,fdb"
VALUE "<project>\designer\impl1\FFT_Butterfly_HW_MATHDSP.pdb,pdb"
VALUE "<project>\designer\impl1\FFT_Butterfly_HW_MATHDSP.stp,stp"
VALUE "<project>\designer\impl1\FFT_Butterfly_HW_MATHDSP_fp\FFT_Butterfly_HW_MATHDSP.pro,pro"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "FFT_Sample_Loader::work"
FILE "<project>\hdl\FFT_Sample_Loader.vhd,hdl"
LIST AssociatedStimulus
VALUE "<project>\stimulus\FFT_Sample_Loader_tb.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.vm,syn_vm"
VALUE "<project>\synthesis\FFT_Sample_Loader.edn,syn_edn"
VALUE "<project>\synthesis\FFT_Sample_Loader.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\FFT_Sample_Loader_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\FFT_Sample_Loader_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\FFT_Sample_Loader_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\FFT_Sample_Loader_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\FFT_Sample_Loader_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\FFT_Sample_Loader.adb,adb"
VALUE "<project>\designer\impl1\FFT_Sample_Loader.fdb,fdb"
VALUE "<project>\designer\impl1\FFT_Sample_Loader.pdb,pdb"
VALUE "<project>\designer\impl1\FFT_Sample_Loader.stp,stp"
VALUE "<project>\designer\impl1\FFT_Sample_Loader_fp\FFT_Sample_Loader.pro,pro"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "FFT_Sample_Outputer::work"
FILE "<project>\hdl\FFT_Sample_Outputer.vhd,hdl"
LIST AssociatedStimulus
VALUE "<project>\stimulus\FFT_Sample_Outputer_tb.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "FFT_Transform_test::work"
FILE "<project>\hdl\FFT_Transform_test.vhd,hdl"
LIST AssociatedStimulus
VALUE "<project>\stimulus\FFT_Transform_test_tb.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\FFT_Transform_test.edn,syn_edn"
VALUE "<project>\synthesis\FFT_Transform_test.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\FFT_Transform_test_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\FFT_Transform_test_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\FFT_Transform_test_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\FFT_Transform_test_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\FFT_Transform_test_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\FFT_Transform_test.adb,adb"
VALUE "<project>\designer\impl1\FFT_Transform_test.fdb,fdb"
VALUE "<project>\designer\impl1\FFT_Transform_test.pdb,pdb"
VALUE "<project>\designer\impl1\FFT_Transform_test.stp,stp"
VALUE "<project>\designer\impl1\FFT_Transform_test_fp\FFT_Transform_test.pro,pro"
VALUE "<project>\synthesis\FFT_Transform_test.vm,syn_vm"
VALUE "<project>\synthesis\FFT_Transform_test_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "HARD_MULT_ADDSUB_C0::work"
FILE "<project>\component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0.vhd,hdl"
LIST AssociatedStimulus
VALUE "<project>\stimulus\Butterfly_HW_DSP_tb.vhd,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "vhdl_complex_mult_test_sd::work"
FILE "<project>\component\work\vhdl_complex_mult_test_sd\vhdl_complex_mult_test_sd.vhd,hdl"
LIST ProjectState5.1
LIST Impl1
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.edn,syn_edn"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\vhdl_complex_mult_test_sd_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\vhdl_complex_mult_test_sd_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\vhdl_complex_mult_test_sd_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\vhdl_complex_mult_test_sd_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\vhdl_complex_mult_test_sd_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\vhdl_complex_mult_test_sd.adb,adb"
VALUE "<project>\designer\impl1\vhdl_complex_mult_test_sd.fdb,fdb"
VALUE "<project>\designer\impl1\vhdl_complex_mult_test_sd.pdb,pdb"
VALUE "<project>\designer\impl1\vhdl_complex_mult_test_sd.stp,stp"
VALUE "<project>\designer\impl1\vhdl_complex_mult_test_sd_fp\vhdl_complex_mult_test_sd.pro,pro"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.vm,syn_vm"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST Butterfly_HW_DSP
VALUE "<project>\stimulus\Butterfly_HW_DSP_tb.vhd,tb_hdl"
ENDLIST
LIST FFT_Transform_test
VALUE "<project>\stimulus\FFT_Transform_test_tb.vhd,tb_hdl"
ENDLIST
LIST FFT_Butterfly_HW_MATHDSP
VALUE "<project>\stimulus\FFT_Butterfly_HW_MATHDSP_tb.vhd,tb_hdl"
ENDLIST
LIST FFT_Sample_Outputer
VALUE "<project>\stimulus\FFT_Sample_Outputer_tb.vhd,tb_hdl"
ENDLIST
LIST FFT_Sample_Loader
VALUE "<project>\stimulus\FFT_Sample_Loader_tb.vhd,tb_hdl"
ENDLIST
LIST HARD_MULT_ADDSUB_C0
VALUE "<project>\stimulus\Butterfly_HW_DSP_tb.vhd,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=20000ns
Resolution=1fs
VsimOpt=
EntityName=FFT_Butterfly_HW_MATHDSP_tb
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DisablePulseFiltering=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
TimeUnit=1
TimeUnitBase=ns
Precision=100
PrecisionBase=ps
ENDLIST
LIST ModelSimLibPath
UseCustomPath=TRUE
LibraryPath=C:/Microsemi/Libero_SoC_v12.1/Designer/lib/modelsimpro/precompiled\vlog\SmartFusion2
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=FALSE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
PeriInitStandalone=FALSE
OnDemandBuildDH=TRUE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
VmNetlistFlowOn=TRUE
EnableDesignSeparationOn=FALSE
EnableSETMitigationOn=FALSE
DisplayFanoutLimit=10
AbortFlowOnPDCErrorsOn=TRUE
AbortFlowOnSDCErrorsOn=TRUE
InstantiateInSmartDesign=TRUE
FlashProInputFile=pdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsole"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="eclipse.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="SynplifyProME"
FUNCTION="Synthesis"
TOOL="Synplify Pro ME"
LOCATION="C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\bin\synplify_pro.exe"
PARAM="-licensetype synplifypro_actel -batch -log synplify.log"
BATCH=1
LICENSE=""
IS32BIT="1"
EndProfile
NAME="ModelSimME"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Microsemi\Libero_SoC_v12.1\ModelSim\win32acoem\modelsim.exe"
PARAM=" -l I2C_LITEON_Op_Sens_test_tb_presynth_simulation.log "
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="FPExpress"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Microsemi\Libero_SoC_v12.1\Designer\binfp\FPExpress.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="IdentifyDebugger"
FUNCTION="IdentifyDebugger"
TOOL="Identify Debugger"
LOCATION="C:\Microsemi\Libero_SoC_v12.1\Identify\bin\identify_debugger.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "DPSRAM_C0::work"
LIST Impl1
ideSYNTHESIS(<project>\synthesis\FFT_Transform_test.vm,syn_vm)=StateSuccess
ideSYNTHESIS(<project>\synthesis\Butterfly_HW_DSP.vm,syn_vm)=StateSuccess
ideSYNTHESIS(<project>\synthesis\Complex_Mult_test_sd.vm,syn_vm)=StateSuccess
ideSYNTHESIS(<project>\synthesis\FFT_Butterfly_test_sd.vm,syn_vm)=StateSuccess
ideSYNTHESIS(<project>\synthesis\HARD_MULT_ADDSUB_C0.vm,syn_vm)=StateSuccess
ideSYNTHESIS(<project>\synthesis\vhdl_complex_mult_test_sd.vm,syn_vm)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\DPSRAM_C0.edn,syn_edn"
VALUE "<project>\synthesis\DPSRAM_C0.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\DPSRAM_C0_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\DPSRAM_C0_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\DPSRAM_C0_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\DPSRAM_C0_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\DPSRAM_C0_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\DPSRAM_C0.adb,adb"
VALUE "<project>\designer\impl1\DPSRAM_C0.fdb,fdb"
VALUE "<project>\designer\impl1\DPSRAM_C0.pdb,pdb"
VALUE "<project>\designer\impl1\DPSRAM_C0.stp,stp"
VALUE "<project>\designer\impl1\DPSRAM_C0_fp\DPSRAM_C0.pro,pro"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.vm,syn_vm"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "Butterfly_HW_DSP::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\Butterfly_HW_DSP.edn,syn_edn"
VALUE "<project>\synthesis\Butterfly_HW_DSP.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\Butterfly_HW_DSP_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\Butterfly_HW_DSP_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\Butterfly_HW_DSP_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\Butterfly_HW_DSP_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\Butterfly_HW_DSP_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\Butterfly_HW_DSP.adb,adb"
VALUE "<project>\designer\impl1\Butterfly_HW_DSP.fdb,fdb"
VALUE "<project>\designer\impl1\Butterfly_HW_DSP.pdb,pdb"
VALUE "<project>\designer\impl1\Butterfly_HW_DSP.stp,stp"
VALUE "<project>\designer\impl1\Butterfly_HW_DSP_fp\Butterfly_HW_DSP.pro,pro"
VALUE "<project>\synthesis\Complex_Mult_test_sd.vm,syn_vm"
VALUE "<project>\synthesis\Complex_Mult_test_sd_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "FFT_Butterfly_HW_MATHDSP::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.vm,syn_vm"
VALUE "<project>\synthesis\FFT_Butterfly_HW_MATHDSP.edn,syn_edn"
VALUE "<project>\synthesis\FFT_Butterfly_HW_MATHDSP.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\FFT_Butterfly_HW_MATHDSP_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\FFT_Butterfly_HW_MATHDSP_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\FFT_Butterfly_HW_MATHDSP_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\FFT_Butterfly_HW_MATHDSP_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\FFT_Butterfly_HW_MATHDSP_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\FFT_Butterfly_HW_MATHDSP.adb,adb"
VALUE "<project>\designer\impl1\FFT_Butterfly_HW_MATHDSP.fdb,fdb"
VALUE "<project>\designer\impl1\FFT_Butterfly_HW_MATHDSP.pdb,pdb"
VALUE "<project>\designer\impl1\FFT_Butterfly_HW_MATHDSP.stp,stp"
VALUE "<project>\designer\impl1\FFT_Butterfly_HW_MATHDSP_fp\FFT_Butterfly_HW_MATHDSP.pro,pro"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "FFT_Sample_Loader::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.vm,syn_vm"
VALUE "<project>\synthesis\FFT_Sample_Loader.edn,syn_edn"
VALUE "<project>\synthesis\FFT_Sample_Loader.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\FFT_Sample_Loader_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\FFT_Sample_Loader_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\FFT_Sample_Loader_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\FFT_Sample_Loader_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\FFT_Sample_Loader_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\FFT_Sample_Loader.adb,adb"
VALUE "<project>\designer\impl1\FFT_Sample_Loader.fdb,fdb"
VALUE "<project>\designer\impl1\FFT_Sample_Loader.pdb,pdb"
VALUE "<project>\designer\impl1\FFT_Sample_Loader.stp,stp"
VALUE "<project>\designer\impl1\FFT_Sample_Loader_fp\FFT_Sample_Loader.pro,pro"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "FFT_Sample_Outputer::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "FFT_Transform_test::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\FFT_Transform_test.edn,syn_edn"
VALUE "<project>\synthesis\FFT_Transform_test.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\FFT_Transform_test_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\FFT_Transform_test_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\FFT_Transform_test_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\FFT_Transform_test_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\FFT_Transform_test_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\FFT_Transform_test.adb,adb"
VALUE "<project>\designer\impl1\FFT_Transform_test.fdb,fdb"
VALUE "<project>\designer\impl1\FFT_Transform_test.pdb,pdb"
VALUE "<project>\designer\impl1\FFT_Transform_test.stp,stp"
VALUE "<project>\designer\impl1\FFT_Transform_test_fp\FFT_Transform_test.pro,pro"
VALUE "<project>\synthesis\FFT_Transform_test.vm,syn_vm"
VALUE "<project>\synthesis\FFT_Transform_test_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "HARD_MULT_ADDSUB_C0::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "vhdl_complex_mult_test_sd::work"
LIST Impl1
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.edn,syn_edn"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.vhd,syn_hdl"
VALUE "<project>\phy_synthesis\vhdl_complex_mult_test_sd_palace.edn,palace_edn"
VALUE "<project>\phy_synthesis\vhdl_complex_mult_test_sd_palace.gcf,palace_gcf"
VALUE "<project>\phy_synthesis\vhdl_complex_mult_test_sd_palace.pdc,palace_pdc"
VALUE "<project>\phy_synthesis\vhdl_complex_mult_test_sd_palace.sdc,palace_sdc"
VALUE "<project>\phy_synthesis\vhdl_complex_mult_test_sd_palace.vhd,palace_hdl"
VALUE "<project>\designer\impl1\vhdl_complex_mult_test_sd.adb,adb"
VALUE "<project>\designer\impl1\vhdl_complex_mult_test_sd.fdb,fdb"
VALUE "<project>\designer\impl1\vhdl_complex_mult_test_sd.pdb,pdb"
VALUE "<project>\designer\impl1\vhdl_complex_mult_test_sd.stp,stp"
VALUE "<project>\designer\impl1\vhdl_complex_mult_test_sd_fp\vhdl_complex_mult_test_sd.pro,pro"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd.vm,syn_vm"
VALUE "<project>\synthesis\vhdl_complex_mult_test_sd_sdc.sdc,syn_sdc"
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
ORIENTATION;HORIZONTAL
StartPage;StartPage;0
ACTIVEVIEW;StartPage
ENDLIST
LIST ModuleSubBlockList
LIST "bit_extender_8_to_35::work","hdl\bit_extender_8_to_35.vhd","FALSE","FALSE"
ENDLIST
LIST "Complex_Mult_test_sd::work","component\work\Complex_Mult_test_sd\Complex_Mult_test_sd.vhd","TRUE","FALSE"
SUBBLOCK "HARD_MULT_ADDSUB_C0::work","component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0.vhd","TRUE","FALSE"
SUBBLOCK "HARD_MULT_C0::work","component\work\HARD_MULT_C0\HARD_MULT_C0.vhd","TRUE","FALSE"
SUBBLOCK "bit_extender_8_to_35::work","hdl\bit_extender_8_to_35.vhd","FALSE","FALSE"
SUBBLOCK "LFSR_Fib_Gen::work","hdl\LFSR_Fib_Gen.vhd","FALSE","FALSE"
ENDLIST
LIST "DPSRAM_C0::work","component\work\DPSRAM_C0\DPSRAM_C0.vhd","TRUE","FALSE"
SUBBLOCK "DPSRAM_C0_DPSRAM_C0_0_DPSRAM::work","component\work\DPSRAM_C0\DPSRAM_C0_0\DPSRAM_C0_DPSRAM_C0_0_DPSRAM.vhd","FALSE","FALSE"
ENDLIST
LIST "DPSRAM_C0_DPSRAM_C0_0_DPSRAM::work","component\work\DPSRAM_C0\DPSRAM_C0_0\DPSRAM_C0_DPSRAM_C0_0_DPSRAM.vhd","FALSE","FALSE"
ENDLIST
LIST "Butterfly_HW_DSP::work","hdl\Butterfly_HW_DSP.vhd","FALSE","FALSE"
SUBBLOCK "Twiddle_table::work","hdl\Twiddle_table.vhd","FALSE","FALSE"
ENDLIST
LIST "LFSR_Fib_Gen::work","hdl\LFSR_Fib_Gen.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "Twiddle_table::work","hdl\Twiddle_table.vhd","FALSE","FALSE"
ENDLIST
LIST "Twiddle_table::work","hdl\Twiddle_table.vhd","FALSE","FALSE"
ENDLIST
LIST "Twiddle_table::work","hdl\Twiddle_table.vhd","FALSE","FALSE"
ENDLIST
LIST "FCCC_C0::work","component\work\FCCC_C0\FCCC_C0.vhd","TRUE","FALSE"
SUBBLOCK "FCCC_C0_FCCC_C0_0_FCCC::work","component\work\FCCC_C0\FCCC_C0_0\FCCC_C0_FCCC_C0_0_FCCC.vhd","FALSE","FALSE"
ENDLIST
LIST "FCCC_C0_FCCC_C0_0_FCCC::work","component\work\FCCC_C0\FCCC_C0_0\FCCC_C0_FCCC_C0_0_FCCC.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_Butterfly_HW_MATHDSP::work","hdl\FFT_Butterfly_HW_MATHDSP.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_Butterfly_test_sd::work","component\work\FFT_Butterfly_test_sd\FFT_Butterfly_test_sd.vhd","TRUE","FALSE"
SUBBLOCK "FCCC_C0::work","component\work\FCCC_C0\FCCC_C0.vhd","TRUE","FALSE"
SUBBLOCK "FFT_Butterfly_HW_MATHDSP::work","hdl\FFT_Butterfly_HW_MATHDSP.vhd","FALSE","FALSE"
SUBBLOCK "OSC_C0::work","component\work\OSC_C0\OSC_C0.vhd","TRUE","FALSE"
SUBBLOCK "LFSR_Fib_Gen::work","hdl\LFSR_Fib_Gen.vhd","FALSE","FALSE"
SUBBLOCK "Twiddle_table::work","hdl\Twiddle_table.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_package::work","hdl\FFT_Package.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_Sample_Loader::work","hdl\FFT_Sample_Loader.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_Sample_Outputer::work","hdl\FFT_Sample_Outputer.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_Transform_test::work","hdl\FFT_Transform_test.vhd","FALSE","FALSE"
SUBBLOCK "DPSRAM_C0::work","component\work\DPSRAM_C0\DPSRAM_C0.vhd","TRUE","FALSE"
SUBBLOCK "FFT_Transformer::work","hdl\FFT_Transformer.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_Transformer::work","hdl\FFT_Transformer.vhd","FALSE","FALSE"
SUBBLOCK "FFT_Butterfly_HW_MATHDSP::work","hdl\FFT_Butterfly_HW_MATHDSP.vhd","FALSE","FALSE"
SUBBLOCK "Twiddle_table::work","hdl\Twiddle_table.vhd","FALSE","FALSE"
SUBBLOCK "Twiddle_table::work","hdl\Twiddle_table.vhd","FALSE","FALSE"
ENDLIST
LIST "HARD_MULT_ADDSUB_C0::work","component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0.vhd","TRUE","FALSE"
SUBBLOCK "HARD_MULT_ADDSUB_C0_HARD_MULT_ADDSUB_C0_0_HARD_MULT_ADDSUB::work","component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0_0\HARD_MULT_ADDSUB_C0_HARD_MULT_ADDSUB_C0_0_HARD_MULT_ADDSUB.vhd","FALSE","FALSE"
ENDLIST
LIST "HARD_MULT_ADDSUB_C0_HARD_MULT_ADDSUB_C0_0_HARD_MULT_ADDSUB::work","component\work\HARD_MULT_ADDSUB_C0\HARD_MULT_ADDSUB_C0_0\HARD_MULT_ADDSUB_C0_HARD_MULT_ADDSUB_C0_0_HARD_MULT_ADDSUB.vhd","FALSE","FALSE"
ENDLIST
LIST "HARD_MULT_C0::work","component\work\HARD_MULT_C0\HARD_MULT_C0.vhd","TRUE","FALSE"
SUBBLOCK "HARD_MULT_C0_HARD_MULT_C0_0_HARD_MULT::work","component\work\HARD_MULT_C0\HARD_MULT_C0_0\HARD_MULT_C0_HARD_MULT_C0_0_HARD_MULT.vhd","FALSE","FALSE"
ENDLIST
LIST "HARD_MULT_C0_HARD_MULT_C0_0_HARD_MULT::work","component\work\HARD_MULT_C0\HARD_MULT_C0_0\HARD_MULT_C0_HARD_MULT_C0_0_HARD_MULT.vhd","FALSE","FALSE"
ENDLIST
LIST "mult_speed_test_sd::work","component\work\mult_speed_test_sd\mult_speed_test_sd.cxf","TRUE","FALSE"
ENDLIST
LIST "OSC_C0::work","component\work\OSC_C0\OSC_C0.vhd","TRUE","FALSE"
SUBBLOCK "OSC_C0_OSC_C0_0_OSC::work","component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd","FALSE","FALSE"
ENDLIST
LIST "OSC_C0_OSC_C0_0_OSC::work","component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd","FALSE","FALSE"
SUBBLOCK "RCOSC_25_50MHZ::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_1MHZ_FAB::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "RCOSC_25_50MHZ_FAB::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "vhdl_complex_mult_test_sd::work","component\work\vhdl_complex_mult_test_sd\vhdl_complex_mult_test_sd.vhd","TRUE","FALSE"
SUBBLOCK "FCCC_C0::work","component\work\FCCC_C0\FCCC_C0.vhd","TRUE","FALSE"
SUBBLOCK "OSC_C0::work","component\work\OSC_C0\OSC_C0.vhd","TRUE","FALSE"
SUBBLOCK "Butterfly_HW_DSP::work","hdl\Butterfly_HW_DSP.vhd","FALSE","FALSE"
SUBBLOCK "LFSR_Fib_Gen::work","hdl\LFSR_Fib_Gen.vhd","FALSE","FALSE"
ENDLIST
LIST "XTLOSC::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "XTLOSC_FAB::work","component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd","FALSE","FALSE"
ENDLIST
LIST "Butterfly_HW_DSP::work","hdl\Butterfly_HW_DSP.vhd","FALSE","FALSE"
SUBBLOCK "Twiddle_table::work","hdl\Twiddle_table.vhd","FALSE","FALSE"
ENDLIST
LIST "Butterfly_HW_DSP_tb::work","stimulus\Butterfly_HW_DSP_tb.vhd","FALSE","TRUE"
SUBBLOCK "Butterfly_HW_DSP::work","hdl\Butterfly_HW_DSP.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_Sample_Outputer::work","hdl\FFT_Sample_Outputer.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT::work","","FALSE","FALSE"
ENDLIST
LIST "FFT_Butterfly_HW_MATHDSP_tb::work","stimulus\FFT_Butterfly_HW_MATHDSP_tb.vhd","FALSE","TRUE"
SUBBLOCK "FFT_Butterfly_HW_MATHDSP::work","hdl\FFT_Butterfly_HW_MATHDSP.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_Sample_Loader_tb::work","stimulus\FFT_Sample_Loader_tb.vhd","FALSE","TRUE"
SUBBLOCK "FFT_Sample_Loader::work","hdl\FFT_Sample_Loader.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_Sample_Outputer_tb::work","stimulus\FFT_Sample_Outputer_tb.vhd","FALSE","TRUE"
SUBBLOCK "FFT_Sample_Outputer::work","hdl\FFT_Sample_Outputer.vhd","FALSE","FALSE"
ENDLIST
LIST "FFT_tb::work","stimulus\FFT_tb.vhd","FALSE","TRUE"
SUBBLOCK "FFT::work","","FALSE","FALSE"
ENDLIST
LIST "FFT_Transform_test_tb::work","stimulus\FFT_Transform_test_tb.vhd","FALSE","TRUE"
SUBBLOCK "FFT_Transform_test::work","hdl\FFT_Transform_test.vhd","FALSE","FALSE"
ENDLIST
LIST "Twiddle_table::work","hdl\Twiddle_table.vhd","FALSE","FALSE"
ENDLIST
LIST "Twiddle_Table_tb::work","stimulus\Twiddle_Table_tb.vhd","FALSE","TRUE"
SUBBLOCK "Twiddle_table::work","hdl\Twiddle_table.vhd","FALSE","FALSE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
ENDLIST
LIST IOTabList
ENDLIST
LIST FPTabList
ENDLIST
LIST TimingTabList
ENDLIST
LIST FDCTabList
ENDLIST
