BATCH:T
MGNCMPL:F
MGNTIMER:F
GEN_BEHV_MODULE:F
DESDIR:C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\FFT_Core\component\work\DPSRAM_C0\DPSRAM_C0_0\
DESIGN:DPSRAM_C0_DPSRAM_C0_0_DPSRAM
OUTFORMAT:VHDL
ADDRESSA_PN:A_ADDR
ADDRESSB_PN:B_ADDR
RESET_POLARITY:2
WE_POLARITY:2
A_CLK_EDGE:RISE
WDEPTH:1024
A_DOUT_ARST_PN:A_DOUT_ARST_N
A_DOUT_ARST_POLARITY:2
A_DOUT_EN_PN:A_DOUT_EN
A_DOUT_EN_POLARITY:2
A_DOUT_SRST_PN:A_DOUT_SRST_N
A_DOUT_SRST_POLARITY:2
PMODE1:0
WWIDTH:18
WMODE1:0
BLKA_PN:A_BLK
BLKB_PN:B_BLK
RE_POLARITY:2
RCLK_EDGE:RISE
RDEPTH:1024
B_DOUT_ARST_PN:B_DOUT_ARST_N
B_DOUT_ARST_POLARITY:2
B_DOUT_EN_PN:B_DOUT_EN
B_DOUT_EN_POLARITY:2
B_DOUT_SRST_PN:B_DOUT_SRST_N
B_DOUT_SRST_POLARITY:2
PMODE2:0
RWIDTH:18
WMODE2:0
CASCADE:0
CLKA_PN:A_CLK
CLKB_PN:B_CLK
CLKS:1
WCLK_EDGE:RISE
CLOCK_PN:CLK
DATAA_IN_PN:A_DIN
DATAA_OUT_PN:A_DOUT
DATAB_IN_PN:B_DIN
DATAB_OUT_PN:B_DOUT
FAM:SmartFusion2
INIT_RAM:T
LPMTYPE:LPM_RAM
PTYPE:2
RESET_PN:ARST_N
RWA_PN:A_WEN
RWB_PN:B_WEN
SD_EXPORT_HIDDEN_PORTS:false
DEVICE:1000
