<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>FFT_Butterfly_test_sd</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./FFT_Butterfly_test_sd.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./FFT_Butterfly_test_sd_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="2"><name>./FFT_Butterfly_test_sd.vhd</name><fileType>VHDLSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SmartCoreDesign</category><function>SmartDesign</function><variation>SmartDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SmartCoreDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><previousType/><preDesignInGoodState>false</preDesignInGoodState><componentRef library="" name="" vendor="" version=""/><dependentModules><module module_class="ComponentModule" name="FCCC_C0::work" state="GOOD" type="1"/><module module_class="ComponentModule" name="OSC_C0::work" state="GOOD" type="1"/><module file="hdl/FFT_Butterfly_HW_MATHDSP.vhd" id_library="Private" id_name="FFT_Butterfly_HW_MATHDSP" id_vendor="User" id_version="1.0" module_class="HDLSpiritModule" name="FFT_Butterfly_HW_MATHDSP" state="GOOD" type="4"/><module file="hdl/LFSR_Fib_Gen.vhd" id_library="Private" id_name="LFSR_Fib_Gen" id_vendor="User" id_version="1.0" module_class="HDLSpiritModule" name="LFSR_Fib_Gen" state="GOOD" type="4"/><module file="hdl/Twiddle_table.vhd" id_library="Private" id_name="Twiddle_table" id_vendor="User" id_version="1.0" module_class="HDLSpiritModule" name="Twiddle_table" state="GOOD" type="4"/></dependentModules></vendorExtensions><model><signals><signal><name>calc_done</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>imag_b_out</name><direction>out</direction><left>8</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>real_a_out</name><direction>out</direction><left>8</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>imag_a_out</name><direction>out</direction><left>8</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>real_b_out</name><direction>out</direction><left>8</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>adr_b_out</name><direction>out</direction><left>4</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>adr_a_out</name><direction>out</direction><left>4</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>