<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CORECORDIC_C0_CORECORDIC_C0_0_CORECORDIC</name><vendor/><library/><version/><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>cordic.mon</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType></file><file fileid="1"><name>testVect.mon</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType></file><file fileid="2"><name>coreparameters.vhd</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType></file><file fileid="3"><name>CORECORDIC_C0_CORECORDIC_C0_0_CordicLUT_word.vhd</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType></file><file fileid="4"><name>round.txt</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType></file><file fileid="5"><name>rtl\vhdl\core\CORECORDIC.vhd</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType><vendorExtensions><IncludeInRunDo/><requireUniquify/></vendorExtensions></file><file fileid="6"><name>rtl\vhdl\core\cordic_word.vhd</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType><vendorExtensions><IncludeInRunDo/><requireUniquify/></vendorExtensions></file><file fileid="7"><name>rtl\vhdl\core\cordic_par.vhd</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType><vendorExtensions><IncludeInRunDo/><requireUniquify/></vendorExtensions></file></fileSet><fileSet fileSetId="STIMULUS_FILESET"><file fileid="8"><name>inpTestVect.vhd</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file><file fileid="9"><name>outpTestVect.vhd</name><logicalName>CORECORDIC_LIB</logicalName><userFileType>VHDL</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file><file fileid="10"><name>..\..\..\Actel\DirectCore\CORECORDIC\4.0.102\coreparameters.vhd</name><userFileType>VHDL</userFileType></file><file fileid="11"><name>..\..\..\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhv_pack.vhd</name><fileType>VHDLSource</fileType></file><file fileid="12"><name>..\..\..\Actel\DirectCore\CORECORDIC\4.0.102\rtl\vhdl\test\user\bhvKit.vhd</name><fileType>VHDLSource</fileType></file><file fileid="13"><name>rtl\vhdl\test\user\coreCordic_tb.vhd</name><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>STIMULUS_FILESET</fileSetRef><name>Simulation</name></view></views></hwModel></Component>