<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREABC_C0_COREABC_C0_0_COREABC</name><vendor/><library/><version/><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>./coreparameters_tgi.vhd</name><logicalName>COREABC_LIB</logicalName><userFileType>vhdlSource</userFileType></file><file fileid="1"><name>./rtl\vhdl\core\instructions.vhd</name><logicalName>COREABC_LIB</logicalName><userFileType>vhdlSource</userFileType></file><file fileid="2"><name>./rtl\vhdl\core\acmtable.vhd</name><logicalName>COREABC_LIB</logicalName><userFileType>vhdlSource</userFileType></file><file fileid="3"><name>rtl\vhdl\test\misc.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="4"><name>rtl\vhdl\test\textio.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="5"><name>rtl\vhdl\core\support.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="6"><name>rtl\vhdl\core\ramblocks.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="7"><name>rtl\vhdl\core\instructram.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="8"><name>rtl\vhdl\core\debugblk.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="9"><name>rtl\vhdl\core\coreabc.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="10"><name>rtl\vhdl\core\components.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="11"><name>rtl\vhdl\core\ram128x8_smartfusion2.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="12"><name>rtl\vhdl\core\iram512x9_rtl.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="13"><name>rtl\vhdl\core\ram256x16_rtl.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="14"><name>rtl\vhdl\core\ram256x8_rtl.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="15"><name>rtl\vhdl\core\instructnvm_bb.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file></fileSet><fileSet fileSetId="OTHER_FILESET"><file fileid="16"><name>./CoreABC.log</name><userFileType>LOG</userFileType></file><file fileid="17"><name>./COREABC_C0_COREABC_C0_0_Mem.c</name><userFileType>vhdlSource</userFileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"/><fileSet fileSetId="STIMULUS_FILESET"><file fileid="18"><name>rtl\vhdl\test\misc.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="19"><name>rtl\vhdl\test\textio.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="20"><name>rtl\vhdl\test\testsupport.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="21"><name>rtl\vhdl\test\apbmodel.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="22"><name>rtl\vhdl\test\testbench.vhd</name><logicalName>COREABC_LIB</logicalName><fileType>VHDLSource</fileType><vendorExtensions><ModuleUnderTest>testbench</ModuleUnderTest><SimulationTime>-all</SimulationTime><requireUniquify/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>OTHER_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>Simulation</name></view><view><fileSetRef>STIMULUS_FILESET</fileSetRef><name>SIMULATION</name></view></views></hwModel></Component>