#Build: Synplify Pro (R) N-2018.03M-SP1-1, Build 209R, Oct 23 2018
#install: C:\Microsemi\Libero_SoC_v12.1\SynplifyPro
#OS: Windows 8 6.2
#Hostname: PHOENIX136DESKY

# Mon Nov 25 01:08:16 2019

#Implementation: synthesis


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03M-SP1-1
Install: C:\Microsemi\Libero_SoC_v12.1\SynplifyPro
OS: Windows 6.2

Hostname: PHOENIX136DESKY

Implementation : synthesis
Synopsys HDL Compiler, Version comp2018q2p1, Build 223R, Built Oct 23 2018 09:18:38

@N|Running in 64-bit mode

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03M-SP1-1
Install: C:\Microsemi\Libero_SoC_v12.1\SynplifyPro
OS: Windows 6.2

Hostname: PHOENIX136DESKY

Implementation : synthesis
Synopsys VHDL Compiler, Version comp2018q2p1, Build 223R, Built Oct 23 2018 09:18:38

@N|Running in 64-bit mode
@N:"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\Delta_Sigma_Design\Delta_Sigma_Design.vhd":17:7:17:24|Top entity is set to Delta_Sigma_Design.
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\iram512x9_rtl.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\test\misc.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ram128x8_smartfusion2.vhd changed - recompiling
File C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\lib\generic\smartfusion2.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ram256x16_rtl.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ram256x8_rtl.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\components.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_muxptob3.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_iaddr_reg.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\components.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\FCCC_C0\FCCC_C0_0\FCCC_C0_FCCC_C0_0_FCCC.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Delta_Sigma_Converter.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\timer.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\acmtable.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\instructnvm_bb.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\instructram.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\test\textio.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\debugblk.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\instructions.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\CoreAPB3_C0\CoreAPB3_C0.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\FCCC_C0\FCCC_C0.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\OSC_C0\OSC_C0.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd changed - recompiling
File C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\Delta_Sigma_Design\Delta_Sigma_Design.vhd changed - recompiling
VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

@N: CD231 :"C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\lib\vhd2008\std1164.vhd":890:16:890:17|Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\Delta_Sigma_Design\Delta_Sigma_Design.vhd":17:7:17:24|Synthesizing work.delta_sigma_design.rtl.
@N: CD630 :"C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\lib\generic\smartfusion2.vhd":492:10:492:19|Synthesizing smartfusion2.inbuf_diff.syn_black_box.
Post processing for smartfusion2.inbuf_diff.syn_black_box
Running optimization stage 1 on INBUF_DIFF .......
@N: CD630 :"C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\lib\generic\smartfusion2.vhd":790:10:790:17|Synthesizing smartfusion2.sysreset.syn_black_box.
Post processing for smartfusion2.sysreset.syn_black_box
Running optimization stage 1 on SYSRESET .......
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\OSC_C0\OSC_C0.vhd":17:7:17:12|Synthesizing work.osc_c0.rtl.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd":8:7:8:25|Synthesizing work.osc_c0_osc_c0_0_osc.def_arch.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\SgCore\OSC\2.0.101\osc_comps.vhd":19:7:19:20|Synthesizing work.rcosc_25_50mhz.def_arch.
Post processing for work.rcosc_25_50mhz.def_arch
Running optimization stage 1 on RCOSC_25_50MHZ .......
Post processing for work.osc_c0_osc_c0_0_osc.def_arch
Running optimization stage 1 on OSC_C0_OSC_C0_0_OSC .......
@W: CL240 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd":16:10:16:19|Signal XTLOSC_O2F is floating; a simulation mismatch is possible.
@W: CL240 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd":15:10:15:19|Signal XTLOSC_CCC is floating; a simulation mismatch is possible.
@W: CL240 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd":14:10:14:23|Signal RCOSC_1MHZ_O2F is floating; a simulation mismatch is possible.
@W: CL240 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd":13:10:13:23|Signal RCOSC_1MHZ_CCC is floating; a simulation mismatch is possible.
@W: CL240 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd":12:10:12:27|Signal RCOSC_25_50MHZ_O2F is floating; a simulation mismatch is possible.
Post processing for work.osc_c0.rtl
Running optimization stage 1 on OSC_C0 .......
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":24:7:24:22|Synthesizing work.nokia5110_driver.architecture_nokia5110_driver.
@N: CD233 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":93:27:93:28|Using sequential encoding for type lcd_state_machine.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":161:11:161:26|Signal mem_addr_updated is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":177:11:177:27|Signal usram2_a_addr_sig is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":180:11:180:27|Signal usram2_b_addr_sig is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":183:11:183:26|Signal usram2_c_blk_sig is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":184:11:184:27|Signal usram2_c_addr_sig is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":185:11:185:26|Signal usram2_c_din_sig is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\timer.vhd":6:7:6:11|Synthesizing work.timer.architecture_timer.
Post processing for work.timer.architecture_timer
Running optimization stage 1 on timer .......
@A: CL282 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\timer.vhd":26:8:26:9|Feedback mux created for signal timer_clock_out_sig. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\timer.vhd":6:7:6:11|Synthesizing work.timer.architecture_timer.
Post processing for work.timer.architecture_timer
Running optimization stage 1 on timer .......
@A: CL282 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\timer.vhd":26:8:26:9|Feedback mux created for signal timer_clock_out_sig. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
Post processing for work.nokia5110_driver.architecture_nokia5110_driver
Running optimization stage 1 on Nokia5110_Driver .......
@N: CL134 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":156:11:156:14|Found RAM mem2, depth=504, width=8
@N: CL134 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":156:11:156:14|Found RAM mem2, depth=504, width=8
@N: CL134 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":155:11:155:13|Found RAM mem, depth=504, width=8
@N: CL134 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":155:11:155:13|Found RAM mem, depth=504, width=8
@A: CL282 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":410:8:410:9|Feedback mux created for signal LCD_reg_mem_data[7:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W: CL177 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":166:78:166:78|Sharing sequential element uSRAM_C_ADDR_sig. Add a syn_preserve attribute to the element to prevent sharing.
@A: CL282 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":500:8:500:9|Feedback mux created for signal SPICLK_last_sig. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A: CL282 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":136:42:136:44|Feedback mux created for signal timer_indicator_last_sig. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W: CL190 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":430:8:430:9|Optimizing register bit LCD_reg_mem_X(7) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":446:8:446:9|Optimizing register bit LCD_reg_mem_Y(3) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":446:8:446:9|Optimizing register bit LCD_reg_mem_Y(4) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":446:8:446:9|Optimizing register bit LCD_reg_mem_Y(5) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":446:8:446:9|Optimizing register bit LCD_reg_mem_Y(6) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":446:8:446:9|Optimizing register bit LCD_reg_mem_Y(7) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":430:8:430:9|Pruning register bit 7 of LCD_reg_mem_X(7 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":446:8:446:9|Pruning register bits 7 to 3 of LCD_reg_mem_Y(7 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\FCCC_C0\FCCC_C0.vhd":17:7:17:13|Synthesizing work.fccc_c0.rtl.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\FCCC_C0\FCCC_C0_0\FCCC_C0_FCCC_C0_0_FCCC.vhd":8:7:8:28|Synthesizing work.fccc_c0_fccc_c0_0_fccc.def_arch.
@N: CD630 :"C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\lib\generic\smartfusion2.vhd":798:10:798:12|Synthesizing smartfusion2.ccc.syn_black_box.
Post processing for smartfusion2.ccc.syn_black_box
Running optimization stage 1 on CCC .......
@N: CD630 :"C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\lib\generic\smartfusion2.vhd":562:10:562:15|Synthesizing smartfusion2.clkint.syn_black_box.
Post processing for smartfusion2.clkint.syn_black_box
Running optimization stage 1 on CLKINT .......
@N: CD630 :"C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\lib\generic\smartfusion2.vhd":576:10:576:12|Synthesizing smartfusion2.gnd.syn_black_box.
Post processing for smartfusion2.gnd.syn_black_box
Running optimization stage 1 on GND .......
@N: CD630 :"C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\lib\generic\smartfusion2.vhd":582:10:582:12|Synthesizing smartfusion2.vcc.syn_black_box.
Post processing for smartfusion2.vcc.syn_black_box
Running optimization stage 1 on VCC .......
Post processing for work.fccc_c0_fccc_c0_0_fccc.def_arch
Running optimization stage 1 on FCCC_C0_FCCC_C0_0_FCCC .......
Post processing for work.fccc_c0.rtl
Running optimization stage 1 on FCCC_C0 .......
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Delta_Sigma_Converter.vhd":24:7:24:27|Synthesizing work.delta_sigma_converter.architecture_delta_sigma_converter.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Delta_Sigma_Converter.vhd":65:11:65:23|Signal internal_data is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Delta_Sigma_Converter.vhd":66:11:66:21|Signal avg_out_sig is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Delta_Sigma_Converter.vhd":67:11:67:22|Signal data_out_sig is undriven. Either assign the signal a value or remove the signal declaration.
Post processing for work.delta_sigma_converter.architecture_delta_sigma_converter
Running optimization stage 1 on Delta_Sigma_Converter .......
@W: CL169 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Delta_Sigma_Converter.vhd":158:8:158:9|Pruning unused register CLK_OSample_last_2. Make sure that there are no unused intermediate registers.
@A: CL282 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Delta_Sigma_Converter.vhd":228:2:228:3|Feedback mux created for signal pixels_ready. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\CoreAPB3_C0\CoreAPB3_C0.vhd":20:7:20:17|Synthesizing work.coreapb3_c0.rtl.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":34:7:34:14|Synthesizing coreapb3_lib.coreapb3.coreapb3_arch.
@N: CD604 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":665:16:665:29|OTHERS clause is not synthesized.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":1438:29:1438:38|Signal infill_upr in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":616:7:616:15|Signal ia_prdata is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3_muxptob3.vhd":33:7:33:23|Synthesizing coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch.
Post processing for coreapb3_lib.coreapb3_muxptob3.coreapb3_muxptob3_arch
Running optimization stage 1 on COREAPB3_MUXPTOB3 .......
Post processing for coreapb3_lib.coreapb3.coreapb3_arch
Running optimization stage 1 on CoreAPB3 .......
Post processing for work.coreapb3_c0.rtl
Running optimization stage 1 on CoreAPB3_C0 .......
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0.vhd":20:7:20:16|Synthesizing work.coreabc_c0.rtl.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":58:7:58:37|Synthesizing coreabc_lib.coreabc_c0_coreabc_c0_0_coreabc.rtl.
@N: CD233 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":223:13:223:14|Using sequential encoding for type ticycle.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":613:8:613:18|Signal accumulator in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":613:20:613:27|Signal accum_in in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@N: CD604 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":665:4:665:18|OTHERS clause is not synthesized.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":631:66:631:72|Signal product in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":776:8:776:14|Signal use_acm in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":776:28:776:34|Signal acmdata in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":795:8:795:11|Signal mux1 in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":795:18:795:28|Signal accumulator in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":795:30:795:39|Signal instr_data in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":822:8:822:19|Signal dataout_zreg in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@N: CD604 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":1001:27:1001:40|OTHERS clause is not synthesized.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":1073:19:1073:28|Signal instr_scmd in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD434 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":1073:30:1073:38|Signal zregister in the sensitivity list is not used in the process. Make sure all variables in the sensitivity list are referenced in the process.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":173:7:173:21|Signal dataout_zreg_zr is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":215:7:215:12|Signal debug1 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":216:7:216:12|Signal debug2 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":217:7:217:21|Signal debugblk_resetn is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\instructions.vhd":31:7:31:42|Synthesizing coreabc_lib.coreabc_c0_coreabc_c0_0_instructions.rtl.
Post processing for coreabc_lib.coreabc_c0_coreabc_c0_0_instructions.rtl
Running optimization stage 1 on COREABC_C0_COREABC_C0_0_INSTRUCTIONS .......
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":33:7:33:39|Synthesizing coreabc_lib.coreabc_c0_coreabc_c0_0_ramblocks.rtl.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":52:7:52:9|Signal wdx is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":53:7:53:9|Signal rdx is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":54:7:54:9|Signal wdy is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":55:7:55:9|Signal rdy is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":63:7:63:14|Signal wen_r0c1 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":64:7:64:14|Signal wen_r0c2 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":65:7:65:14|Signal wen_r0c3 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":67:7:67:14|Signal wen_r1c1 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":68:7:68:14|Signal wen_r1c2 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":69:7:69:14|Signal wen_r1c3 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":72:7:72:13|Signal rd_r0c1 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":73:7:73:13|Signal rd_r0c2 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":74:7:74:13|Signal rd_r0c3 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":76:7:76:13|Signal rd_r1c1 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":77:7:77:13|Signal rd_r1c2 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ramblocks.vhd":78:7:78:13|Signal rd_r1c3 is undriven. Either assign the signal a value or remove the signal declaration.
@N: CD630 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\ram128x8_smartfusion2.vhd":23:7:23:38|Synthesizing coreabc_lib.coreabc_c0_coreabc_c0_0_ram128x8.rtl.
@N: CD630 :"C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\lib\generic\smartfusion2.vhd":629:10:629:17|Synthesizing smartfusion2.ram64x18.syn_black_box.
Post processing for smartfusion2.ram64x18.syn_black_box
Running optimization stage 1 on RAM64x18 .......
Post processing for coreabc_lib.coreabc_c0_coreabc_c0_0_ram128x8.rtl
Running optimization stage 1 on COREABC_C0_COREABC_C0_0_RAM128X8 .......
Post processing for coreabc_lib.coreabc_c0_coreabc_c0_0_ramblocks.rtl
Running optimization stage 1 on COREABC_C0_COREABC_C0_0_RAMBLOCKS .......
Post processing for coreabc_lib.coreabc_c0_coreabc_c0_0_coreabc.rtl
Running optimization stage 1 on COREABC_C0_COREABC_C0_0_COREABC .......
@W: CL252 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":174:7:174:13|Bit 0 of signal PRODUCT is floating -- simulation mismatch possible.
@W: CL252 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":174:7:174:13|Bit 1 of signal PRODUCT is floating -- simulation mismatch possible.
@W: CL252 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":174:7:174:13|Bit 2 of signal PRODUCT is floating -- simulation mismatch possible.
@W: CL252 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":174:7:174:13|Bit 3 of signal PRODUCT is floating -- simulation mismatch possible.
@W: CL252 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":174:7:174:13|Bit 4 of signal PRODUCT is floating -- simulation mismatch possible.
@W: CL252 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":174:7:174:13|Bit 5 of signal PRODUCT is floating -- simulation mismatch possible.
@W: CL252 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":174:7:174:13|Bit 6 of signal PRODUCT is floating -- simulation mismatch possible.
@W: CL252 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":174:7:174:13|Bit 7 of signal PRODUCT is floating -- simulation mismatch possible.
@W: CL169 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":869:2:869:3|Pruning unused register GETINST_6. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":869:2:869:3|Pruning unused register ZREGISTER_3(0). Make sure that there are no unused intermediate registers.
@W: CL111 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":869:2:869:3|All reachable assignments to STKPTR(4) are '1'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":869:2:869:3|All reachable assignments to STKPTR(5) are '1'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":869:2:869:3|All reachable assignments to STKPTR(6) are '1'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":869:2:869:3|All reachable assignments to STKPTR(7) are '1'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL260 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":430:2:430:3|Pruning register bit 1 of INSTR_SLOT(1 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Post processing for work.coreabc_c0.rtl
Running optimization stage 1 on COREABC_C0 .......
@N: CD630 :"C:\Microsemi\Libero_SoC_v12.1\SynplifyPro\lib\generic\smartfusion2.vhd":191:10:191:13|Synthesizing smartfusion2.and2.syn_black_box.
Post processing for smartfusion2.and2.syn_black_box
Running optimization stage 1 on AND2 .......
Post processing for work.delta_sigma_design.rtl
Running optimization stage 1 on Delta_Sigma_Design .......
Running optimization stage 2 on AND2 .......
Running optimization stage 2 on RAM64x18 .......
Running optimization stage 2 on COREABC_C0_COREABC_C0_0_RAM128X8 .......
Running optimization stage 2 on COREABC_C0_COREABC_C0_0_RAMBLOCKS .......
Running optimization stage 2 on COREABC_C0_COREABC_C0_0_INSTRUCTIONS .......
Running optimization stage 2 on COREABC_C0_COREABC_C0_0_COREABC .......
@N: CL201 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":869:2:869:3|Trying to extract state machine for register ICYCLE.
Extracted state machine for register ICYCLE
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":109:9:109:17|Input PSLVERR_M is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":120:9:120:18|Input INITDATVAL is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":121:9:121:16|Input INITDONE is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":122:9:122:16|Input INITADDR is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":123:9:123:16|Input INITDATA is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":126:9:126:14|Input PSEL_S is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":127:9:127:17|Input PENABLE_S is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":128:9:128:16|Input PWRITE_S is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":129:9:129:15|Input PADDR_S is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\COREABC_C0\COREABC_C0_0\rtl\vhdl\core\coreabc.vhd":130:9:130:16|Input PWDATA_S is unused.
Running optimization stage 2 on COREABC_C0 .......
Running optimization stage 2 on COREAPB3_MUXPTOB3 .......
Running optimization stage 2 on CoreAPB3 .......
@W: CL246 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":78:0:78:4|Input port bits 31 to 12 of paddr(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":75:0:75:4|Input IADDR is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":76:0:76:6|Input PRESETN is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":77:0:77:3|Input PCLK is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":109:0:109:7|Input PRDATAS2 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":110:0:110:7|Input PRDATAS3 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":111:0:111:7|Input PRDATAS4 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":112:0:112:7|Input PRDATAS5 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":113:0:113:7|Input PRDATAS6 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":114:0:114:7|Input PRDATAS7 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":115:0:115:7|Input PRDATAS8 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":116:0:116:7|Input PRDATAS9 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":117:0:117:8|Input PRDATAS10 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":118:0:118:8|Input PRDATAS11 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":119:0:119:8|Input PRDATAS12 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":120:0:120:8|Input PRDATAS13 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":121:0:121:8|Input PRDATAS14 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":122:0:122:8|Input PRDATAS15 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":126:0:126:7|Input PREADYS2 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":127:0:127:7|Input PREADYS3 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":128:0:128:7|Input PREADYS4 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":129:0:129:7|Input PREADYS5 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":130:0:130:7|Input PREADYS6 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":131:0:131:7|Input PREADYS7 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":132:0:132:7|Input PREADYS8 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":133:0:133:7|Input PREADYS9 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":134:0:134:8|Input PREADYS10 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":135:0:135:8|Input PREADYS11 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":136:0:136:8|Input PREADYS12 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":137:0:137:8|Input PREADYS13 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":138:0:138:8|Input PREADYS14 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":139:0:139:8|Input PREADYS15 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":143:0:143:8|Input PSLVERRS2 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":144:0:144:8|Input PSLVERRS3 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":145:0:145:8|Input PSLVERRS4 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":146:0:146:8|Input PSLVERRS5 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":147:0:147:8|Input PSLVERRS6 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":148:0:148:8|Input PSLVERRS7 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":149:0:149:8|Input PSLVERRS8 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":150:0:150:8|Input PSLVERRS9 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":151:0:151:9|Input PSLVERRS10 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":152:0:152:9|Input PSLVERRS11 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":153:0:153:9|Input PSLVERRS12 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":154:0:154:9|Input PSLVERRS13 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":155:0:155:9|Input PSLVERRS14 is unused.
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vhdl\core\coreapb3.vhd":156:0:156:9|Input PSLVERRS15 is unused.
Running optimization stage 2 on CoreAPB3_C0 .......
Running optimization stage 2 on Delta_Sigma_Converter .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on CLKINT .......
Running optimization stage 2 on CCC .......
Running optimization stage 2 on FCCC_C0_FCCC_C0_0_FCCC .......
Running optimization stage 2 on FCCC_C0 .......
Running optimization stage 2 on timerZ1 .......
Running optimization stage 2 on timerZ0 .......
Running optimization stage 2 on Nokia5110_Driver .......
@W: CL190 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":500:8:500:9|Optimizing register bit init_step(3) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":500:8:500:9|Pruning register bit 3 of init_step(3 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CL201 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\hdl\Nokia5110_Driver.vhd":500:8:500:9|Trying to extract state machine for register LCD_State.
Extracted state machine for register LCD_State
State machine has 2 reachable states with original encodings of:
   00
   10
Running optimization stage 2 on RCOSC_25_50MHZ .......
Running optimization stage 2 on OSC_C0_OSC_C0_0_OSC .......
@N: CL159 :"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\component\work\OSC_C0\OSC_C0_0\OSC_C0_OSC_C0_0_OSC.vhd":10:10:10:12|Input XTL is unused.
Running optimization stage 2 on OSC_C0 .......
Running optimization stage 2 on SYSRESET .......
Running optimization stage 2 on INBUF_DIFF .......
Running optimization stage 2 on Delta_Sigma_Design .......

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
@L: C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\synthesis\synwork\layer0.rt.csv


At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Nov 25 01:08:17 2019

###########################################################]

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03M-SP1-1
Install: C:\Microsemi\Libero_SoC_v12.1\SynplifyPro
OS: Windows 6.2

Hostname: PHOENIX136DESKY

Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 223R, Built Oct 23 2018 09:18:38

@N|Running in 64-bit mode

Linker output is up to date. No re-linking necessary


At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Nov 25 01:08:17 2019

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Nov 25 01:08:17 2019

###########################################################]

@A: multi_srs_gen output is up to date. No run necessary.
To force a re-synthesis, select [Resynthesize All] in menu [Run].
Click link to view previous log file.
Multi-srs Generator Report
@R:"C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\synthesis\Delta_Sigma_Design_cck.srr"
Premap Report

# Mon Nov 25 01:08:17 2019


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03M-SP1-1
Install: C:\Microsemi\Libero_SoC_v12.1\SynplifyPro
OS: Windows 6.2

Hostname: PHOENIX136DESKY

Implementation : synthesis
Synopsys Generic Technology Pre-mapping, Version mapact, Build 2461R, Built Nov 29 2018 09:35:20


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

Reading constraint file: C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\constraint\Synplify_attr.fdc
@N: MF284 |Setting synthesis effort to medium for the design
@L: C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\synthesis\Delta_Sigma_Design_scck.rpt 
Printing clock  summary report in "C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\synthesis\Delta_Sigma_Design_scck.rpt" file 
@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 105MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 107MB)

@N: MF284 |Setting synthesis effort to medium for the design
@W: BN132 :"c:\users\phoenix136\dropbox\fpga\microsemi\delta_sigma_converter\component\work\coreabc_c0\coreabc_c0_0\rtl\vhdl\core\coreabc.vhd":430:2:430:3|Removing sequential instance COREABC_C0_0.COREABC_C0_0.INSTR_SLOT[0] because it is equivalent to instance COREABC_C0_0.COREABC_C0_0.INSTR_MUXC. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: BN362 :"c:\users\phoenix136\dropbox\fpga\microsemi\delta_sigma_converter\hdl\timer.vhd":26:8:26:9|Removing sequential instance timer_indic_sig (in view: work.timerZ1(architecture_timer)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"c:\users\phoenix136\dropbox\fpga\microsemi\delta_sigma_converter\component\work\coreabc_c0\coreabc_c0_0\rtl\vhdl\core\coreabc.vhd":869:2:869:3|Removing sequential instance IO_OUT[0] (in view: coreabc_lib.COREABC_C0_COREABC_C0_0_COREABC(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
syn_allowed_resources : blockrams=21  set on top level netlist Delta_Sigma_Design

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB)



Clock Summary
******************

          Start                                             Requested     Requested     Clock        Clock                   Clock
Level     Clock                                             Frequency     Period        Type         Group                   Load 
----------------------------------------------------------------------------------------------------------------------------------
0 -       System                                            100.0 MHz     10.000        system       system_clkgroup         0    
                                                                                                                                  
0 -       FCCC_C0_FCCC_C0_0_FCCC|GL0_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_0     263  
                                                                                                                                  
0 -       FCCC_C0_FCCC_C0_0_FCCC|GL1_net_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2     103  
                                                                                                                                  
0 -       timerZ1|timer_clock_out_sig_inferred_clock        100.0 MHz     10.000        inferred     Inferred_clkgroup_1     34   
==================================================================================================================================



Clock Load Summary
***********************

                                                  Clock     Source                                                          Clock Pin                                          Non-clock Pin                               Non-clock Pin                               
Clock                                             Load      Pin                                                             Seq Example                                        Seq Example                                 Comb Example                                
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                            0         -                                                               -                                                  -                                           -                                           
                                                                                                                                                                                                                                                                       
FCCC_C0_FCCC_C0_0_FCCC|GL0_net_inferred_clock     263       FCCC_C0_0.FCCC_C0_0.CCC_INST.GL0(CCC)                           Nokia5110_Driver_0.timer_indicator_last_sig.C      -                                           FCCC_C0_0.FCCC_C0_0.GL0_INST.I(BUFG)        
                                                                                                                                                                                                                                                                       
FCCC_C0_FCCC_C0_0_FCCC|GL1_net_inferred_clock     103       FCCC_C0_0.FCCC_C0_0.CCC_INST.GL1(CCC)                           Delta_Sigma_Converter_0.analog_FF.C                -                                           FCCC_C0_0.FCCC_C0_0.GL1_INST.I(BUFG)        
                                                                                                                                                                                                                                                                       
timerZ1|timer_clock_out_sig_inferred_clock        34        Nokia5110_Driver_0.SPI_timer.timer_clock_out_sig.Q[0](dffe)     Nokia5110_Driver_0.LCD_timer.timer_indic_sig.C     Nokia5110_Driver_0.SPICLK_last_sig.D[0]     Nokia5110_Driver_0.un1_CLK_SPI_sig.I[0](inv)
=======================================================================================================================================================================================================================================================================

@W: MT530 :"c:\users\phoenix136\dropbox\fpga\microsemi\delta_sigma_converter\component\work\coreabc_c0\coreabc_c0_0\rtl\vhdl\core\ram128x8_smartfusion2.vhd":103:4:103:13|Found inferred clock FCCC_C0_FCCC_C0_0_FCCC|GL0_net_inferred_clock which controls 263 sequential elements including COREABC_C0_0.COREABC_C0_0.URAM\.UR.UG4\.UR8\.ram_r0c0.U_RAM64x18. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"c:\users\phoenix136\dropbox\fpga\microsemi\delta_sigma_converter\hdl\timer.vhd":26:8:26:9|Found inferred clock timerZ1|timer_clock_out_sig_inferred_clock which controls 34 sequential elements including Nokia5110_Driver_0.LCD_timer.counter[20:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"c:\users\phoenix136\dropbox\fpga\microsemi\delta_sigma_converter\hdl\delta_sigma_converter.vhd":78:45:78:47|Found inferred clock FCCC_C0_FCCC_C0_0_FCCC|GL1_net_inferred_clock which controls 103 sequential elements including Delta_Sigma_Converter_0.pwm_quantized_value[11:0]. This clock has no specified timing constraint which may adversely impact design performance. 

@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@W: BN105 :"c:/users/phoenix136/dropbox/fpga/microsemi/delta_sigma_converter/constraint/synplify_attr.fdc":1:0:1:0|Cannot apply constraint syn_radhardlevel to dataout[3:0]
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\synthesis\Delta_Sigma_Design.sap.

Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB)

Encoding state machine ICYCLE[0:3] (in view: coreabc_lib.COREABC_C0_COREABC_C0_0_COREABC(rtl))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N: MO225 :"c:\users\phoenix136\dropbox\fpga\microsemi\delta_sigma_converter\component\work\coreabc_c0\coreabc_c0_0\rtl\vhdl\core\coreabc.vhd":869:2:869:3|There are no possible illegal states for state machine ICYCLE[0:3] (in view: coreabc_lib.COREABC_C0_COREABC_C0_0_COREABC(rtl)); safe FSM implementation is not required.
Encoding state machine LCD_State[0:1] (in view: work.Nokia5110_Driver(architecture_nokia5110_driver))
original code -> new code
   00 -> 0
   10 -> 1
@N: MO225 :"c:\users\phoenix136\dropbox\fpga\microsemi\delta_sigma_converter\hdl\nokia5110_driver.vhd":500:8:500:9|There are no possible illegal states for state machine LCD_State[0:1] (in view: work.Nokia5110_Driver(architecture_nokia5110_driver)); safe FSM implementation is not required.

Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB)

None
None
@W: MF511 |Found issues with constraints. Please check constraint checker report "C:\Users\Phoenix136\Dropbox\FPGA\Microsemi\Delta_Sigma_Converter\synthesis\Delta_Sigma_Design_cck.rpt" .

Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 138MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 138MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Nov 25 01:08:18 2019

###########################################################]
