~ Copyright (c) 2019-2024 Griefer@Work
~
~ This software is provided 'as-is', without any express or implied
~ warranty. In no event will the authors be held liable for any damages
~ arising from the use of this software.
~
~ Permission is granted to anyone to use this software for any purpose,
~ including commercial applications, and to alter it and redistribute it
~ freely, subject to the following restrictions:
~
~ 1. The origin of this software must not be misrepresented; you must not
~    claim that you wrote the original software. If you use this software
~    in a product, an acknowledgement (see the following) in the product
~    documentation is required:
~    Portions Copyright (c) 2019-2024 Griefer@Work
~ 2. Altered source versions must be plainly marked as such, and must not be
~    misrepresented as being the original software.
~ 3. This notice may not be removed or altered from any source distribution.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~ ARM INSTRUCTION DATABASE                                           ~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~



~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~ From: "DDI0406B_arm_architecture_reference_manual.pdf"
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~ Format:
~ >>         ENCODING : PATTERN : MNEMONIC OPERANDS ~ [ARM-VERSIONS]
~ >> FLAGS : ENCODING : PATTERN : MNEMONIC OPERANDS ~ [ARM-VERSIONS]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~ Define FLAGS:
~   - IT0        Only if outside of If-Then block
~   - IT1        Only if inside of If-Then block
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~ Each bit of PATTERN is represented by 2 characters:
~   - _0         Fixed, 0-bit
~   - _1         Fixed, 1-bit
~   - ?0         SBZ (Should-Be-Zero)
~   - Ra         Register bit for "Ra"
~   - Rd         Register bit for "Rd"
~   - Rm         Register bit for "Rm"
~   - ?m         Copy of Rm
~   - Rn         Register bit for "Rn"
~   - Rs         Register bit for "Rs"
~   - Rl         Register bit for "RdLo"
~   - Rh         Register bit for "RdHi"
~   - Ii         Immediate operand bit
~   - I+         Immediate operand bit (printed operand is +1 encoded bit-value)
~   - Cc         Condition code bit
~   - Lr         Register list bit
~      - Ll      Register list: LR
~      - Lp      Register list: PC
~   - Xs         Option bit: "S"et flags (in mnemonic: append "S")
~   - Xw         Option bit: "W"rite-back (in mnemonic: append "{!}")
~   - Xu         Option bit: add (in mnemonic: "+/-")
~   - Xr         Rotation operator (in mnemonic: "<rotation>")
~   - Ty         Type bit for shift-type (in mnemonic: "<type>")
~                   - TyTy = 0b00 --> LSL
~                   - TyTy = 0b01 --> LSR
~                   - TyTy = 0b10 --> ASR
~                   - TyTy = 0b11 --> ROR
~   - St         Shift-type bit
~   - J{1,2,3}   Extension bit for immediate operand
~   - Lb         Operand bit for "lsbit" (in mnemonic: "<lsb>")
~   - Mb         Operand bit for "msbit" (in mnemonic: "<width>", calculated as "msbit = <lsb>+<width>-1")
~   - Wi         Operand bit for "width" (in mnemonic: "<width>", calculated as "width = <width>-1")
~
~   - O1         Operand bit for "opc1"
~   - O2         Operand bit for "opc2"
~   - Cd         Operand bit for "CRd"
~   - Cm         Operand bit for "CRm"
~   - Cn         Operand bit for "CRn"
~   - Cp         Operand bit for "coproc"
~   - Tc         If-Then condition
~   - Tm         If-Then mask
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~




~~~~~~~~~~~~ T16 instructions
IT0 : T1 : _0_1_0_0_0_0_0_1_0_1RmRmRmRdRdRd : ADCS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_0_1_0_1RmRmRmRdRdRd : ADC<c> <Rd>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_0_1RdRdRdIiIiIiIiIiIiIiIi : ADD<c> <Rd>,SP,#<imm00>                           ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
~     T1 : _0_1_0_0_0_1_0_0Rd_1_1_0_1RdRdRd : ADD<c> <Rd>,SP,<Rd>                               ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T2 : _0_1_0_0_0_1_0_0RdRmRmRmRmRdRdRd : ADD<c> <Rd>,<Rm>                                  ~ [ARMv6T2, ARMv7 if <Rd> and <Rm> are both from R0-R7]
~     T2 : _0_1_0_0_0_1_0_0_1RmRmRmRm_1_0_1 : ADD<c> SP,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_0_1_1_0_0_0_0_0IiIiIiIiIiIiIi : ADD<c> SP,SP,#<imm00>                             ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_0_0_1_1_1_0IiIiIiRnRnRnRdRdRd : ADDS <Rd>,<Rn>,#<imm>                             ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_0_0_1_1_1_0IiIiIiRnRnRnRdRdRd : ADD<c> <Rd>,<Rn>,#<imm>                           ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_0_0_1_1_0_0RmRmRmRnRnRnRdRdRd : ADDS <Rd>,<Rn>,<Rm>                               ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_0_0_1_1_0_0RmRmRmRnRnRnRdRdRd : ADD<c> <Rd>,<Rn>,<Rm>                             ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T2 : _0_0_1_1_0RdRdRdIiIiIiIiIiIiIiIi : ADDS <Rd>,#<imm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T2 : _0_0_1_1_0RdRdRdIiIiIiIiIiIiIiIi : ADD<c> <Rd>,#<imm>                                ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_0_0RdRdRdIiIiIiIiIiIiIiIi : ADR<c> <Rd>,<imm00_rel>                           ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_0_0_0_0RmRmRmRdRdRd : ANDS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_0_0_0_0RmRmRmRdRdRd : AND<c> <Rd>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_0_1_0_0RmRmRmRdRdRd : ASRS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_0_1_0_0RmRmRmRdRdRd : ASR<c> <Rd>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_0_0_1_0IiIiIiIiIiRmRmRmRdRdRd : ASRS <Rd>,<Rm>,#<dis10_imm>                       ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_0_1_1_1_1_1IiIiIiIiIiIiIiIi : SVC<c> #<imm>                                     ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_0_1CcCcCcCcIiIiIiIiIiIiIiIi : B<c> <Simm0_rel>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_0IiIiIiIiIiIiIiIiIiIiIi : B<c> <Simm0_rel>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_1_1_1_0RmRmRmRdRdRd : BICS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_1_1_1_0RmRmRmRdRdRd : BIC<c> <Rd>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_1_1_1_1_0IiIiIiIiIiIiIiIi : BKPT #<imm>                                       ~ [ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_0_0_1_1_1_1RmRmRmRm_0_0_0 : BLX<c> <Rm>                                       ~ [ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_0_0_1_1_1_0RmRmRmRm_0_0_0 : BX<c> <Rm>                                        ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_1_0_0Ii_1IiIiIiIiIiRnRnRn : CBZ <Rn>,<imm0_rel>                               ~ [ARMv6T2, ARMv7]
      T1 : _1_0_1_1_1_0Ii_1IiIiIiIiIiRnRnRn : CBNZ <Rn>,<imm0_rel>                              ~ [ARMv6T2, ARMv7]
      T1 : _0_1_0_0_0_0_1_0_1_1RmRmRmRnRnRn : CMN<c> <Rn>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_0_1_0_1RnRnRnIiIiIiIiIiIiIiIi : CMP<c> <Rn>,#<imm>                                ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_0_0_0_1_0_1_0RmRmRmRnRnRn : CMP<c> <Rn>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T2 : _0_1_0_0_0_1_0_1RnRmRmRmRmRnRnRn : CMP<c> <Rn>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_0_0_0_1RmRmRmRdRdRd : EORS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_0_0_0_1RmRmRmRdRdRd : EOR<c> <Rd>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_1_1_1_1_1TcTcTcTcTmTmTmTm : IT{TODO_x}{TODO_y}{TODO_z} <firstcond>            ~ [ARMv6T2, ARMv7]
      T1 : _1_1_0_0_1RnRnRnLrLrLrLrLrLrLrLr : LDM<c> <Rn>!,<registers>                          ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7 (not in ThumbEE)]
      T1 : _0_1_1_0_1IiIiIiIiIiRnRnRnRtRtRt : LDR<c> <Rt>,[<Rn>,#<imm>]                         ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_0_1RtRtRtIiIiIiIiIiIiIiIi : LDR<c> <Rt>,<imm00_rel>                           ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_1_1_0_0RmRmRmRnRnRnRtRtRt : LDR<c> <Rt>,[<Rn>,<Rm>]                           ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_0_0_1_1RtRtRtIiIiIiIiIiIiIiIi : LDR<c> <Rt>,[SP,#<imm>]                           ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_1_1_1_0RmRmRmRnRnRnRtRtRt : LDRB<c> <Rt>,[<Rn>,<Rm>]                          ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_1_1_1IiIiIiIiIiRnRnRnRtRtRt : LDRB<c> <Rt>,[<Rn>,#<imm>]                        ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_1_1_0_1RmRmRmRnRnRnRtRtRt : LDRH<c> <Rt>,[<Rn>,<Rm>]                          ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_0_0_1IiIiIiIiIiRnRnRnRtRtRt : LDRH<c> <Rt>,[<Rn>,#<imm>]                        ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_1_0_1_1RmRmRmRnRnRnRtRtRt : LDRSB<c> <Rt>,[<Rn>,<Rm>]                         ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_1_1_1_1RmRmRmRnRnRnRtRtRt : LDRSH<c> <Rt>,[<Rn>,<Rm>]                         ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_0_0_1_0RmRmRmRdRdRd : LSLS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_0_0_1_0RmRmRmRdRdRd : LSL<c> <Rd>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_0_0_0_0IiIiIiIiIiRmRmRmRdRdRd : LSLS <Rd>,<Rm>,#<imm>                             ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_0_0_0_0IiIiIiIiIiRmRmRmRdRdRd : LSL <Rd>,<Rm>,#<imm>                              ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_0_0_1_1RmRmRmRdRdRd : LSRS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_0_0_1_1RmRmRmRdRdRd : LSR<c> <Rd>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_0_0_0_1IiIiIiIiIiRmRmRmRdRdRd : LSRS <Rd>,<Rm>,#<imm>                             ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_0_0_0_1IiIiIiIiIiRmRmRmRdRdRd : LSR<c> <Rd>,<Rm>,#<imm>                           ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_0_0_1_1_0RdRmRmRmRmRdRdRd : MOV<c> <Rd>,<Rm>                                  ~ [ARMv6*, ARMv7 if <Rd> and <Rm> both from R0-R7]
IT0 : T2 : _0_0_0_0_0_0_0_0_0_0RmRmRmRdRdRd : MOVS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_0_1_0_0RdRdRdIiIiIiIiIiIiIiIi : MOVS <Rd>,#<imm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_0_1_0_0RdRdRdIiIiIiIiIiIiIiIi : MOV<c> <Rd>,#<imm>                                ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_1_1_0_1RnRnRnRdRdRd : MULS <Rd>,<Rn>,<Rd>                               ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_1_1_0_1RnRnRnRdRdRd : MUL<c> <Rd>,<Rn>,<Rd>                             ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_1_1_1_1RmRmRmRdRdRd : MVNS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_1_1_1_1RmRmRmRdRdRd : MVN<c> <Rd>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_1_1_1_1_1_0_0_0_0_0_0_0_0 : NOP<c>                                            ~ [ARMv6T2, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_1_1_0_0RmRmRmRdRdRd : ORRS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_1_1_0_0RmRmRmRdRdRd : ORR<c> <Rd>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_1_1_1_0LpLrLrLrLrLrLrLrLr : POP<c> <registers>                                ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_1_0_1_0LlLrLrLrLrLrLrLrLr : PUSH<c> <registers>                               ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_1_1_0_1_0_0_1RmRmRmRdRdRd : REV16<c> <Rd>,<Rm>                                ~ [ARMv6*, ARMv7]
      T1 : _1_0_1_1_1_0_1_0_0_0RmRmRmRdRdRd : REV<c> <Rd>,<Rm>                                  ~ [ARMv6*, ARMv7]
      T1 : _1_0_1_1_1_0_1_0_1_1RmRmRmRdRdRd : REVSH<c> <Rd>,<Rm>                                ~ [ARMv6*, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_0_1_1_1RmRmRmRdRdRd : RORS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_0_1_1_1RmRmRmRdRdRd : ROR<c> <Rd>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_1_0_0_1RnRnRnRdRdRd : RSBS <Rd>,<Rn>,#0                                 ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_1_0_0_1RnRnRnRdRdRd : RSB<c> <Rd>,<Rn>,#0                               ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_1_0_0_0_0_0_1_1_0RmRmRmRdRdRd : SBCS <Rd>,<Rm>                                    ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_1_0_0_0_0_0_1_1_0RmRmRmRdRdRd : SBC<c> <Rd>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_1_0_1_1_0_0_1_0_1_0_0_0_0 : SETEND LE                                         ~ [ARMv6*, ARMv7]
      T1 : _1_0_1_1_0_1_1_0_0_1_0_1_1_0_0_0 : SETEND BE                                         ~ [ARMv6*, ARMv7]
      T1 : _1_0_1_1_1_1_1_1_0_1_0_0_0_0_0_0 : SEV<c>                                            ~ [ARMv7 (executes as NOP in ARMv6T2)]
      T1 : _1_1_0_0_0RnRnRnLrLrLrLrLrLrLrLr : STM<c> <Rn>!,<registers>                          ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7 (not in ThumbEE)]
      T1 : _0_1_1_0_0IiIiIiIiIiRnRnRnRtRtRt : STR<c> <Rt>,[<Rn>,#<imm>]                         ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_1_0_0_0RmRmRmRnRnRnRtRtRt : STR<c> <Rt>,[<Rn>,<Rm>]                           ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_0_0_1_0RtRtRtIiIiIiIiIiIiIiIi : STR<c> <Rt>,[SP,#<imm>]                           ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_1_1_0IiIiIiIiIiRnRnRnRtRtRt : STRB<c> <Rt>,[<Rn>,#<imm>]                        ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_1_0_1_0RmRmRmRnRnRnRtRtRt : STRB<c> <Rt>,[<Rn>,<Rm>]                          ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _0_1_0_1_0_0_1RmRmRmRnRnRnRtRtRt : STRH<c> <Rt>,[<Rn>,<Rm>]                          ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_0_0_0IiIiIiIiIiRnRnRnRtRtRt : STRH<c> <Rt>,[<Rn>,#<imm>]                        ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_1_0_0_0_0_1IiIiIiIiIiIiIi : SUB<c> SP,SP,#<imm>                               ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_0_0_1_1_1_1IiIiIiRnRnRnRdRdRd : SUBS <Rd>,<Rn>,#<imm>                             ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_0_0_1_1_1_1IiIiIiRnRnRnRdRdRd : SUB<c> <Rd>,<Rn>,#<imm>                           ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T1 : _0_0_0_1_1_0_1RmRmRmRnRnRnRdRdRd : SUBS <Rd>,<Rn>,<Rm>                               ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T1 : _0_0_0_1_1_0_1RmRmRmRnRnRnRdRdRd : SUB<c> <Rd>,<Rn>,<Rm>                             ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT0 : T2 : _0_0_1_1_1RdRdRdIiIiIiIiIiIiIiIi : SUBS <Rd>,#<imm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
IT1 : T2 : _0_0_1_1_1RdRdRdIiIiIiIiIiIiIiIi : SUB<c> <Rd>,#<imm>                                ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_1_0_0_1_0_0_1RmRmRmRdRdRd : SXTB<c> <Rd>,<Rm>                                 ~ [ARMv6*, ARMv7]
      T1 : _1_0_1_1_0_0_1_0_0_0RmRmRmRdRdRd : SXTH<c> <Rd>,<Rm>                                 ~ [ARMv6*, ARMv7]
      T1 : _0_1_0_0_0_0_1_0_0_0RmRmRmRnRnRn : TST<c> <Rn>,<Rm>                                  ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_0_1_1_0_0_1_0_1_1RmRmRmRdRdRd : UXTB<c> <Rd>,<Rm>                                 ~ [ARMv6*, ARMv7]
      T1 : _1_0_1_1_0_0_1_0_1_0RmRmRmRdRdRd : UXTH<c> <Rd>,<Rm>                                 ~ [ARMv6*, ARMv7]
      T1 : _1_0_1_1_1_1_1_1_0_0_1_0_0_0_0_0 : WFE<c>                                            ~ [ARMv7 (executes as NOP in ARMv6T2)]
      T1 : _1_0_1_1_1_1_1_1_0_0_1_1_0_0_0_0 : WFI<c>                                            ~ [ARMv7 (executes as NOP in ARMv6T2)]
      T1 : _1_0_1_1_1_1_1_1_0_0_0_1_0_0_0_0 : YIELD<c>                                          ~ [ARMv7 (executes as NOP in ARMv6T2)]

~~~~~~~~~~~~ A32 and T32 instructions
      A1 : CcCcCcCc_0_0_1_0_1_0_1XsRnRnRnRnRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : ADC{S}<c> <Rd>,<Rn>,#<ArmExpandImm(imm)>          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0Ii_0_1_0_1_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : ADC{S}<c> <Rd>,<Rn>,#<ThumbExpandImm(imm)>        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_0_1XsRnRnRnRnRdRdRdRdRsRsRsRs_0TyTy_1RmRmRmRm : ADC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_0_1XsRnRnRnRnRdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : ADC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_1_0_1_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : ADC{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}              ~ [ARMv6T2, ARMv7]
      T4 : _1_1_1_1_0Ii_1_0_0_0_0_0RnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : ADDW<c> <Rd>,<Rn>,#<imm>                          ~ [ARMv6T2, ARMv7]
~     T4 : _1_1_1_1_0Ii_1_0_0_0_0_0_1_1_0_1_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : ADDW<c> <Rd>,SP,#<imm>                            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_0_1_0_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : ADD{S}<c> <Rd>,<Rn>,#<ArmExpandImm(imm)>          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_0_0XsRnRnRnRnRdRdRdRdRsRsRsRs_0TyTy_1RmRmRmRm : ADD{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_0_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : ADD{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
~     A1 : CcCcCcCc_0_0_1_0_1_0_0Xs_1_1_0_1RdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : ADD{S}<c> <Rd>,SP,#<ArmExpandImm(imm)>            ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
~     A1 : CcCcCcCc_0_0_0_0_1_0_0Xs_1_1_0_1RdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : ADD{S}<c> <Rd>,SP,<Rm>{,<shift>}                  ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T3 : _1_1_1_1_0Ii_0_1_0_0_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : ADD{S}<c>.W <Rd>,<Rn>,#<ThumbExpandImm(imm)>      ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_0_1_0_1_1_0_0_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : ADD{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}              ~ [ARMv6T2, ARMv7]
~     T3 : _1_1_1_1_0Ii_0_1_0_0_0Xs_1_1_0_1_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : ADD{S}<c>.W <Rd>,SP,#<ThumbExpandImm(imm)>        ~ [ARMv6T2, ARMv7]
~     T3 : _1_1_1_0_1_0_1_1_0_0_0Xs_1_1_0_1_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : ADD{S}<c>.W <Rd>,SP,<Rm>{,<shift>}                ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_0_1_0_0_0_1_1_1_1RdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : ADR<c> <Rd>,+<ArmExpandImm_rel(imm)>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A2 : CcCcCcCc_0_0_1_0_0_1_0_0_1_1_1_1RdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : ADR<c> <Rd>,-<ArmExpandImm_rel(imm)>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T3 : _1_1_1_1_0Ii_1_0_0_0_0_0_1_1_1_1_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : ADR<c>.W <Rd>,+<imm>                              ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_0Ii_1_0_1_0_1_0_1_1_1_1_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : ADR<c>.W <Rd>,-<imm>                              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_0_0_0_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : AND{S}<c> <Rd>,<Rn>,#<ArmExpandImm_C(imm)>        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0Ii_0_0_0_0_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : AND{S}<c> <Rd>,<Rn>,#<ThumbExpandImm_C(imm)>      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_0_0XsRnRnRnRnRdRdRdRdRsRsRsRs_0TyTy_1RmRmRmRm : AND{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_0_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : AND{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_0_0_0_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : AND{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1Xs_0_0_0_0RdRdRdRdIiIiIiIiIi_1_0_0RmRmRmRm : ASR{S}<c> <Rd>,<Rm>,#<imm>                        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1Xs_0_0_0_0RdRdRdRdRmRmRmRm_0_1_0_1RnRnRnRn : ASR{S}<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_0_0_1_0Xs_1_1_1_1_0IiIiIiRdRdRdRdIiIi_1_0RmRmRmRm : ASR{S}<c>.W <Rd>,<Rm>,#<imm>                      ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_1_0_0_1_0XsRnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : ASR{S}<c>.W <Rd>,<Rn>,<Rm>                        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_1_0_1_0IiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIi : B<c> <Simm00_rel>                                 ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T3 : _1_1_1_1_0J3CcCcCcCcIiIiIiIiIiIi_1_0J1_0J2IiIiIiIiIiIiIiIiIiIiIi : B<c>.W <Simm0_sj2j1_rel>                          ~ [ARMv6T2, ARMv7]
      T4 : _1_1_1_1_0J3IiIiIiIiIiIiIiIiIiIi_1_0J1_1J2IiIiIiIiIiIiIiIiIiIiIi : B<c>.W <Simm0_sj2j1_rel>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_1_1_0MbMbMbMbMbRdRdRdRdLbLbLbLbLb_0_0_1_1_1_1_1 : BFC<c> <Rd>,#<lsb>,#<width>                       ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_0_1_1_0_1_1_1_1_0IiIiIiRdRdRdRdIiIi_0MbMbMbMbMb : BFC<c> <Rd>,#<lsb>,#<width>                       ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_1_1_0MbMbMbMbMbRdRdRdRdLbLbLbLbLb_0_0_1RnRnRnRn : BFI<c> <Rd>,<Rn>,#<lsb>,#<width>                  ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_0_1_1_0RnRnRnRn_0IiIiIiRdRdRdRdIiIi_0MbMbMbMbMb : BFI<c> <Rd>,<Rn>,#<lsb>,#<width>                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_1_1_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : BIC{S}<c> <Rd>,<Rn>,#<ArmExpandImm_C(imm)>        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0Ii_0_0_0_0_1XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : BIC{S}<c> <Rd>,<Rn>,#<ThumbExpandImm_C(imm)>      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_1_0XsRnRnRnRnRdRdRdRdRsRsRsRs_0TyTy_1RmRmRmRm : BIC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_1_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : BIC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_0_0_0_1XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : BIC{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0IiIiIiIiIiIiIiIiIiIiIiIi_0_1_1_1IiIiIiIi : BKPT #<imm>                                       ~ [ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_1_0_1_1IiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIi : BL<c> <Simm00_rel>                                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0XsIiIiIiIiIiIiIiIiIiIi_1_1j1_1j2IiIiIiIiIiIiIiIiIiIiIi : BL<c> <Simm0_sj2j1_rel>                           ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7 if J1 == J2 == 1]
      A2 : _1_1_1_1_1_0_1IiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIi : BLX <Simm0_h_rel>                                 ~ [ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0_1_1_1_1_1_1_1_1_1_1_1_1_0_0_1_1RmRmRmRm : BLX<c> <Rm>                                       ~ [ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_1_0XsIiIiIiIiIiIiIiIiIiIi_1_1j1_0j2IiIiIiIiIiIiIiIiIiIi_0 : BLX<c> <Simm00_sj2j1_rel>                         ~ [ARMv5T*, ARMv6*, ARMv7 if J1 == J2 == 1]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0_1_1_1_1_1_1_1_1_1_1_1_1_0_0_0_1RmRmRmRm : BX<c> <Rm>                                        ~ [ARMv4T, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0_1_1_1_1_1_1_1_1_1_1_1_1_0_0_1_0RmRmRmRm : BXJ<c> <Rm>                                       ~ [ARMv5TEJ, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_1_0_0RmRmRmRm_1_0_0_0_1_1_1_1_0_0_0_0_0_0_0_0 : BXJ<c> <Rm>                                       ~ [ARMv6T2, ARMv7]
 T2 / A2 : _1_1_1_1_1_1_1_0O1O1O1O1CnCnCnCnCdCdCdCdCpCpCpCpO2O2O2_0CmCmCmCm : CDP2<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>  ~ [ARMv6T2, ARMv7 for encoding T2]
 T1 / A1 : _1_1_1_0_1_1_1_0O1O1O1O1CnCnCnCnCdCdCdCdCpCpCpCpO2O2O2_0CmCmCmCm : CDP<c> <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>   ~ [ARMv6T2, ARMv7 for encoding T1]
      A1 : _1_1_1_1_0_1_0_1_0_1_1_1_1_1_1_1_1_1_1_1_0_0_0_0_0_0_0_1_1_1_1_1 : CLREX                                             ~ [ARMv6K, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_0_1_1_1_1_1_1_1_0_0_0_1_1_1_1_0_0_1_0_1_1_1_1 : CLREX<c>                                          ~ [ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_1_0_1_1_1_1RdRdRdRd_1_1_1_1_0_0_0_1RmRmRmRm : CLZ<c> <Rd>,<Rm>                                  ~ [ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_1_1?m?m?m?m_1_1_1_1RdRdRdRd_1_0_0_0RmRmRmRm : CLZ<c> <Rd>,<Rm>                                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_0_1_1_1RnRnRnRn_0_0_0_0IiIiIiIiIiIiIiIiIiIiIiIi : CMN<c> <Rn>,#<ArmExpandImm(imm)>                  ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0Ii_0_1_0_0_0_1RnRnRnRn_0IiIiIi_1_1_1_1IiIiIiIiIiIiIiIi : CMN<c> <Rn>,#<ThumbExpandImm(imm)>                ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_1_1RnRnRnRn_0_0_0_0RsRsRsRs_0TyTy_1RmRmRmRm : CMN<c> <Rn>,<Rm>,<type> <Rs>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_1_1RnRnRnRn_0_0_0_0IiIiIiIiIiStSt_0RmRmRmRm : CMN<c> <Rn>,<Rm>{,<shift>}                        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_1_0_0_0_1RnRnRnRn_0IiIiIi_1_1_1_1IiIiStStRmRmRmRm : CMN<c>.W <Rn>,<Rm>{,<shift>}                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_0_1_0_1RnRnRnRn_0_0_0_0IiIiIiIiIiIiIiIiIiIiIiIi : CMP<c> <Rn>,#<ArmExpandImm(imm)>                  ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_0_1RnRnRnRn_0_0_0_0RsRsRsRs_0TyTy_1RmRmRmRm : CMP<c> <Rn>,<Rm>,<type> <Rs>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_0_1RnRnRnRn_0_0_0_0IiIiIiIiIiStSt_0RmRmRmRm : CMP<c> <Rn>,<Rm>{,<shift>}                        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T3 : _1_1_1_0_1_0_1_1_1_0_1_1RnRnRnRn_0IiIiIi_1_1_1_1IiIiStStRmRmRmRm : CMP<c>.W <Rn>,<Rm> {,<shift>}                     ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_0Ii_0_1_1_0_1_1RnRnRnRn_0IiIiIi_1_1_1_1IiIiIiIiIiIiIiIi : CMP<c>.W <Rn>,#<ThumbExpandImm(imm)>              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_0_0_1_0_0_0_0_0_1_1_1_1_0_0_0_0_1_1_1_1IiIiIiIi : DBG<c> #<imm>                                     ~ [ARMv7 (executes as NOP in ARMv6Kand ARMv6T2)]
      T1 : _1_1_1_1_0_0_1_1_1_0_1_0_1_1_1_1_1_0_0_0_0_0_0_0_1_1_1_1IiIiIiIi : DBG<c> #<imm>                                     ~ [ARMv7 (executes as NOP in ARMv6T2)]
      A1 : _1_1_1_1_0_1_0_1_0_1_1_1_1_1_1_1_1_1_1_1_0_0_0_0_0_1_0_1IiIiIiIi : DMB #<mb_option>                                  ~ [ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_0_1_1_1_1_1_1_1_0_0_0_1_1_1_1_0_1_0_1IiIiIiIi : DMB<c> #<mb_option>                               ~ [ARMv7]
      A1 : _1_1_1_1_0_1_0_1_0_1_1_1_1_1_1_1_1_1_1_1_0_0_0_0_0_1_0_0IiIiIiIi : DSB #<mb_option>                                  ~ [ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_0_1_1_1_1_1_1_1_0_0_0_1_1_1_1_0_1_0_0IiIiIiIi : DSB<c> #<mb_option>                               ~ [ARMv7]
      A1 : CcCcCcCc_0_0_1_0_0_0_1XsRnRnRnRnRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : EOR{S}<c> <Rd>,<Rn>,#<ArmExpandImm_C(imm)>        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0Ii_0_0_1_0_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : EOR{S}<c> <Rd>,<Rn>,#<ThumbExpandImm_C(imm)>      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_0_1XsRnRnRnRnRdRdRdRdRsRsRsRs_0TyTy_1RmRmRmRm : EOR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_0_1XsRnRnRnRnRdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : EOR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_0_1_0_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : EOR{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}              ~ [ARMv6T2, ARMv7]
      A1 : _1_1_1_1_0_1_0_1_0_1_1_1_1_1_1_1_1_1_1_1_0_0_0_0_0_1_1_0IiIiIiIi : ISB #<mb_option>                                  ~ [ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_0_1_1_1_1_1_1_1_0_0_0_1_1_1_1_0_1_1_0IiIiIiIi : ISB<c> #<mb_option>                               ~ [ARMv7]
 T2 / A2 : _1_1_1_1_1_1_0XPXuXDXw_1_1_1_1_1CdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : LDC2{L}<c> <coproc>,<CRd>,<label>                 ~ [ARMv6T2, ARMv7 for encoding T2]
 T2 / A2 : _1_1_1_1_1_1_0XPXuXDXw_1RnRnRnRnCdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : LDC2{L}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}     ~ [ARMv6T2, ARMv7 for encoding T2]
 T1 / A1 : _1_1_1_0_1_1_0XPXuXDXw_1_1_1_1_1CdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : LDC{L}<c> <coproc>,<CRd>,<label>                  ~ [ARMv6T2, ARMv7 for encoding T1]
 T1 / A1 : _1_1_1_0_1_1_0XPXuXDXw_1RnRnRnRnCdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : LDC{L}<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}      ~ [ARMv6T2, ARMv7 for encoding T1]
      A1 : CcCcCcCc_1_0_0_0_1_0Xw_1RnRnRnRnLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : LDM<c> <Rn>{!},<registers>                        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_0_0_1_0Xw_1RnRnRnRnLpLl_0LrLrLrLrLrLrLrLrLrLrLrLrLr : LDM<c>.W <Rn>{!},<registers>                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_1_0_0_0_0_0Xw_1RnRnRnRnLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : LDMDA<c> <Rn>{!},<registers>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_1_0_0_1_0_0Xw_1RnRnRnRnLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : LDMDB<c> <Rn>{!},<registers>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_0_1_0_0_1_0_0Xw_1RnRnRnRnLpLl_0LrLrLrLrLrLrLrLrLrLrLrLrLr : LDMDB<c> <Rn>{!},<registers>                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_1_0_0_1_1_0Xw_1RnRnRnRnLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : LDMIB<c> <Rn>{!},<registers>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_0_1Xu_0_0_1_1_1_1_1RtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDR<c> <Rt>,<label>                               ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T4 : _1_1_1_1_1_0_0_0_0_1_0_1RnRnRnRnRtRtRtRt_1_1XuXwIiIiIiIiIiIiIiIi : LDR<c> <Rt>,[<Rn>,#+/-<imm>]{!}                   ~ [ARMv6T2, ARMv7]
      T4 : _1_1_1_1_1_0_0_0_0_1_0_1RnRnRnRnRtRtRtRt_1_0Xu_1IiIiIiIiIiIiIiIi : LDR<c> <Rt>,[<Rn>],#+/-<imm>                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1Xu_0Xw_1RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : LDR<c> <Rt>,[<Rn>,+/-<Rm>{,<shift>}]{!}           ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_0Xu_0_0_1RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : LDR<c> <Rt>,[<Rn>],+/-<Rm>{,<shift>}              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_0_1Xu_0Xw_1RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDR<c> <Rt>,[<Rn>,#+/-<imm>]{!}                   ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_0_0Xu_0_0_1RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDR<c> <Rt>,[<Rn>],#+/-<imm>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_0_0Xu_1_0_1_1_1_1_1RtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDR<c>.W <Rt>,<label>                             ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_0_0_0_1_0_1RnRnRnRnRtRtRtRt_0_0_0_0_0_0IiIiRmRmRmRm : LDR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]           ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_1_0_0_0_1_1_0_1RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDR<c>.W <Rt>,[<Rn>,#<imm>]                       ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_0_1Xu_1_0_1_1_1_1_1RtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRB<c> <Rt>,<label>                              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_0_0Xu_0_0_1_1_1_1_1RtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRB<c> <Rt>,<label>                              ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_1_0_0_0_0_0_0_1RnRnRnRnRtRtRtRt_1_1XuXwIiIiIiIiIiIiIiIi : LDRB<c> <Rt>,[<Rn>,#+/-<imm>]{!}                  ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_1_0_0_0_0_0_0_1RnRnRnRnRtRtRtRt_1_0Xu_1IiIiIiIiIiIiIiIi : LDRB<c> <Rt>,[<Rn>],#+/-<imm>                     ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1Xu_1Xw_1RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : LDRB<c> <Rt>,[<Rn>,+/-<Rm>{,<shift>}]{!}          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_0Xu_1_0_1RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : LDRB<c> <Rt>,[<Rn>],+/-<Rm>{,<shift>}             ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_0_1Xu_1Xw_1RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRB<c> <Rt>,[<Rn>,#+/-<imm>]{!}                  ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_0_0Xu_1_0_1RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRB<c> <Rt>,[<Rn>],#+/-<imm>                     ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_0_0_0_0_0_1RnRnRnRnRtRtRtRt_0_0_0_0_0_0IiIiRmRmRmRm : LDRB<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]          ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_0_0_1_0_0_1RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRB<c>.W <Rt>,[<Rn>,#<imm>]                      ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_0_0_0_0_0_1RnRnRnRnRtRtRtRt_1_1_1_0IiIiIiIiIiIiIiIi : LDRBT<c> <Rt>,[<Rn>,#<imm>]                       ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_0_0Xu_1_1_1RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRBT<c> <Rt>,[<Rn>],#+/-<imm>                    ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A2 : CcCcCcCc_0_1_1_0Xu_1_1_1RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : LDRBT<c> <Rt>,[<Rn>],+/-<Rm>{,<shift>}            ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_0Xw_0RnRnRnRnRtRtRtRt_0_0_0_0_1_1_0_1RmRmRmRm : LDRD<c> <Rt>,<RtP1>,[<Rn>,+/-<Rm>]{!}             ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_0_0_0RnRnRnRnRtRtRtRt_0_0_0_0_1_1_0_1RmRmRmRm : LDRD<c> <Rt>,<RtP1>,[<Rn>],+/-<Rm>                ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_1_0_0_1_1_1_1RtRtRtRtIiIiIiIi_1_1_0_1IiIiIiIi : LDRD<c> <Rt>,<RtP1>,<label>                       ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_1Xw_0RnRnRnRnRtRtRtRtIiIiIiIi_1_1_0_1IiIiIiIi : LDRD<c> <Rt>,<RtP1>,[<Rn>,#+/-<imm>]{!}           ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_1_0_0RnRnRnRnRtRtRtRtIiIiIiIi_1_1_0_1IiIiIiIi : LDRD<c> <Rt>,<RtP1>,[<Rn>],#+/-<imm>              ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_0_1_0_0_1Xu_1_0_1_1_1_1_1RtRtRtRtRTRTRTRTIiIiIiIiIiIiIiIi : LDRD<c> <Rt>,<Rt2>,<label>                        ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_0_1_0_0_1Xu_1Xw_1RnRnRnRnRtRtRtRtRTRTRTRTIiIiIiIiIiIiIiIi : LDRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm>]{!}            ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_0_1_0_0_0Xu_1_1_1RnRnRnRnRtRtRtRtRTRTRTRTIiIiIiIiIiIiIiIi : LDRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm>               ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_0_1RnRnRnRnRtRtRtRt_1_1_1_1_1_0_0_1_1_1_1_1 : LDREX<c> <Rt>,[<Rn>]                              ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_0_1_0_0_0_0_1_0_1RnRnRnRnRtRtRtRt_1_1_1_1IiIiIiIiIiIiIiIi : LDREX<c> <Rt>,[<Rn>,#<imm>]                       ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_1_0_1RnRnRnRnRtRtRtRt_1_1_1_1_1_0_0_1_1_1_1_1 : LDREXB<c> <Rt>,[<Rn>]                             ~ [ARMv6K, ARMv7]
      T1 : _1_1_1_0_1_0_0_0_1_1_0_1RnRnRnRnRtRtRtRt_1_1_1_1_0_1_0_0_1_1_1_1 : LDREXB<c> <Rt>,[<Rn>]                             ~ [ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1_1RnRnRnRnRtRtRtRt_1_1_1_1_1_0_0_1_1_1_1_1 : LDREXD<c> <Rt>,<RtP1>,[<Rn>]                      ~ [ARMv6K, ARMv7]
      T1 : _1_1_1_0_1_0_0_0_1_1_0_1RnRnRnRnRtRtRtRtRTRTRTRT_0_1_1_1_1_1_1_1 : LDREXD<c> <Rt>,<Rt2>,[<Rn>]                       ~ [ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_1_1_1RnRnRnRnRtRtRtRt_1_1_1_1_1_0_0_1_1_1_1_1 : LDREXH<c> <Rt>,[<Rn>]                             ~ [ARMv6K, ARMv7]
      T1 : _1_1_1_0_1_0_0_0_1_1_0_1RnRnRnRnRtRtRtRt_1_1_1_1_0_1_0_1_1_1_1_1 : LDREXH<c> <Rt>,[<Rn>]                             ~ [ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_1_0_1_1_1_1_1RtRtRtRtIiIiIiIi_1_0_1_1IiIiIiIi : LDRH<c> <Rt>,<label>                              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_0_0Xu_0_1_1_1_1_1_1RtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRH<c> <Rt>,<label>                              ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_1_0_0_0_0_0_1_1RnRnRnRnRtRtRtRt_1_1XuXwIiIiIiIiIiIiIiIi : LDRH<c> <Rt>,[<Rn>,#+/-<imm>]{!}                  ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_1_0_0_0_0_0_1_1RnRnRnRnRtRtRtRt_1_0Xu_1IiIiIiIiIiIiIiIi : LDRH<c> <Rt>,[<Rn>],#+/-<imm>                     ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_0Xw_1RnRnRnRnRtRtRtRt_0_0_0_0_1_0_1_1RmRmRmRm : LDRH<c> <Rt>,[<Rn>,+/-<Rm>]{!}                    ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_0_0_1RnRnRnRnRtRtRtRt_0_0_0_0_1_0_1_1RmRmRmRm : LDRH<c> <Rt>,[<Rn>],+/-<Rm>                       ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_1Xw_1RnRnRnRnRtRtRtRtIiIiIiIi_1_0_1_1IiIiIiIi : LDRH<c> <Rt>,[<Rn>,#+/-<imm>]{!}                  ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_1_0_1RnRnRnRnRtRtRtRtIiIiIiIi_1_0_1_1IiIiIiIi : LDRH<c> <Rt>,[<Rn>],#+/-<imm>                     ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_0_0_0_0_1_1RnRnRnRnRtRtRtRt_0_0_0_0_0_0IiIiRmRmRmRm : LDRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]          ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_0_0_1_0_1_1RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRH<c>.W <Rt>,[<Rn>,#<imm>]                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_1_1_1RnRnRnRnRtRtRtRtIiIiIiIi_1_0_1_1IiIiIiIi : LDRHT<c> <Rt>,[<Rn>],#+/-<imm>                    ~ [ARMv6T2, ARMv7]
      A2 : CcCcCcCc_0_0_0_0Xu_0_1_1RnRnRnRnRtRtRtRt_0_0_0_0_1_0_1_1RmRmRmRm : LDRHT<c> <Rt>,[<Rn>],+/-<Rm>                      ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_0_0_0_0_1_1RnRnRnRnRtRtRtRt_1_1_1_0IiIiIiIiIiIiIiIi : LDRHT<c> <Rt>,[<Rn>,#<imm>]                       ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_1_0_1_1_1_1_1RtRtRtRtIiIiIiIi_1_1_0_1IiIiIiIi : LDRSB<c> <Rt>,<label>                             ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_0_1Xu_0_0_1_1_1_1_1RtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRSB<c> <Rt>,<label>                             ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_0_1_0_0_0_1RnRnRnRnRtRtRtRt_1_1XuXwIiIiIiIiIiIiIiIi : LDRSB<c> <Rt>,[<Rn>,#+/-<imm>]{!}                 ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_0_1_0_0_0_1RnRnRnRnRtRtRtRt_1_0Xu_1IiIiIiIiIiIiIiIi : LDRSB<c> <Rt>,[<Rn>],#+/-<imm>                    ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_0_1_1_0_0_1RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRSB<c> <Rt>,[<Rn>,#<imm>]                       ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_0Xw_1RnRnRnRnRtRtRtRt_0_0_0_0_1_1_0_1RmRmRmRm : LDRSB<c> <Rt>,[<Rn>,+/-<Rm>]{!}                   ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_0_0_1RnRnRnRnRtRtRtRt_0_0_0_0_1_1_0_1RmRmRmRm : LDRSB<c> <Rt>,[<Rn>],+/-<Rm>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_1Xw_1RnRnRnRnRtRtRtRtIiIiIiIi_1_1_0_1IiIiIiIi : LDRSB<c> <Rt>,[<Rn>,#+/-<imm>]{!}                 ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_1_0_1RnRnRnRnRtRtRtRtIiIiIiIi_1_1_0_1IiIiIiIi : LDRSB<c> <Rt>,[<Rn>],#+/-<imm>                    ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_0_1_0_0_0_1RnRnRnRnRtRtRtRt_0_0_0_0_0_0IiIiRmRmRmRm : LDRSB<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]         ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_1_1_1RnRnRnRnRtRtRtRtIiIiIiIi_1_1_0_1IiIiIiIi : LDRSBT<c> <Rt>,[<Rn>],#+/-<imm>                   ~ [ARMv6T2, ARMv7]
      A2 : CcCcCcCc_0_0_0_0Xu_0_1_1RnRnRnRnRtRtRtRt_0_0_0_0_1_1_0_1RmRmRmRm : LDRSBT<c> <Rt>,[<Rn>],+/-<Rm>                     ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_0_1_0_0_0_1RnRnRnRnRtRtRtRt_1_1_1_0IiIiIiIiIiIiIiIi : LDRSBT<c> <Rt>,[<Rn>,#<imm>]                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_1_0_1_1_1_1_1RtRtRtRtIiIiIiIi_1_1_1_1IiIiIiIi : LDRSH<c> <Rt>,<label>                             ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_0_1Xu_0_1_1_1_1_1_1RtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRSH<c> <Rt>,<label>                             ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_0_1_0_0_1_1RnRnRnRnRtRtRtRt_1_1XuXwIiIiIiIiIiIiIiIi : LDRSH<c> <Rt>,[<Rn>,#+/-<imm>]{!}                 ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_0_1_0_0_1_1RnRnRnRnRtRtRtRt_1_0Xu_1IiIiIiIiIiIiIiIi : LDRSH<c> <Rt>,[<Rn>],#+/-<imm>                    ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_0_1_1_0_1_1RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRSH<c> <Rt>,[<Rn>,#<imm>]                       ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_0Xw_1RnRnRnRnRtRtRtRt_0_0_0_0_1_1_1_1RmRmRmRm : LDRSH<c> <Rt>,[<Rn>,+/-<Rm>]{!}                   ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_0_0_1RnRnRnRnRtRtRtRt_0_0_0_0_1_1_1_1RmRmRmRm : LDRSH<c> <Rt>,[<Rn>],+/-<Rm>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_1Xw_1RnRnRnRnRtRtRtRtIiIiIiIi_1_1_1_1IiIiIiIi : LDRSH<c> <Rt>,[<Rn>,#+/-<imm>]{!}                 ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_1_0_1RnRnRnRnRtRtRtRtIiIiIiIi_1_1_1_1IiIiIiIi : LDRSH<c> <Rt>,[<Rn>],#+/-<imm>                    ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_0_1_0_0_1_1RnRnRnRnRtRtRtRt_0_0_0_0_0_0IiIiRmRmRmRm : LDRSH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]         ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_1_1_1RnRnRnRnRtRtRtRtIiIiIiIi_1_1_1_1IiIiIiIi : LDRSHT<c> <Rt>,[<Rn>],#+/-<imm>                   ~ [ARMv6T2, ARMv7]
      A2 : CcCcCcCc_0_0_0_0Xu_0_1_1RnRnRnRnRtRtRtRt_0_0_0_0_1_1_1_1RmRmRmRm : LDRSHT<c> <Rt>,[<Rn>],+/-<Rm>                     ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_0_1_0_0_1_1RnRnRnRnRtRtRtRt_1_1_1_0IiIiIiIiIiIiIiIi : LDRSHT<c> <Rt>,[<Rn>,#<imm>]                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_0_0Xu_0_1_1RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : LDRT<c> <Rt>,[<Rn>],#+/-<imm>                     ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_0_0_0_1_0_1RnRnRnRnRtRtRtRt_1_1_1_0IiIiIiIiIiIiIiIi : LDRT<c> <Rt>,[<Rn>,#<imm>]                        ~ [ARMv6T2, ARMv7]
      A2 : CcCcCcCc_0_1_1_0Xu_0_1_1RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : LDRT<c> <Rt>,[<Rn>],+/-<Rm>{,<shift>}             ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1Xs_0_0_0_0RdRdRdRdIiIiIiIiIi_0_0_0RmRmRmRm : LSL{S}<c> <Rd>,<Rm>,#<imm>                        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1Xs_0_0_0_0RdRdRdRdRmRmRmRm_0_0_0_1RnRnRnRn : LSL{S}<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_0_0_1_0Xs_1_1_1_1_0IiIiIiRdRdRdRdIiIi_0_0RmRmRmRm : LSL{S}<c>.W <Rd>,<Rm>,#<imm>                      ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_1_0_0_0_0XsRnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : LSL{S}<c>.W <Rd>,<Rn>,<Rm>                        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1Xs_0_0_0_0RdRdRdRdIiIiIiIiIi_0_1_0RmRmRmRm : LSR{S}<c> <Rd>,<Rm>,#<imm>                        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1Xs_0_0_0_0RdRdRdRdRmRmRmRm_0_0_1_1RnRnRnRn : LSR{S}<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_0_0_1_0Xs_1_1_1_1_0IiIiIiRdRdRdRdIiIi_0_1RmRmRmRm : LSR{S}<c>.W <Rd>,<Rm>,#<imm>                      ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_1_0_0_0_1XsRnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : LSR{S}<c>.W <Rd>,<Rn>,<Rm>                        ~ [ARMv6T2, ARMv7]
 T2 / A2 : _1_1_1_1_1_1_1_0O1O1O1_0CnCnCnCnRtRtRtRtCpCpCpCpO2O2O2_1CmCmCmCm : MCR2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>} ~ [ARMv6T2, ARMv7 for encoding T2]
 T1 / A1 : _1_1_1_0_1_1_1_0O1O1O1_0CnCnCnCnRtRtRtRtCpCpCpCpO2O2O2_1CmCmCmCm : MCR<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}  ~ [ARMv6T2, ARMv7 for encoding T1]
 T2 / A2 : _1_1_1_1_1_1_0_0_0_1_0_0RTRTRTRTRtRtRtRtCpCpCpCpO1O1O1O1CmCmCmCm : MCRR2<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>         ~ [ARMv6T2, ARMv7 for encoding T2]
 T1 / A1 : _1_1_1_0_1_1_0_0_0_1_0_0RTRTRTRTRtRtRtRtCpCpCpCpO1O1O1O1CmCmCmCm : MCRR<c> <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>          ~ [ARMv6T2, ARMv7 for encoding T1]
      T1 : _1_1_1_1_1_0_1_1_0_0_0_0RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_0RmRmRmRm : MLA<c> <Rd>,<Rn>,<Rm>,<Ra>                        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_0_1XsRdRdRdRdRaRaRaRaRmRmRmRm_1_0_0_1RnRnRnRn : MLA{S}<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_1_1_0RdRdRdRdRaRaRaRaRmRmRmRm_1_0_0_1RnRnRnRn : MLS<c> <Rd>,<Rn>,<Rm>,<Ra>                        ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_0_0RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_1RmRmRmRm : MLS<c> <Rd>,<Rn>,<Rm>,<Ra>                        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_0_1_0_0IiIiIiIiRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : MOVT<c> <Rd>,#<imm>                               ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_0Ii_1_0_1_1_0_0IiIiIiIi_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : MOVT<c> <Rd>,#<imm>                               ~ [ARMv6T2, ARMv7]
      A2 : CcCcCcCc_0_0_1_1_0_0_0_0IiIiIiIiRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : MOVW<c> <Rd>,#<imm>                               ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_0Ii_1_0_0_1_0_0IiIiIiIi_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : MOVW<c> <Rd>,#<imm>                               ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_1_0_1Xs_0_0_0_0RdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : MOV{S}<c> <Rd>,#<ArmExpandImm_C(imm)>             ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1Xs_0_0_0_0RdRdRdRd_0_0_0_0_0_0_0_0RmRmRmRm : MOV{S}<c> <Rd>,<Rm>                               ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_1_0Ii_0_0_0_1_0Xs_1_1_1_1_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : MOV{S}<c>.W <Rd>,#<ThumbExpandImm_C(imm)>         ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_0_1_0_1_0_0_1_0Xs_1_1_1_1_0_0_0_0RdRdRdRd_0_0_0_0RmRmRmRm : MOV{S}<c>.W <Rd>,<Rm>                             ~ [ARMv6T2, ARMv7]
 T2 / A2 : _1_1_1_1_1_1_1_0O1O1O1_1CnCnCnCnRtRtRtRtCpCpCpCpO2O2O2_1CmCmCmCm : MRC2<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>} ~ [ARMv6T2, ARMv7 for encoding T2]
 T1 / A1 : _1_1_1_0_1_1_1_0O1O1O1_1CnCnCnCnRtRtRtRtCpCpCpCpO2O2O2_1CmCmCmCm : MRC<c> <coproc>,<opc1>,<Rt>,<CRn>,<CRm>{,<opc2>}  ~ [ARMv6T2, ARMv7 for encoding T1]
 T2 / A2 : _1_1_1_1_1_1_0_0_0_1_0_1RTRTRTRTRtRtRtRtCpCpCpCpO1O1O1O1CmCmCmCm : MRRC2<c> <coproc>,<opc>,<Rt>,<Rt2>,<CRm>          ~ [ARMv6T2, ARMv7 for encoding T2]
 T1 / A1 : _1_1_1_0_1_1_0_0_0_1_0_1RTRTRTRTRtRtRtRtCpCpCpCpO1O1O1O1CmCmCmCm : MRRC<c> <coproc>,<opc>,<Rt>,<Rt2>,<CRm>           ~ [ARMv6T2, ARMv7 for encoding T1]
      A1 : CcCcCcCc_0_0_0_1_0_0_0_0_1_1_1_1RdRdRdRd_0_0_0_0_0_0_0_0_0_0_0_0 : MRS<c> <Rd>,CPSR                                  ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_0_0_1_1_1_1RdRdRdRd_0_0_0_0_0_0_0_0_0_0_0_0 : MRS<c> <Rd>,SPSR                                  ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_1_1_0_1_1_1_1_1_0_0_0RdRdRdRd_0_0_0_0_0_0_0_0 : MRS<c> <Rd>,CPSR                                  ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_1_1_1_1_1_1_1_1_0_0_0RdRdRdRd_0_0_0_0_0_0_0_0 : MRS<c> <Rd>,SPSR                                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_0_0_1_0_1_0_0_0_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : MSR<c> CPSR_f,#<ArmExpandImm(imm)>                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_0_0_1_0_0_1_0_0_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : MSR<c> CPSR_s,#<ArmExpandImm(imm)>                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_0_0_1_0_1_1_0_0_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : MSR<c> CPSR_fs,#<ArmExpandImm(imm)>               ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0_1_0_0_0_1_1_1_1_0_0_0_0_0_0_0_0RnRnRnRn : MSR<c> CPSR_f,<Rn>                                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0_0_1_0_0_1_1_1_1_0_0_0_0_0_0_0_0RnRnRnRn : MSR<c> CPSR_s,<Rn>                                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0_1_1_0_0_1_1_1_1_0_0_0_0_0_0_0_0RnRnRnRn : MSR<c> CPSR_fs,<Rn>                               ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_0_0_0RnRnRnRn_1_0_0_0_1_0_0_0_0_0_0_0_0_0_0_0 : MSR<c> CPSR_f,<Rn>                                ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_0_0_0RnRnRnRn_1_0_0_0_0_1_0_0_0_0_0_0_0_0_0_0 : MSR<c> CPSR_s,<Rn>                                ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_0_0_0RnRnRnRn_1_0_0_0_1_1_0_0_0_0_0_0_0_0_0_0 : MSR<c> CPSR_fs,<Rn>                               ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_1_1_0_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : MUL<c> <Rd>,<Rn>,<Rm>                             ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_0_0XsRdRdRdRd_0_0_0_0RmRmRmRm_1_0_0_1RnRnRnRn : MUL{S}<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_1_1_1Xs_0_0_0_0RdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : MVN{S}<c> <Rd>,#<ArmExpandImm_C(imm)>             ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0Ii_0_0_0_1_1Xs_1_1_1_1_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : MVN{S}<c> <Rd>,#<ThumbExpandImm_C(imm)>           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_1_1Xs_0_0_0_0RdRdRdRdRsRsRsRs_0TyTy_1RmRmRmRm : MVN{S}<c> <Rd>,<Rm>,<type> <Rs>                   ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_1_1Xs_0_0_0_0RdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : MVN{S}<c> <Rd>,<Rm>{,<shift>}                     ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_0_0_1_1Xs_1_1_1_1_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : MVN{S}<c>.W <Rd>,<Rm>{,<shift>}                   ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_0_0_1_0_0_0_0_0_1_1_1_1_0_0_0_0_0_0_0_0_0_0_0_0 : NOP<c>                                            ~ [ARMv6K, ARMv6T2, ARMv7]
      T2 : _1_1_1_1_0_0_1_1_1_0_1_0_1_1_1_1_1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 : NOP<c>.W                                          ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_0Ii_0_0_0_1_1XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : ORN{S}<c> <Rd>,<Rn>,#<ThumbExpandImm_C(imm)>      ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_0_1_0_1_0_0_1_1XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : ORN{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_1_0_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : ORR{S}<c> <Rd>,<Rn>,#<ArmExpandImm_C(imm)>        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0Ii_0_0_0_1_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : ORR{S}<c> <Rd>,<Rn>,#<ThumbExpandImm_C(imm)>      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_0XsRnRnRnRnRdRdRdRdRsRsRsRs_0TyTy_1RmRmRmRm : ORR{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : ORR{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_0_0_1_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : ORR{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_0_0_0RnRnRnRnRdRdRdRdIiIiIiIiIi!t_0_1RmRmRmRm : PKHBT<c> <Rd>,<Rn>,<Rm>{,LSL #<imm>}              ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_0_1_0_1_0_1_1_0_0RnRnRnRn_0IiIiIiRdRdRdRdIiIi!t_0RmRmRmRm : PKHBT<c> <Rd>,<Rn>,<Rm>{,LSL #<imm>}              ~ [ARMv6T2, ARMv7]
      A1 : _1_1_1_1_0_1_0_1Xu_1_0_1_1_1_1_1_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : PLD +/-<label>                                    ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_0_0Xu_0_0_1_1_1_1_1_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : PLD<c> +/-<label>                                 ~ [ARMv6T2, ARMv7]
      A1 : _1_1_1_1_0_1_0_1Xu_0_0_1RnRnRnRn_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : PLD [<Rn>,#+/-<imm>]                              ~ [ARMv5TE*, ARMv6*, ARMv7 for PLD]
      T2 : _1_1_1_1_1_0_0_0_0_0_0_1RnRnRnRn_1_1_1_1_1_1_0_0IiIiIiIiIiIiIiIi : PLD<c> [<Rn>,#-<imm>]                             ~ [ARMv6T2, ARMv7 for PLD]
      T1 : _1_1_1_1_1_0_0_0_1_0_0_1RnRnRnRn_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : PLD<c> [<Rn>,#<imm>]                              ~ [ARMv6T2, ARMv7 for PLD]
      A1 : _1_1_1_1_0_1_1_1Xu_0_0_1RnRnRnRn_1_1_1_1IiIiIiIiIiStSt_0RmRmRmRm : PLD<c> [<Rn>,+/-<Rm>{,<shift>}]                   ~ [ARMv5TE*, ARMv6*, ARMv7 for PLD]
      T1 : _1_1_1_1_1_0_0_0_0_0_0_1RnRnRnRn_1_1_1_1_0_0_0_0_0_0IiIiRmRmRmRm : PLD<c> [<Rn>,<Rm>{,LSL #<imm2>}]                  ~ [ARMv6T2, ARMv7 for PLD]
      A1 : _1_1_1_1_0_1_0_1Xu_1_0_1RnRnRnRn_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : PLDW [<Rn>,#+/-<imm>]                             ~ [ARMv5TE*, ARMv6*, ARMv7 for PLD]
      T2 : _1_1_1_1_1_0_0_0_0_0_1_1RnRnRnRn_1_1_1_1_1_1_0_0IiIiIiIiIiIiIiIi : PLDW<c> [<Rn>,#-<imm>]                            ~ [ARMv6T2, ARMv7 for PLD]
      T1 : _1_1_1_1_1_0_0_0_1_0_1_1RnRnRnRn_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : PLDW<c> [<Rn>,#<imm>]                             ~ [ARMv6T2, ARMv7 for PLD]
      A1 : _1_1_1_1_0_1_1_1Xu_1_0_1RnRnRnRn_1_1_1_1IiIiIiIiIiStSt_0RmRmRmRm : PLDW<c> [<Rn>,+/-<Rm>{,<shift>}]                  ~ [ARMv5TE*, ARMv6*, ARMv7 for PLD]
      T1 : _1_1_1_1_1_0_0_0_0_0_1_1RnRnRnRn_1_1_1_1_0_0_0_0_0_0IiIiRmRmRmRm : PLDW<c> [<Rn>,<Rm>{,LSL #<imm2>}]                 ~ [ARMv6T2, ARMv7 for PLD]
      A1 : _1_1_1_1_0_1_0_0Xu_1_0_1RnRnRnRn_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : PLI [<Rn>,#+/-<imm>]                              ~ [ARMv7]
      A1 : _1_1_1_1_0_1_1_0Xu_1_0_1RnRnRnRn_1_1_1_1IiIiIiIiIiStSt_0RmRmRmRm : PLI [<Rn>,+/-<Rm>{,<shift>}]                      ~ [ARMv7]
      T3 : _1_1_1_1_1_0_0_1Xu_0_0_1_1_1_1_1_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : PLI<c> +/-<label>                                 ~ [ARMv7]
      T2 : _1_1_1_1_1_0_0_1_0_0_0_1RnRnRnRn_1_1_1_1_1_1_0_0IiIiIiIiIiIiIiIi : PLI<c> [<Rn>,#-<imm>]                             ~ [ARMv7]
      T1 : _1_1_1_1_1_0_0_1_1_0_0_1RnRnRnRn_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIi : PLI<c> [<Rn>,#<imm>]                              ~ [ARMv7]
      T1 : _1_1_1_1_1_0_0_1_0_0_0_1RnRnRnRn_1_1_1_1_0_0_0_0_0_0IiIiRmRmRmRm : PLI<c> [<Rn>,<Rm>{,LSL #<imm2>}]                  ~ [ARMv7]
      A2 : CcCcCcCc_0_1_0_0_1_0_0_1_1_1_0_1RtRtRtRt_0_0_0_0_0_0_0_0_0_1_0_0 : POP<c> {<Rt>}                                     ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_1_0_0_0_1_0_1_1_1_1_0_1LrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : POP<c> <registers>                                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_0_0_1_0_1_1_1_1_0_1LrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : POP<c>.W <registers>                              ~ [ARMv6T2, ARMv7]
~     T2 : _1_1_1_0_1_0_0_0_1_0_1_1_1_1_0_1LpLl_0LrLrLrLrLrLrLrLrLrLrLrLrLr : POP<c>.W <registers>                              ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_1_0_0_0_0_1_0_1_1_1_0_1RtRtRtRt_1_0_1_1_0_0_0_0_0_1_0_0 : POP<c>.W {<Rt>}                                   ~ [ARMv6T2, ARMv7]
      A2 : CcCcCcCc_0_1_0_1_0_0_1_0_1_1_0_1RtRtRtRt_0_0_0_0_0_0_0_0_0_1_0_0 : PUSH<c> {<Rt>}                                    ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_1_0_0_1_0_0_1_0_1_1_0_1LrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : PUSH<c> <registers>                               ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_0_0_1_0_1_0_1_1_0_1LrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : PUSH<c>.W <registers>                             ~ [ARMv6T2, ARMv7]
~     T2 : _1_1_1_0_1_0_0_0_1_0_1_0_1_1_0_1_0Ll_0LrLrLrLrLrLrLrLrLrLrLrLrLr : PUSH<c>.W <registers>                             ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_1_0_0_0_0_1_0_0_1_1_0_1RtRtRtRt_1_1_0_1_0_0_0_0_0_1_0_0 : PUSH<c>.W {<Rt>}                                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_0RnRnRnRnRdRdRdRd_1_1_1_1_0_0_0_1RmRmRmRm : QADD16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_1RmRmRmRm : QADD16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_0RnRnRnRnRdRdRdRd_1_1_1_1_1_0_0_1RmRmRmRm : QADD8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_1RmRmRmRm : QADD8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_0_0RnRnRnRnRdRdRdRd_0_0_0_0_0_1_0_1RmRmRmRm : QADD<c> <Rd>,<Rm>,<Rn>                            ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_1_0_0_0RmRmRmRm : QADD<c> <Rd>,<Rm>,<Rn>                            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_0RnRnRnRnRdRdRdRd_1_1_1_1_0_0_1_1RmRmRmRm : QASX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_1RmRmRmRm : QASX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_0_0RnRnRnRnRdRdRdRd_0_0_0_0_0_1_0_1RmRmRmRm : QDADD<c> <Rd>,<Rm>,<Rn>                           ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_1_0_0_1RmRmRmRm : QDADD<c> <Rd>,<Rm>,<Rn>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_1_0RnRnRnRnRdRdRdRd_0_0_0_0_0_1_0_1RmRmRmRm : QDSUB<c> <Rd>,<Rm>,<Rn>                           ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_1_0_1_1RmRmRmRm : QDSUB<c> <Rd>,<Rm>,<Rn>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_0RnRnRnRnRdRdRdRd_1_1_1_1_0_1_0_1RmRmRmRm : QSAX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_1RmRmRmRm : QSAX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_0RnRnRnRnRdRdRdRd_1_1_1_1_0_1_1_1RmRmRmRm : QSUB16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_1RmRmRmRm : QSUB16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_0RnRnRnRnRdRdRdRd_1_1_1_1_1_1_1_1RmRmRmRm : QSUB8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_1RmRmRmRm : QSUB8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0RnRnRnRnRdRdRdRd_0_0_0_0_0_1_0_1RmRmRmRm : QSUB<c> <Rd>,<Rm>,<Rn>                            ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_1_0_1_0RmRmRmRm : QSUB<c> <Rd>,<Rm>,<Rn>                            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_1_1_1_1_1_1_1RdRdRdRd_1_1_1_1_0_0_1_1RmRmRmRm : RBIT<c> <Rd>,<Rm>                                 ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_1?m?m?m?m_1_1_1_1RdRdRdRd_1_0_1_0RmRmRmRm : RBIT<c> <Rd>,<Rm>                                 ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_0_1_1_1_1_1_1RdRdRdRd_1_1_1_1_1_0_1_1RmRmRmRm : REV16<c> <Rd>,<Rm>                                ~ [ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_1_0_1_0_0_1?m?m?m?m_1_1_1_1RdRdRdRd_1_0_0_1RmRmRmRm : REV16<c>.W <Rd>,<Rm>                              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_0_1_1_1_1_1_1RdRdRdRd_1_1_1_1_0_0_1_1RmRmRmRm : REV<c> <Rd>,<Rm>                                  ~ [ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_1_0_1_0_0_1?m?m?m?m_1_1_1_1RdRdRdRd_1_0_0_0RmRmRmRm : REV<c>.W <Rd>,<Rm>                                ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_1_1_1_1_1_1_1RdRdRdRd_1_1_1_1_1_0_1_1RmRmRmRm : REVSH<c> <Rd>,<Rm>                                ~ [ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_1_0_1_0_0_1?m?m?m?m_1_1_1_1RdRdRdRd_1_0_1_1RmRmRmRm : REVSH<c>.W <Rd>,<Rm>                              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1Xs_0_0_0_0RdRdRdRdIiIiIiIiIi_1_1_0RmRmRmRm : ROR{S}<c> <Rd>,<Rm>,#<imm>                        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_0_1_0_1_0_0_1_0Xs_1_1_1_1_0IiIiIiRdRdRdRdIiIi_1_1RmRmRmRm : ROR{S}<c> <Rd>,<Rm>,#<imm>                        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1Xs_0_0_0_0RdRdRdRdRmRmRmRm_0_1_1_1RnRnRnRn : ROR{S}<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_1_0_0_1_1XsRnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : ROR{S}<c>.W <Rd>,<Rn>,<Rm>                        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1Xs_0_0_0_0RdRdRdRd_0_0_0_0_0_1_1_0RmRmRmRm : RRX{S}<c> <Rd>,<Rm>                               ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_0_1_0_1_0_0_1_0Xs_1_1_1_1_0_0_0_0RdRdRdRd_0_0_1_1RmRmRmRm : RRX{S}<c> <Rd>,<Rm>                               ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_0_0_1_1XsRnRnRnRnRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : RSB{S}<c> <Rd>,<Rn>,#<ArmExpandImm(imm)>          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_1_1XsRnRnRnRnRdRdRdRdRsRsRsRs_0TyTy_1RmRmRmRm : RSB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_1_1XsRnRnRnRnRdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : RSB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_0_1_0_1_1_1_1_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : RSB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_0Ii_0_1_1_1_0XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : RSB{S}<c>.W <Rd>,<Rn>,#<ThumbExpandImm(imm)>      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_0_1_1_1XsRnRnRnRnRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : RSC{S}<c> <Rd>,<Rn>,#<ArmExpandImm(imm)>          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_1_1XsRnRnRnRnRdRdRdRdRsRsRsRs_0TyTy_1RmRmRmRm : RSC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_1_1XsRnRnRnRnRdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : RSC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_0_1RnRnRnRnRdRdRdRd_1_1_1_1_0_0_0_1RmRmRmRm : SADD16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : SADD16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_0_1RnRnRnRnRdRdRdRd_1_1_1_1_1_0_0_1RmRmRmRm : SADD8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : SADD8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_0_1RnRnRnRnRdRdRdRd_1_1_1_1_0_0_1_1RmRmRmRm : SASX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : SASX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_0_1_1_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : SBC{S}<c> <Rd>,<Rn>,#<ArmExpandImm(imm)>          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0Ii_0_1_0_1_1XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : SBC{S}<c> <Rd>,<Rn>,#<ThumbExpandImm(imm)>        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_1_0XsRnRnRnRnRdRdRdRdRsRsRsRs_0TyTy_1RmRmRmRm : SBC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_1_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : SBC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_1_0_1_1XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : SBC{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_1_0_1WiWiWiWiWiRdRdRdRdLbLbLbLbLb_1_0_1RnRnRnRn : SBFX<c> <Rd>,<Rn>,#<lsb>,#<width>                 ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_0_1_0_0RnRnRnRn_0IiIiIiRdRdRdRdIiIi_0WiWiWiWiWi : SBFX<c> <Rd>,<Rn>,#<lsb>,#<width>                 ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_1_1_1_1RmRmRmRm : SDIV<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv7-R]
      A1 : CcCcCcCc_0_1_1_0_1_0_0_0RnRnRnRnRdRdRdRd_1_1_1_1_1_0_1_1RmRmRmRm : SEL<c> <Rd>,<Rn>,<Rm>                             ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_1_0RnRnRnRn_1_1_1_1RdRdRdRd_1_0_0_0RmRmRmRm : SEL<c> <Rd>,<Rn>,<Rm>                             ~ [ARMv6T2, ARMv7]
      A1 : _1_1_1_1_0_0_0_1_0_0_0_0_0_0_0_1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0 : SETEND LE                                         ~ [ARMv6*, ARMv7]
      A1 : _1_1_1_1_0_0_0_1_0_0_0_0_0_0_0_1_0_0_0_0_0_0_1_0_0_0_0_0_0_0_0_0 : SETEND BE                                         ~ [ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_0_0_1_0_0_0_0_0_1_1_1_1_0_0_0_0_0_0_0_0_0_1_0_0 : SEV<c>                                            ~ [ARMv6K, ARMv7 (executes as NOP in ARMv6T2)]
      T2 : _1_1_1_1_0_0_1_1_1_0_1_0_1_1_1_1_1_0_0_0_0_0_0_0_0_0_0_0_0_1_0_0 : SEV<c>.W                                          ~ [ARMv7 (executes as NOP in ARMv6T2)]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_1RnRnRnRnRdRdRdRd_1_1_1_1_0_0_0_1RmRmRmRm : SHADD16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_1_0RmRmRmRm : SHADD16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_1RnRnRnRnRdRdRdRd_1_1_1_1_1_0_0_1RmRmRmRm : SHADD8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_1_0RmRmRmRm : SHADD8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_1RnRnRnRnRdRdRdRd_1_1_1_1_0_0_1_1RmRmRmRm : SHASX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_1_0RmRmRmRm : SHASX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_1RnRnRnRnRdRdRdRd_1_1_1_1_0_1_0_1RmRmRmRm : SHSAX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_1_0RmRmRmRm : SHSAX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_1RnRnRnRnRdRdRdRd_1_1_1_1_0_1_1_1RmRmRmRm : SHSUB16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_1_0RmRmRmRm : SHSUB16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_1_1RnRnRnRnRdRdRdRd_1_1_1_1_1_1_1_1RmRmRmRm : SHSUB8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_1_0RmRmRmRm : SHSUB8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_0_0RdRdRdRdRaRaRaRaRmRmRmRm_1_1_1_0RnRnRnRn : SMLATT<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_0_0RdRdRdRdRaRaRaRaRmRmRmRm_1_1_0_0RnRnRnRn : SMLABT<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_0_0RdRdRdRdRaRaRaRaRmRmRmRm_1_0_1_0RnRnRnRn : SMLATB<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_0_0RdRdRdRdRaRaRaRaRmRmRmRm_1_0_0_0RnRnRnRn : SMLABB<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_0_1RnRnRnRnRaRaRaRaRdRdRdRd_0_0_1_1RmRmRmRm : SMLATT<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_0_1RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_1RmRmRmRm : SMLABT<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_0_1RnRnRnRnRaRaRaRaRdRdRdRd_0_0_1_0RmRmRmRm : SMLATB<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_0_1RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_0RmRmRmRm : SMLABB<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_0_0_0RdRdRdRdRaRaRaRaRmRmRmRm_0_0_1_1RnRnRnRn : SMLADX<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_0_0_0RdRdRdRdRaRaRaRaRmRmRmRm_0_0_0_1RnRnRnRn : SMLAD<c> <Rd>,<Rn>,<Rm>,<Ra>                      ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_1_0RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_1RmRmRmRm : SMLADX<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_1_0RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_0RmRmRmRm : SMLAD<c> <Rd>,<Rn>,<Rm>,<Ra>                      ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_1_0_0RnRnRnRnRlRlRlRlRhRhRhRh_0_0_0_0RmRmRmRm : SMLAL<c> <RdLo>,<RdHi>,<Rn>,<Rm>                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_0_0RhRhRhRhRlRlRlRlRmRmRmRm_1_1_1_0RnRnRnRn : SMLALTT<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_0_0RhRhRhRhRlRlRlRlRmRmRmRm_1_1_0_0RnRnRnRn : SMLALBT<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_0_0RhRhRhRhRlRlRlRlRmRmRmRm_1_0_1_0RnRnRnRn : SMLALTB<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_0_0RhRhRhRhRlRlRlRlRmRmRmRm_1_0_0_0RnRnRnRn : SMLALBB<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_1_0_0RnRnRnRnRlRlRlRlRhRhRhRh_1_0_1_1RmRmRmRm : SMLALTT<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_1_0_0RnRnRnRnRlRlRlRlRhRhRhRh_1_0_0_1RmRmRmRm : SMLALBT<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_1_0_0RnRnRnRnRlRlRlRlRhRhRhRh_1_0_1_0RmRmRmRm : SMLALTB<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_1_0_0RnRnRnRnRlRlRlRlRhRhRhRh_1_0_0_0RmRmRmRm : SMLALBB<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_1_0_0RhRhRhRhRlRlRlRlRmRmRmRm_0_0_1_1RnRnRnRn : SMLALDX<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_1_0_0RhRhRhRhRlRlRlRlRmRmRmRm_0_0_0_1RnRnRnRn : SMLALD<c> <RdLo>,<RdHi>,<Rn>,<Rm>                 ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_1_0_0RnRnRnRnRlRlRlRlRhRhRhRh_1_1_0_1RmRmRmRm : SMLALDX<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_1_0_0RnRnRnRnRlRlRlRlRhRhRhRh_1_1_0_0RmRmRmRm : SMLALD<c> <RdLo>,<RdHi>,<Rn>,<Rm>                 ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_1_1XsRhRhRhRhRlRlRlRlRmRmRmRm_1_0_0_1RnRnRnRn : SMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm>               ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0RdRdRdRdRaRaRaRaRmRmRmRm_1_1_0_0RnRnRnRn : SMLAWT<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0RdRdRdRdRaRaRaRaRmRmRmRm_1_0_0_0RnRnRnRn : SMLAWB<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_1_1RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_1RmRmRmRm : SMLAWT<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_1_1RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_0RmRmRmRm : SMLAWB<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_0_0_0RdRdRdRdRaRaRaRaRmRmRmRm_0_1_1_1RnRnRnRn : SMLSDT<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_0_0_0RdRdRdRdRaRaRaRaRmRmRmRm_0_1_0_1RnRnRnRn : SMLSDB<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_0_0RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_1RmRmRmRm : SMLSDT<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_0_0RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_0RmRmRmRm : SMLSDB<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_1_0_0RhRhRhRhRlRlRlRlRmRmRmRm_0_1_1_1RnRnRnRn : SMLSLDT<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_1_0_0RhRhRhRhRlRlRlRlRmRmRmRm_0_1_0_1RnRnRnRn : SMLSLDB<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_1_0_1RnRnRnRnRlRlRlRlRhRhRhRh_1_1_0_1RmRmRmRm : SMLSLDT<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_1_0_1RnRnRnRnRlRlRlRlRhRhRhRh_1_1_0_0RmRmRmRm : SMLSLDB<c> <RdLo>,<RdHi>,<Rn>,<Rm>                ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_1_0_1RdRdRdRdRaRaRaRaRmRmRmRm_0_0_1_1RnRnRnRn : SMMLAR<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_1_0_1RdRdRdRdRaRaRaRaRmRmRmRm_0_0_0_1RnRnRnRn : SMMLA<c> <Rd>,<Rn>,<Rm>,<Ra>                      ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_0_1RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_1RmRmRmRm : SMMLAR<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_0_1RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_0RmRmRmRm : SMMLA<c> <Rd>,<Rn>,<Rm>,<Ra>                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_1_0_1RdRdRdRdRaRaRaRaRmRmRmRm_1_1_1_1RnRnRnRn : SMMLSR<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_1_0_1RdRdRdRdRaRaRaRaRmRmRmRm_1_1_0_1RnRnRnRn : SMMLS<c> <Rd>,<Rn>,<Rm>,<Ra>                      ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_1_0RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_1RmRmRmRm : SMMLSR<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_1_0RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_0RmRmRmRm : SMMLS<c> <Rd>,<Rn>,<Rm>,<Ra>                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_1_0_1RdRdRdRd_1_1_1_1RmRmRmRm_0_0_1_1RnRnRnRn : SMMULR<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_1_0_1RdRdRdRd_1_1_1_1RmRmRmRm_0_0_0_1RnRnRnRn : SMMUL<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_1RmRmRmRm : SMMULR<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : SMMUL<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_0_0_0RdRdRdRd_1_1_1_1RmRmRmRm_0_0_1_1RnRnRnRn : SMUADX<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_0_0_0RdRdRdRd_1_1_1_1RmRmRmRm_0_0_0_1RnRnRnRn : SMUAD<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_1RmRmRmRm : SMUADX<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : SMUAD<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_1_0RdRdRdRd?0?0?0?0RmRmRmRm_1_1_1_0RnRnRnRn : SMULTT<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_1_0RdRdRdRd?0?0?0?0RmRmRmRm_1_1_0_0RnRnRnRn : SMULBT<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_1_0RdRdRdRd?0?0?0?0RmRmRmRm_1_0_1_0RnRnRnRn : SMULTB<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_1_1_0RdRdRdRd?0?0?0?0RmRmRmRm_1_0_0_0RnRnRnRn : SMULBB<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_1_1RmRmRmRm : SMULTT<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_1RmRmRmRm : SMULBT<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_1_0RmRmRmRm : SMULTB<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : SMULBB<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_0_0_0RnRnRnRnRlRlRlRlRhRhRhRh_0_0_0_0RmRmRmRm : SMULL<c> <RdLo>,<RdHi>,<Rn>,<Rm>                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_1_0XsRhRhRhRhRlRlRlRlRmRmRmRm_1_0_0_1RnRnRnRn : SMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm>               ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0RdRdRdRd?0?0?0?0RmRmRmRm_1_1_1_0RnRnRnRn : SMULWT<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_0RdRdRdRd?0?0?0?0RmRmRmRm_1_0_1_0RnRnRnRn : SMULWB<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_1_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_1RmRmRmRm : SMULWT<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_0_1_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : SMULWB<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_0_0_0RdRdRdRd_1_1_1_1RmRmRmRm_0_1_1_1RnRnRnRn : SMUSDX<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_0_0_0_0RdRdRdRd_1_1_1_1RmRmRmRm_0_1_0_1RnRnRnRn : SMUSD<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_1RmRmRmRm : SMUSDX<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : SMUSD<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_0_1_0I+I+I+I+RdRdRdRd_1_1_1_1_0_0_1_1RnRnRnRn : SSAT16<c> <Rd>,#<imm>,<Rn>                        ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_0_0_1_0RnRnRnRn_0_0_0_0RdRdRdRd_0_0_0_0I+I+I+I+ : SSAT16<c> <Rd>,#<imm>,<Rn>                        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_0_1I+I+I+I+I+RdRdRdRdIiIiIiIiIiSt_0_1RnRnRnRn : SSAT<c> <Rd>,#<imm>,<Rn>{,<shift>}                ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_0_0St_0RnRnRnRn_0IiIiIiRdRdRdRdIiIi_0I+I+I+I+I+ : SSAT<c> <Rd>,#<imm>,<Rn>{,<shift>}                ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_0_1RnRnRnRnRdRdRdRd_1_1_1_1_0_1_0_1RmRmRmRm : SSAX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : SSAX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_0_1RnRnRnRnRdRdRdRd_1_1_1_1_0_1_1_1RmRmRmRm : SSUB16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : SSUB16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_0_0_1RnRnRnRnRdRdRdRd_1_1_1_1_1_1_1_1RmRmRmRm : SSUB8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : SSUB8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
 T2 / A2 : _1_1_1_1_1_1_0_1Xu_0Xw_0RnRnRnRnCdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : STC2<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}        ~ [ARMv6T2, ARMv7 for encoding T2]
 T2 / A2 : _1_1_1_1_1_1_0_0Xu_0_1_0RnRnRnRnCdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : STC2<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>           ~ [ARMv6T2, ARMv7 for encoding T2]
 T2 / A2 : _1_1_1_1_1_1_0_1Xu_1Xw_0RnRnRnRnCdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : STC2L<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}       ~ [ARMv6T2, ARMv7 for encoding T2]
 T2 / A2 : _1_1_1_1_1_1_0_0Xu_1_1_0RnRnRnRnCdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : STC2L<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>          ~ [ARMv6T2, ARMv7 for encoding T2]
 T1 / A1 : _1_1_1_0_1_1_0_1Xu_0Xw_0RnRnRnRnCdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : STC<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}         ~ [ARMv6T2, ARMv7 for encoding T1]
 T1 / A1 : _1_1_1_0_1_1_0_0Xu_0_1_0RnRnRnRnCdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : STC<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>            ~ [ARMv6T2, ARMv7 for encoding T1]
 T1 / A1 : _1_1_1_0_1_1_0_1Xu_1Xw_0RnRnRnRnCdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : STCL<c> <coproc>,<CRd>,[<Rn>,#+/-<imm>]{!}        ~ [ARMv6T2, ARMv7 for encoding T1]
 T1 / A1 : _1_1_1_0_1_1_0_0Xu_1_1_0RnRnRnRnCdCdCdCdCpCpCpCpIiIiIiIiIiIiIiIi : STCL<c> <coproc>,<CRd>,[<Rn>],#+/-<imm>           ~ [ARMv6T2, ARMv7 for encoding T1]
      A1 : CcCcCcCc_1_0_0_0_1_0Xw_0RnRnRnRnLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : STM<c> <Rn>{!},<registers>                        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_0_0_1_0Xw_0RnRnRnRn_0XM_0LrLrLrLrLrLrLrLrLrLrLrLrLr : STM<c>.W <Rn>{!},<registers>                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_1_0_0_0_0_0Xw_0RnRnRnRnLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : STMDA<c> <Rn>{!},<registers>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_1_0_0_1_0_0Xw_0RnRnRnRnLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : STMDB<c> <Rn>{!},<registers>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_0_1_0_0_1_0_0Xw_0RnRnRnRn_0XM_0LrLrLrLrLrLrLrLrLrLrLrLrLr : STMDB<c> <Rn>{!},<registers>                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_1_0_0_1_1_0Xw_0RnRnRnRnLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLr : STMIB<c> <Rn>{!},<registers>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T4 : _1_1_1_1_1_0_0_0_0_1_0_0RnRnRnRnRtRtRtRt_1_1XuXwIiIiIiIiIiIiIiIi : STR<c> <Rt>,[<Rn>,#+/-<imm>]{!}                   ~ [ARMv6T2, ARMv7]
      T4 : _1_1_1_1_1_0_0_0_0_1_0_0RnRnRnRnRtRtRtRt_1_0Xu_1IiIiIiIiIiIiIiIi : STR<c> <Rt>,[<Rn>],#+/-<imm>                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1Xu_0Xw_0RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : STR<c> <Rt>,[<Rn>,+/-<Rm>{,<shift>}]{!}           ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_0Xu_0_0_0RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : STR<c> <Rt>,[<Rn>],+/-<Rm>{,<shift>}              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_0_1Xu_0Xw_0RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : STR<c> <Rt>,[<Rn>,#+/-<imm>]{!}                   ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_0_0Xu_0_0_0RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : STR<c> <Rt>,[<Rn>],#+/-<imm>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T3 : _1_1_1_1_1_0_0_0_1_1_0_0RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : STR<c>.W <Rt>,[<Rn>,#<imm>]                       ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_0_0_0_1_0_0RnRnRnRnRtRtRtRt_0_0_0_0_0_0IiIiRmRmRmRm : STR<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]           ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_1_0_0_0_0_0_0_0RnRnRnRnRtRtRtRt_1_1XuXwIiIiIiIiIiIiIiIi : STRB<c> <Rt>,[<Rn>,#+/-<imm>]{!}                  ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_1_0_0_0_0_0_0_0RnRnRnRnRtRtRtRt_1_0Xu_1IiIiIiIiIiIiIiIi : STRB<c> <Rt>,[<Rn>],#+/-<imm>                     ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1Xu_1Xw_0RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : STRB<c> <Rt>,[<Rn>,+/-<Rm>{,<shift>}]{!}          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_0Xu_1_0_0RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : STRB<c> <Rt>,[<Rn>],+/-<Rm>{,<shift>}             ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_0_1Xu_1Xw_0RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : STRB<c> <Rt>,[<Rn>,#+/-<imm>]{!}                  ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_0_0Xu_1_0_0RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : STRB<c> <Rt>,[<Rn>],#+/-<imm>                     ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_0_0_1_0_0_0RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : STRB<c>.W <Rt>,[<Rn>,#<imm>]                      ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_0_0_0_0_0_0RnRnRnRnRtRtRtRt_0_0_0_0_0_0IiIiRmRmRmRm : STRB<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]          ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_0_0_0_0_0_0RnRnRnRnRtRtRtRt_1_1_1_0IiIiIiIiIiIiIiIi : STRBT<c> <Rt>,[<Rn>,#<imm>]                       ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_0_0Xu_1_1_0RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : STRBT<c> <Rt>,[<Rn>],#+/-<imm>                    ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A2 : CcCcCcCc_0_1_1_0Xu_1_1_0RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : STRBT<c> <Rt>,[<Rn>],+/-<Rm>{,<shift>}            ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_0Xw_0RnRnRnRnRtRtRtRt_0_0_0_0_1_1_1_1RmRmRmRm : STRD<c> <Rt>,<RtP1>,[<Rn>,+/-<Rm>]{!}             ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_0_0_0RnRnRnRnRtRtRtRt_0_0_0_0_1_1_1_1RmRmRmRm : STRD<c> <Rt>,<RtP1>,[<Rn>],+/-<Rm>                ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_1Xw_0RnRnRnRnRtRtRtRtIiIiIiIi_1_1_1_1IiIiIiIi : STRD<c> <Rt>,<RtP1>,[<Rn>,#+/-<imm>]{!}           ~ [ARMv5TE*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_1_0_0RnRnRnRnRtRtRtRtIiIiIiIi_1_1_1_1IiIiIiIi : STRD<c> <Rt>,<RtP1>,[<Rn>],#+/-<imm>              ~ [ARMv5TE*, ARMv6*, ARMv7]
      T1 : _1_1_1_0_1_0_0_1Xu_1Xw_0RnRnRnRnRtRtRtRtRTRTRTRTIiIiIiIiIiIiIiIi : STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm>]{!}            ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_0_1_0_0_0Xu_1_1_0RnRnRnRnRtRtRtRtRTRTRTRTIiIiIiIiIiIiIiIi : STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm>               ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_0_0RnRnRnRnRdRdRdRd_1_1_1_1_1_0_0_1RtRtRtRt : STREX<c> <Rd>,<Rt>,[<Rn>]                         ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_0_1_0_0_0_0_1_0_0RnRnRnRnRtRtRtRtRdRdRdRdIiIiIiIiIiIiIiIi : STREX<c> <Rd>,<Rt>,[<Rn>,#<imm>]                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_1_0_0RnRnRnRnRdRdRdRd_1_1_1_1_1_0_0_1RtRtRtRt : STREXB<c> <Rd>,<Rt>,[<Rn>]                        ~ [ARMv6K, ARMv7]
      T1 : _1_1_1_0_1_0_0_0_1_1_0_0RnRnRnRnRtRtRtRt_1_1_1_1_0_1_0_0RdRdRdRd : STREXB<c> <Rd>,<Rt>,[<Rn>]                        ~ [ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_0_1_0RnRnRnRnRdRdRdRd_1_1_1_1_1_0_0_1RtRtRtRt : STREXD<c> <Rd>,<Rt>,<RtP1>,[<Rn>]                 ~ [ARMv6K, ARMv7]
      T1 : _1_1_1_0_1_0_0_0_1_1_0_0RnRnRnRnRtRtRtRtRTRTRTRT_0_1_1_1RdRdRdRd : STREXD<c> <Rd>,<Rt>,<Rt2>,[<Rn>]                  ~ [ARMv7]
      A1 : CcCcCcCc_0_0_0_1_1_1_1_0RnRnRnRnRdRdRdRd_1_1_1_1_1_0_0_1RtRtRtRt : STREXH<c> <Rd>,<Rt>,[<Rn>]                        ~ [ARMv6K, ARMv7]
      T1 : _1_1_1_0_1_0_0_0_1_1_0_0RnRnRnRnRtRtRtRt_1_1_1_1_0_1_0_1RdRdRdRd : STREXH<c> <Rd>,<Rt>,[<Rn>]                        ~ [ARMv7]
      T3 : _1_1_1_1_1_0_0_0_0_0_1_0RnRnRnRnRtRtRtRt_1_1XuXwIiIiIiIiIiIiIiIi : STRH<c> <Rt>,[<Rn>,#+/-<imm>]{!}                  ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_1_0_0_0_0_0_1_0RnRnRnRnRtRtRtRt_1_0Xu_1IiIiIiIiIiIiIiIi : STRH<c> <Rt>,[<Rn>],#+/-<imm>                     ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_0Xw_0RnRnRnRnRtRtRtRt_0_0_0_0_1_0_1_1RmRmRmRm : STRH<c> <Rt>,[<Rn>,+/-<Rm>]{!}                    ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_0_0_0RnRnRnRnRtRtRtRt_0_0_0_0_1_0_1_1RmRmRmRm : STRH<c> <Rt>,[<Rn>],+/-<Rm>                       ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1Xu_1Xw_0RnRnRnRnRtRtRtRtIiIiIiIi_1_0_1_1IiIiIiIi : STRH<c> <Rt>,[<Rn>,#+/-<imm>]{!}                  ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_1_0_0RnRnRnRnRtRtRtRtIiIiIiIi_1_0_1_1IiIiIiIi : STRH<c> <Rt>,[<Rn>],#+/-<imm>                     ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_0_0_0_0_1_0RnRnRnRnRtRtRtRt_0_0_0_0_0_0IiIiRmRmRmRm : STRH<c>.W <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]          ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_1_1_0_0_0_1_0_1_0RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : STRH<c>.W <Rt>,[<Rn>,#<imm>]                      ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0Xu_1_1_0RnRnRnRnRtRtRtRtIiIiIiIi_1_0_1_1IiIiIiIi : STRHT<c> <Rt>,[<Rn>],#+/-<imm>                    ~ [ARMv6T2, ARMv7]
      A2 : CcCcCcCc_0_0_0_0Xu_0_1_0RnRnRnRnRtRtRtRt_0_0_0_0_1_0_1_1RmRmRmRm : STRHT<c> <Rt>,[<Rn>],+/-<Rm>                      ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_0_0_0_0_1_0RnRnRnRnRtRtRtRt_1_1_1_0IiIiIiIiIiIiIiIi : STRHT<c> <Rt>,[<Rn>,#<imm>]                       ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_0_0Xu_0_1_0RnRnRnRnRtRtRtRtIiIiIiIiIiIiIiIiIiIiIiIi : STRT<c> <Rt>,[<Rn>]{,+/-<imm>}                    ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_0_0_0_1_0_0RnRnRnRnRtRtRtRt_1_1_1_0IiIiIiIiIiIiIiIi : STRT<c> <Rt>,[<Rn>,#<imm>]                        ~ [ARMv6T2, ARMv7]
      A2 : CcCcCcCc_0_1_1_0Xu_0_1_0RnRnRnRnRtRtRtRtIiIiIiIiIiStSt_0RmRmRmRm : STRT<c> <Rt>,[<Rn>],+/-<Rm>{,<shift>}             ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T4 : _1_1_1_1_0Ii_1_0_1_0_1_0RnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : SUBW<c> <Rd>,<Rn>,#<imm>                          ~ [ARMv6T2, ARMv7]
~     T3 : _1_1_1_1_0Ii_1_0_1_0_1_0_1_1_0_1_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : SUBW<c> <Rd>,SP,#<imm>                            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_0_0_1_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : SUB{S}<c> <Rd>,<Rn>,#<ArmExpandImm(imm)>          ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_1_0XsRnRnRnRnRdRdRdRdRsRsRsRs_0TyTy_1RmRmRmRm : SUB{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>              ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_1_0XsRnRnRnRnRdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : SUB{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
~     A1 : CcCcCcCc_0_0_1_0_0_1_0Xs_1_1_0_1RdRdRdRdIiIiIiIiIiIiIiIiIiIiIiIi : SUB{S}<c> <Rd>,SP,#<ArmExpandImm(imm)>            ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
~     A1 : CcCcCcCc_0_0_0_0_0_1_0Xs_1_1_0_1RdRdRdRdIiIiIiIiIiStSt_0RmRmRmRm : SUB{S}<c> <Rd>,SP,<Rm>{,<shift>}                  ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
~     T1 : _1_1_1_0_1_0_1_1_1_0_1Xs_1_1_0_1_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : SUB{S}<c> <Rd>,SP,<Rm>{,<shift>}                  ~ [ARMv6T2, ARMv7]
      T3 : _1_1_1_1_0Ii_0_1_1_0_1XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : SUB{S}<c>.W <Rd>,<Rn>,#<ThumbExpandImm(imm)>      ~ [ARMv6T2, ARMv7]
      T2 : _1_1_1_0_1_0_1_1_1_0_1XsRnRnRnRn_0IiIiIiRdRdRdRdIiIiStStRmRmRmRm : SUB{S}<c>.W <Rd>,<Rn>,<Rm>{,<shift>}              ~ [ARMv6T2, ARMv7]
~     T2 : _1_1_1_1_0Ii_0_1_1_0_1Xs_1_1_0_1_0IiIiIiRdRdRdRdIiIiIiIiIiIiIiIi : SUB{S}<c>.W <Rd>,SP,#<ThumbExpandImm(imm)>        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_1_1_1_1IiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIiIi : SVC<c> #<imm>                                     ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_0_0RnRnRnRnRtRtRtRt_0_0_0_0_1_0_0_1RTRTRTRT : SWP<c> <Rt>,<Rt2>,[<Rn>]                          ~ [ARMv4*, ARMv5T*, ARMv6* (deprecated), ARMv7 (deprecated)]
      A1 : CcCcCcCc_0_0_0_1_0_1_0_0RnRnRnRnRtRtRtRt_0_0_0_0_1_0_0_1RTRTRTRT : SWPB<c> <Rt>,<Rt2>,[<Rn>]                         ~ [ARMv4*, ARMv5T*, ARMv6* (deprecated), ARMv7 (deprecated)]
      A1 : CcCcCcCc_0_1_1_0_1_0_0_0RnRnRnRnRdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : SXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>}            ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_0_0_1_0RnRnRnRn_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : SXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>}            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_0_1_0RnRnRnRnRdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : SXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>}              ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_0_1_0_0RnRnRnRn_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : SXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>}              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_0_1_1RnRnRnRnRdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : SXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>}              ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_0_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : SXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>}              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_0_0_0_1_1_1_1RdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : SXTB16<c> <Rd>,<Rm>{,<rotation>}                  ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_0_0_1_0_1_1_1_1_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : SXTB16<c> <Rd>,<Rm>{,<rotation>}                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_0_1_0_1_1_1_1RdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : SXTB<c> <Rd>,<Rm>{,<rotation>}                    ~ [ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_1_0_0_1_0_0_1_1_1_1_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : SXTB<c>.W <Rd>,<Rm>{,<rotation>}                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_0_1_1_1_1_1_1RdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : SXTH<c> <Rd>,<Rm>{,<rotation>}                    ~ [ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_1_0_0_0_0_0_1_1_1_1_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : SXTH<c>.W <Rd>,<Rm>{,<rotation>}                  ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_0_1_0_0_0_1_1_0_1RnRnRnRn_1_1_1_1_0_0_0_0_0_0_0IiRmRmRmRm : TBB<c> [<Rn>,<Rm>]                                ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_0_0_1_1RnRnRnRn_0_0_0_0IiIiIiIiIiIiIiIiIiIiIiIi : TEQ<c> <Rn>,#<ArmExpandImm_C(imm)>                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0Ii_0_0_1_0_0_1RnRnRnRn_0IiIiIi_1_1_1_1IiIiIiIiIiIiIiIi : TEQ<c> <Rn>,#<ThumbExpandImm_C(imm)>              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_1RnRnRnRn_0_0_0_0RsRsRsRs_0TyTy_1RmRmRmRm : TEQ<c> <Rn>,<Rm>,<type> <Rs>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_1_1RnRnRnRn_0_0_0_0IiIiIiIiIiStSt_0RmRmRmRm : TEQ<c> <Rn>,<Rm>{,<shift>}                        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_0_1_0_1_0_1_0_0_1RnRnRnRn_0IiIiIi_1_1_1_1IiIiStStRmRmRmRm : TEQ<c> <Rn>,<Rm>{,<shift>}                        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_1_1_0_0_0_1RnRnRnRn_0_0_0_0IiIiIiIiIiIiIiIiIiIiIiIi : TST<c> <Rn>,#<ArmExpandImm_C(imm)>                ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_0Ii_0_0_0_0_0_1RnRnRnRn_0IiIiIi_1_1_1_1IiIiIiIiIiIiIiIi : TST<c> <Rn>,#<ThumbExpandImm_C(imm)>              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_0_1RnRnRnRn_0_0_0_0RsRsRsRs_0TyTy_1RmRmRmRm : TST<c> <Rn>,<Rm>,<type> <Rs>                      ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_0_0_1_0_0_0_1RnRnRnRn_0_0_0_0IiIiIiIiIiStSt_0RmRmRmRm : TST<c> <Rn>,<Rm>{,<shift>}                        ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T2 : _1_1_1_0_1_0_1_0_0_0_0_1RnRnRnRn_0IiIiIi_1_1_1_1IiIiTyTyRmRmRmRm : TST<c>.W                                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_0_1RnRnRnRnRdRdRdRd_1_1_1_1_0_0_0_1RmRmRmRm : UADD16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_0RmRmRmRm : UADD16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_0_1RnRnRnRnRdRdRdRd_1_1_1_1_1_0_0_1RmRmRmRm : UADD8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_0RmRmRmRm : UADD8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_0_1RnRnRnRnRdRdRdRd_1_1_1_1_0_0_1_1RmRmRmRm : UASX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_0RmRmRmRm : UASX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_1_1_1WiWiWiWiWiRdRdRdRdLbLbLbLbLb_1_0_1RnRnRnRn : UBFX<c> <Rd>,<Rn>,#<lsb>,#<width>                 ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_1_0_0RnRnRnRn_0IiIiIiRdRdRdRdIiIi_0WiWiWiWiWi : UBFX<c> <Rd>,<Rn>,#<lsb>,#<width>                 ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_0_1_1RnRnRnRn_1_1_1_1RdRdRdRd_1_1_1_1RmRmRmRm : UDIV<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv7-R]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_1RnRnRnRnRdRdRdRd_1_1_1_1_0_0_0_1RmRmRmRm : UHADD16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_1_1_0RmRmRmRm : UHADD16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_1RnRnRnRnRdRdRdRd_1_1_1_1_1_0_0_1RmRmRmRm : UHADD8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_1_0RmRmRmRm : UHADD8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_1RnRnRnRnRdRdRdRd_1_1_1_1_0_0_1_1RmRmRmRm : UHASX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_1_0RmRmRmRm : UHASX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_1RnRnRnRnRdRdRdRd_1_1_1_1_0_1_0_1RmRmRmRm : UHSAX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_1_0RmRmRmRm : UHSAX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_1RnRnRnRnRdRdRdRd_1_1_1_1_0_1_1_1RmRmRmRm : UHSUB16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_1_1_0RmRmRmRm : UHSUB16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_1RnRnRnRnRdRdRdRd_1_1_1_1_1_1_1_1RmRmRmRm : UHSUB8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_1_0RmRmRmRm : UHSUB8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_0_1_0_0RhRhRhRhRlRlRlRlRmRmRmRm_1_0_0_1RnRnRnRn : UMAAL<c> <RdLo>,<RdHi>,<Rn>,<Rm>                  ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_1_1_0RnRnRnRnRlRlRlRlRhRhRhRh_0_1_1_0RmRmRmRm : UMAAL<c> <RdLo>,<RdHi>,<Rn>,<Rm>                  ~ [ARMv6T2, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_1_1_0RnRnRnRnRlRlRlRlRhRhRhRh_0_0_0_0RmRmRmRm : UMLAL<c> <RdLo>,<RdHi>,<Rn>,<Rm>                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_0_1XsRhRhRhRhRlRlRlRlRmRmRmRm_1_0_0_1RnRnRnRn : UMLAL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm>               ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_1_0_1_0RnRnRnRnRlRlRlRlRhRhRhRh_0_0_0_0RmRmRmRm : UMULL<c> <RdLo>,<RdHi>,<Rn>,<Rm>                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_0_0_0_1_0_0XsRhRhRhRhRlRlRlRlRmRmRmRm_1_0_0_1RnRnRnRn : UMULL{S}<c> <RdLo>,<RdHi>,<Rn>,<Rm>               ~ [ARMv4*, ARMv5T*, ARMv6*, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_0RnRnRnRnRdRdRdRd_1_1_1_1_0_0_0_1RmRmRmRm : UQADD16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_1RmRmRmRm : UQADD16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_0RnRnRnRnRdRdRdRd_1_1_1_1_1_0_0_1RmRmRmRm : UQADD8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_1RmRmRmRm : UQADD8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_0RnRnRnRnRdRdRdRd_1_1_1_1_0_0_1_1RmRmRmRm : UQASX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_0_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_1RmRmRmRm : UQASX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_0RnRnRnRnRdRdRdRd_1_1_1_1_0_1_0_1RmRmRmRm : UQSAX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_1RmRmRmRm : UQSAX<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_0RnRnRnRnRdRdRdRd_1_1_1_1_0_1_1_1RmRmRmRm : UQSUB16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_1RmRmRmRm : UQSUB16<c> <Rd>,<Rn>,<Rm>                         ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_1_0RnRnRnRnRdRdRdRd_1_1_1_1_1_1_1_1RmRmRmRm : UQSUB8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_1RmRmRmRm : UQSUB8<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_1_0_0_0RdRdRdRd_1_1_1_1RmRmRmRm_0_0_0_1RnRnRnRn : USAD8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_1_1RnRnRnRn_1_1_1_1RdRdRdRd_0_0_0_0RmRmRmRm : USAD8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_1_1_0_0_0RdRdRdRdRaRaRaRaRmRmRmRm_0_0_0_1RnRnRnRn : USADA8<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_1_0_1_1_1RnRnRnRnRaRaRaRaRdRdRdRd_0_0_0_0RmRmRmRm : USADA8<c> <Rd>,<Rn>,<Rm>,<Ra>                     ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_1_1_0IiIiIiIiRdRdRdRd_1_1_1_1_0_0_1_1RnRnRnRn : USAT16<c> <Rd>,#<imm>,<Rn>                        ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_0_1_0RnRnRnRn_0_0_0_0RdRdRdRd_0_0_0_0IiIiIiIi : USAT16<c> <Rd>,#<imm>,<Rn>                        ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_1_1SiSiSiSiSiRdRdRdRdIiIiIiIiIiSh_0_1RnRnRnRn : USAT<c> <Rd>,#<DecodeImmShift(sh0,imm)>,<Rn>{,<shift>}  ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_0_0_1_1_1_0Sh_0RnRnRnRn_0IiIiIiRdRdRdRdIiIi_0SiSiSiSiSi : USAT<c> <Rd>,#<DecodeImmShift(sh0,imm)>,<Rn>{,<shift>}  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_0_1RnRnRnRnRdRdRdRd_1_1_1_1_0_1_0_1RmRmRmRm : USAX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_1_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_0RmRmRmRm : USAX<c> <Rd>,<Rn>,<Rm>                            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_0_1RnRnRnRnRdRdRdRd_1_1_1_1_0_1_1_1RmRmRmRm : USUB16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_1RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_0RmRmRmRm : USUB16<c> <Rd>,<Rn>,<Rm>                          ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_0_1_0_1RnRnRnRnRdRdRdRd_1_1_1_1_1_1_1_1RmRmRmRm : USUB8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_1_1_0_0RnRnRnRn_1_1_1_1RdRdRdRd_0_1_0_0RmRmRmRm : USUB8<c> <Rd>,<Rn>,<Rm>                           ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_1_0_0RnRnRnRnRdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : UXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>}            ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_0_0_1_1RnRnRnRn_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : UXTAB16<c> <Rd>,<Rn>,<Rm>{,<rotation>}            ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_1_1_0RnRnRnRnRdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : UXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>}              ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_0_1_0_1RnRnRnRn_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : UXTAB<c> <Rd>,<Rn>,<Rm>{,<rotation>}              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_1_1_1RnRnRnRnRdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : UXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>}              ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_0_0_0_1RnRnRnRn_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : UXTAH<c> <Rd>,<Rn>,<Rm>{,<rotation>}              ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_1_0_0_1_1_1_1RdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : UXTB16<c> <Rd>,<Rm>{,<rotation>}                  ~ [ARMv6*, ARMv7]
      T1 : _1_1_1_1_1_0_1_0_0_0_1_1_1_1_1_1_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : UXTB16<c> <Rd>,<Rm>{,<rotation>}                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_1_1_0_1_1_1_1RdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : UXTB<c> <Rd>,<Rm>{,<rotation>}                    ~ [ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_1_0_0_1_0_1_1_1_1_1_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : UXTB<c>.W <Rd>,<Rm>{,<rotation>}                  ~ [ARMv6T2, ARMv7]
      A1 : CcCcCcCc_0_1_1_0_1_1_1_1_1_1_1_1RdRdRdRdXrXr_0_0_0_1_1_1RmRmRmRm : UXTH<c> <Rd>,<Rm>{,<rotation>}                    ~ [ARMv6*, ARMv7]
      T2 : _1_1_1_1_1_0_1_0_0_0_0_1_1_1_1_1_1_1_1_1RdRdRdRd_1_0XrXrRmRmRmRm : UXTH<c>.W <Rd>,<Rm>{,<rotation>}                  ~ [ARMv6T2, ARMv7]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_0VdOpOpVnVnVnVnVdVdVdVd_0_0_0_1XnXQXM_1VmVmVmVm : V<op><c> <Qd>,<Qn>,<Qm>                           ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1VnVnVnVnVdVdVdVd_1_0XsXsXnOpXM_0VmVmVmVm : V<op><c>.8 <Dd>,<list>,<Dm>                       ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XQ_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_0Op_0XFXn_1XM_0VmVmVmVm : V<op><c>.<dt> <Qd>,<Qn>,<Dm[x]>                   ~ [Advanced SIMD (F = 1 UNDEFINED in integer-only variants)]
~TODO T1 / A1 : _1_1_1Op_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_1_0_0_1XnXQXM_0VmVmVmVm : V<op><c>.<dt> <Qd>,<Qn>,<Qm>                      ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_1_1_0XnXQXMOpVmVmVmVm : V<op><c>.<dt> <Qd>,<Qn>,<Qm>                      ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0VdOpSzVnVnVnVnVdVdVdVd_1_1_0_1XnXQXM_1VmVmVmVm : V<op><c>.F32 <Qd>,<Qn>,<Qm>                       ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0VdOpSzVnVnVnVnVdVdVdVd_1_1_1_1XnXQXM_0VmVmVmVm : V<op><c>.F32 <Qd>,<Qn>,<Qm>                       ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_0VdOpSzVnVnVnVnVdVdVdVd_1_1_1_0XnXQXM_1VmVmVmVm : V<op><c>.F32 <Qd>,<Qn>,<Qm>                       ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T2 / A2 : _1_1_1_0_1_1_1_0_0Vd_0_0VnVnVnVnVdVdVdVd_1_0_1SzXnOpXM_0VmVmVmVm : V<op><c>.F64 <Dd>,<Dn>,<Dm>                       ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T2 / A2 : _1_1_1XU_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_1_0Op_0Xn_0XM_0VmVmVmVm : V<op>L<c>.<dt> <Qd>,<Dn>,<Dm>                     ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1XU_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_0Op_1_0Xn_1XM_0VmVmVmVm : V<op>L<c>.<dt> <Qd>,<Dn>,<Dm[x]>                  ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_1_1_1XnXQXM_1VmVmVmVm : VABA<c>.<dt>                                      ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1XU_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_0_1_0_1Xn_0XM_0VmVmVmVm : VABAL<c>.<dt>                                     ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_1_1_1XnXQXM_0VmVmVmVm : VABD<c>.<dt>                                      ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_0Vd_1SzVnVnVnVnVdVdVdVd_1_1_0_1XnXQXM_0VmVmVmVm : VABD<c>.F32                                       ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T2 / A2 : _1_1_1XU_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_0_1_1_1Xn_0XM_0VmVmVmVm : VABDL<c>.<dt>                                     ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_1VdVdVdVd_0XF_1_1_0XQXM_0VmVmVmVm : VABS<c>.<dt> <Qd>,<Qm>                            ~ [Advanced SIMD (F = 1 UNDEFINED in integer-only variants)]
~TODO T2 / A2 : _1_1_1_0_1_1_1_0_1Vd_1_1_0_0_0_0VdVdVdVd_1_0_1Sz_1_1XM_0VmVmVmVm : VABS<c>.F64 <Dd>,<Dm>                             ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_1_0_0_0XnXQXM_0VmVmVmVm : VADD<c>.<dt> <Qd>,<Qn>,<Qm>                       ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0Vd_0SzVnVnVnVnVdVdVdVd_1_1_0_1XnXQXM_0VmVmVmVm : VADD<c>.F32 <Qd>,<Qn>,<Qm>                        ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T2 / A2 : _1_1_1_0_1_1_1_0_0Vd_1_1VnVnVnVnVdVdVdVd_1_0_1SzXn_0XM_0VmVmVmVm : VADD<c>.F64 <Dd>,<Dn>,<Dm>                        ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_0_1_0_0Xn_0XM_0VmVmVmVm : VADDHN<c>.<dt> <Dd>,<Qn>,<Qm>                     ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_0_0_0OpXn_0XM_0VmVmVmVm : VADDL<c>.<dt> <Qd>,<Dn>,<Dm>                      ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0Vd_0_0VnVnVnVnVdVdVdVd_0_0_0_1XnXQXM_1VmVmVmVm : VAND<c> <Qd>,<Qn>,<Qm>                            ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0Vd_0_1VnVnVnVnVdVdVdVd_0_0_0_1XnXQXM_1VmVmVmVm : VBIC<c> <Qd>,<Qn>,<Qm>                            ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1Ii_1_1_1_1_1Vd_0_0_0IiIiIiVdVdVdVdXCXCXCXC_0XQ_1_1IiIiIiIi : VBIC<c>.<dt> <Qd>,#<imm>                          ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_1VdVdVdVd_0XF_0_1_0XQXM_0VmVmVmVm : VCEQ<c>.<dt> <Qd>,<Qm>,#0                         ~ [Advanced SIMD (F = 1 UNDEFINED in integer-only variants)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_1_0_0_0XnXQXM_1VmVmVmVm : VCEQ<c>.<dt> <Qd>,<Qn>,<Qm>                       ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1_0_1_1_1_1_0Vd_0SzVnVnVnVnVdVdVdVd_1_1_1_0XnXQXM_0VmVmVmVm : VCEQ<c>.F32 <Qd>,<Qn>,<Qm>                        ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_1VdVdVdVd_0XF_0_0_1XQXM_0VmVmVmVm : VCGE<c>.<dt> <Qd>,<Qm>,#0                         ~ [Advanced SIMD (F = 1 UNDEFINED in integer-only variants)]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_0_1_1XnXQXM_1VmVmVmVm : VCGE<c>.<dt> <Qd>,<Qn>,<Qm>                       ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1_1_1_1_1_1_0Vd_0SzVnVnVnVnVdVdVdVd_1_1_1_0XnXQXM_0VmVmVmVm : VCGE<c>.F32 <Qd>,<Qn>,<Qm>                        ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_1VdVdVdVd_0XF_0_0_0XQXM_0VmVmVmVm : VCGT<c>.<dt> <Qd>,<Qm>,#0                         ~ [Advanced SIMD (F = 1 UNDEFINED in integer-only variants)]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_0_1_1XnXQXM_0VmVmVmVm : VCGT<c>.<dt> <Qd>,<Qn>,<Qm>                       ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1_1_1_1_1_1_0Vd_1SzVnVnVnVnVdVdVdVd_1_1_1_0XnXQXM_0VmVmVmVm : VCGT<c>.F32 <Qd>,<Qn>,<Qm>                        ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_1VdVdVdVd_0XF_0_1_1XQXM_0VmVmVmVm : VCLE<c>.<dt> <Qd>,<Qm>,#0                         ~ [Advanced SIMD (F = 1 UNDEFINED in integer-only variants)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_0VdVdVdVd_0_1_0_0_0XQXM_0VmVmVmVm : VCLS<c>.<dt> <Qd>,<Qm>                            ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_1VdVdVdVd_0XF_1_0_0XQXM_0VmVmVmVm : VCLT<c>.<dt> <Qd>,<Qm>,#0                         ~ [Advanced SIMD (F = 1 UNDEFINED in integer-only variants)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_0VdVdVdVd_0_1_0_0_1XQXM_0VmVmVmVm : VCLZ<c>.<dt> <Qd>,<Qm>                            ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1_0_1_1_1_0_1Vd_1_1_0_1_0_1VdVdVdVd_1_0_1SzXE_1_0_0_0_0_0_0 : VCMP{E}<c>.F64 <Dd>,#0.0                          ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_1Vd_1_1_0_1_0_0VdVdVdVd_1_0_1SzXE_1XM_0VmVmVmVm : VCMP{E}<c>.F64 <Dd>,<Dm>                          ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_0VdVdVdVd_0_1_0_1_0XQXM_0VmVmVmVm : VCNT<c>.8 <Qd>,<Qm>                               ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_1_1VdVdVdVd_0_1_1OpOpXQXM_0VmVmVmVm : VCVT<c>.<Td>.<Tm> <Qd>,<Qm>                       ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_1_1_1Op_0XQXM_1VmVmVmVm : VCVT<c>.<Td>.<Tm> <Qd>,<Qm>,#<fbits>              ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_1Vd_1_1_1Op_1XUVdVdVdVd_1_0_1SfSx_1Ii_0IiIiIiIi : VCVT<c>.<Td>.F64 <Dd>,<Dd>,#<fbits>               ~ [VFPv3 (sf = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_1_0VdVdVdVd_0_1_1Op_0_0XM_0VmVmVmVm : VCVT<c>.F32.F16 <Qd>,<Dm>                         ~ [Advanced SIMD with half-precision extensions (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_1Vd_1_1_0_1_1_1VdVdVdVd_1_0_1Sz_1_1XM_0VmVmVmVm : VCVT<c>.F64.F32 <Dd>,<Sm>                         ~ [VFPv2, VFPv3 (UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_1Vd_1_1_0_0_1OpVdVdVdVd_1_0_1_0XT_1XM_0VmVmVmVm : VCVT<y><c>.F32.F16 <Sd>,<Sm>                      ~ [VFPv3 half-precision extensions]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_1Vd_1_1_1O2O2O2VdVdVdVd_1_0_1SzOp_1XM_0VmVmVmVm : VCVT{R}<c>.S32.F64 <Sd>,<Dm>                      ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_1Vd_0_0VnVnVnVnVdVdVdVd_1_0_1SzXn_0XM_0VmVmVmVm : VDIV<c>.F64 <Dd>,<Dn>,<Dm>                        ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_1XBXQ_0VdVdVdVdRtRtRtRt_1_0_1_1Vd_0XE_1_0_0_0_0 : VDUP<c>.<size>                                    ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1IiIiIiIiVdVdVdVd_1_1_0_0_0XQXM_0VmVmVmVm : VDUP<c>.<size>                                    ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_0Vd_0_0VnVnVnVnVdVdVdVd_0_0_0_1XnXQXM_1VmVmVmVm : VEOR<c> <Qd>,<Qn>,<Qm>                            ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_1Vd_1_1VnVnVnVnVdVdVdVdIiIiIiIiXnXQXM_0VmVmVmVm : VEXT<c>.8 <Qd>,<Qn>,<Qm>,#<imm>                   ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_0Op_0XnXQXM_0VmVmVmVm : VH<op><c> <Qd>,<Qn>,<Qm>                          ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_0Vd_1_0RnRnRnRnVdVdVdVdTyTyTyTyXsXsXaXaRmRmRmRm : VLD1<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_1_0RnRnRnRnVdVdVdVdXsXs_0_0XiXiXiXiRmRmRmRm : VLD1<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_1_0RnRnRnRnVdVdVdVd_1_1_0_0XsXsXTXaRmRmRmRm : VLD1<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_0Vd_1_0RnRnRnRnVdVdVdVdTyTyTyTyXsXsXaXaRmRmRmRm : VLD2<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_1_0RnRnRnRnVdVdVdVdXsXs_0_1XiXiXiXiRmRmRmRm : VLD2<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_1_0RnRnRnRnVdVdVdVd_1_1_0_1XsXsXTXaRmRmRmRm : VLD2<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_1_0RnRnRnRnVdVdVdVdXsXs_1_0XiXiXiXiRmRmRmRm : VLD3<c>.<size> <list>,[<Rn>]{!}                   ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_1_0RnRnRnRnVdVdVdVd_1_1_1_0XsXsXTXaRmRmRmRm : VLD3<c>.<size> <list>,[<Rn>]{!}                   ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_0Vd_1_0RnRnRnRnVdVdVdVdTyTyTyTyXsXsXaXaRmRmRmRm : VLD3<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_1_0RnRnRnRnVdVdVdVd_1_1_1_1XsXsXTXaRmRmRmRm : VLD4<c>.<size> <list>,[<Rn>{ @<align>}]{!}        ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_0Vd_1_0RnRnRnRnVdVdVdVdTyTyTyTyXsXsXaXaRmRmRmRm : VLD4<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_1_0RnRnRnRnVdVdVdVdXsXs_1_1XiXiXiXiRmRmRmRm : VLD4<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1_0_1_1_0XPXUVdXw_1RnRnRnRnVdVdVdVd_1_0_1_0IiIiIiIiIiIiIiIi : VLDM{mode}<c> <Rn>{!},<list>                      ~ [VFPv2, VFPv3]
~TODO T1 / A1 : _1_1_1_0_1_1_0XPXUVdXw_1RnRnRnRnVdVdVdVd_1_0_1_1IiIiIiIiIiIiIiIi : VLDM{mode}<c> <Rn>{!},<list>                      ~ [VFPv2, VFPv3, Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_0_1XUVd_0_1RnRnRnRnVdVdVdVd_1_0_1_1IiIiIiIiIiIiIiIi : VLDR<c> <Dd>,[<Rn>,#+/-<imm>]                     ~ [VFPv2, VFPv3, Advanced SIMD]
~TODO T2 / A2 : _1_1_1_0_1_1_0_1XUVd_0_1RnRnRnRnVdVdVdVd_1_0_1_0IiIiIiIiIiIiIiIi : VLDR<c> <Sd>,[<Rn>,#+/-<imm>]                     ~ [VFPv2, VFPv3]
~TODO T1 / A1 : _1_1_1_0_1_1_0_0_0_1_0OpRTRTRTRTRtRtRtRt_1_0_1_1_0_0XM_1VmVmVmVm : VMOV<c> <Dm>,<Rt>,<Rt2>                           ~ [VFPv2, VFPv3, Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0Vd_1_0VmVmVmVmVdVdVdVd_0_0_0_1XMXQXM_1VmVmVmVm : VMOV<c> <Qd>,<Qm>                                 ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_0_0_0_1_0OpRTRTRTRTRtRtRtRt_1_0_1_0_0_0XM_1VmVmVmVm : VMOV<c> <Sm>,<Sm1>,<Rt>,<Rt2>                     ~ [VFPv2, VFPv3]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_0_0_0OpVnVnVnVnRtRtRtRt_1_0_1_0Xn_0_0_1_0_0_0_0 : VMOV<c> <Sn>,<Rt>                                 ~ [VFPv2, VFPv3]
~TODO T1 / A1 : _1_1_1Ii_1_1_1_1_1Vd_0_0_0IiIiIiVdVdVdVdXCXCXCXC_0XQOp_1IiIiIiIi : VMOV<c>.<dt> <Qd>,#<imm>                          ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0XUO1O1_1VnVnVnVnRtRtRtRt_1_0_1_1XnO2O2_1_0_0_0_0 : VMOV<c>.<dt> <Rt>,<Dn[x]>                         ~ [VFPv2, VFPv3, Advanced SIMD if opc1 == â0xâ && opc2 == '00']
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_0O1O1_0VdVdVdVdRtRtRtRt_1_0_1_1VdO2O2_1_0_0_0_0 : VMOV<c>.<size> <Dd[x]>,<Rt>                       ~ [VFPv2, VFPv3, Advanced SIMD if opc1 == â0xâ && opc2 == '00']
~TODO T2 / A2 : _1_1_1_0_1_1_1_0_1Vd_1_1IiIiIiIiVdVdVdVd_1_0_1Sz_0_0_0_0IiIiIiIi : VMOV<c>.F64 <Dd>,#<imm>                           ~ [VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T2 / A2 : _1_1_1_0_1_1_1_0_1Vd_1_1_0_0_0_0VdVdVdVd_1_0_1Sz_0_1XM_0VmVmVmVm : VMOV<c>.F64 <Dd>,<Dm>                             ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdIiIiIi_0_0_0VdVdVdVd_1_0_1_0_0_0XM_1VmVmVmVm : VMOVL<c>.<dt> <Qd>,<Dm>                           ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_1_0VdVdVdVd_0_0_1_0_0_0XM_0VmVmVmVm : VMOVN<c>.<dt> <Dd>,<Qm>                           ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_1_1_1_1_0_0_0_1RtRtRtRt_1_0_1_0_0_0_0_1_0_0_0_0 : VMRS<c> <Rt>,FPSCR                                ~ [VFPv2, VFPv3, Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_1_1_1_0_0_0_0_1RtRtRtRt_1_0_1_0_0_0_0_1_0_0_0_0 : VMSR<c> FPSCR,<Rt>                                ~ [VFPv2, VFPv3, Advanced SIMD]
~TODO T1 / A1 : _1_1_1XQ_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_1_0_0XFXn_1XM_0VmVmVmVm : VMUL<c>.<dt> <Qd>,<Qn>,<Dm[x]>                    ~ [Advanced SIMD (F = 1 UNDEFINED in integer-only variants)]
~TODO T1 / A1 : _1_1_1Op_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_1_0_0_1XnXQXM_1VmVmVmVm : VMUL<c>.<dt> <Qd>,<Qn>,<Qm>                       ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_0Vd_0SzVnVnVnVnVdVdVdVd_1_1_0_1XnXQXM_1VmVmVmVm : VMUL<c>.F32 <Qd>,<Qn>,<Qm>                        ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T2 / A2 : _1_1_1_0_1_1_1_0_0Vd_1_0VnVnVnVnVdVdVdVd_1_0_1SzXn_0XM_0VmVmVmVm : VMUL<c>.F64 <Dd>,<Dn>,<Dm>                        ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T2 / A2 : _1_1_1XU_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_1_1Op_0Xn_0XM_0VmVmVmVm : VMULL<c>.<dt> <Qd>,<Dn>,<Dm>                      ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1XU_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_1_0_1_0Xn_1XM_0VmVmVmVm : VMULL<c>.<dt> <Qd>,<Dn>,<Dm[x]>                   ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_0VdVdVdVd_0_1_0_1_1XQXM_0VmVmVmVm : VMVN<c> <Qd>,<Qm>                                 ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1Ii_1_1_1_1_1Vd_0_0_0IiIiIiVdVdVdVdXCXCXCXC_0XQ_1_1IiIiIiIi : VMVN<c>.<dt> <Qd>,#<imm>                          ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_1VdVdVdVd_0XF_1_1_1XQXM_0VmVmVmVm : VNEG<c>.<dt> <Qd>,<Qm>                            ~ [Advanced SIMD (F = 1 UNDEFINED in integer-only variants)]
~TODO T2 / A2 : _1_1_1_0_1_1_1_0_1Vd_1_1_0_0_0_1VdVdVdVd_1_0_1Sz_0_1XM_0VmVmVmVm : VNEG<c>.F64 <Dd>,<Dm>                             ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_0Vd_0_1VnVnVnVnVdVdVdVd_1_0_1SzXnOpXM_0VmVmVmVm : VNMLA<c>.F64 <Dd>,<Dn>,<Dm>                       ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T2 / A2 : _1_1_1_0_1_1_1_0_0Vd_1_0VnVnVnVnVdVdVdVd_1_0_1SzXn_1XM_0VmVmVmVm : VNMUL<c>.F64 <Dd>,<Dn>,<Dm>                       ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0Vd_1_1VnVnVnVnVdVdVdVd_0_0_0_1XnXQXM_1VmVmVmVm : VORN<c> <Qd>,<Qn>,<Qm>                            ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0Vd_1_0VnVnVnVnVdVdVdVd_0_0_0_1XnXQXM_1VmVmVmVm : VORR<c> <Qd>,<Qn>,<Qm>                            ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1Ii_1_1_1_1_1Vd_0_0_0IiIiIiVdVdVdVdXCXCXCXC_0XQ_0_1IiIiIiIi : VORR<c>.<dt> <Qd>,#<imm>                          ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_1_0_1_0XnXQXMOpVmVmVmVm : VP<op><c>.<dt>                                    ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_0VdOpSzVnVnVnVnVdVdVdVd_1_1_1_1XnXQXM_0VmVmVmVm : VP<op><c>.F32                                     ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_0VdVdVdVd_0_1_1_0OpXQXM_0VmVmVmVm : VPADAL<c>.<dt>                                    ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_1_0_1_1XnXQXM_1VmVmVmVm : VPADD<c>.<dt>                                     ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_0Vd_0SzVnVnVnVnVdVdVdVd_1_1_0_1XnXQXM_0VmVmVmVm : VPADD<c>.F32                                      ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_0VdVdVdVd_0_0_1_0OpXQXM_0VmVmVmVm : VPADDL<c>.<dt>                                    ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1_0_1_1_0_0_1Vd_1_1_1_1_0_1VdVdVdVd_1_0_1_0IiIiIiIiIiIiIiIi : VPOP <list>                                       ~ [VFPv2, VFPv3]
~TODO T1 / A1 : _1_1_1_0_1_1_0_0_1Vd_1_1_1_1_0_1VdVdVdVd_1_0_1_1IiIiIiIiIiIiIiIi : VPOP <list>                                       ~ [VFPv2, VFPv3, Advanced SIMD]
~TODO T2 / A2 : _1_1_1_0_1_1_0_1_0Vd_1_0_1_1_0_1VdVdVdVd_1_0_1_0IiIiIiIiIiIiIiIi : VPUSH<c> <list>                                   ~ [VFPv2, VFPv3]
~TODO T1 / A1 : _1_1_1_0_1_1_0_1_0Vd_1_0_1_1_0_1VdVdVdVd_1_0_1_1IiIiIiIiIiIiIiIi : VPUSH<c> <list>                                   ~ [VFPv2, VFPv3, Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_0VdVdVdVd_0_1_1_1_0XQXM_0VmVmVmVm : VQABS<c>.<dt> <Qd>,<Qm>                           ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_0_0_0XnXQXM_1VmVmVmVm : VQADD<c>.<dt> <Qd>,<Qn>,<Qm>                      ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_1_0Op_1Xn_0XM_0VmVmVmVm : VQD<op><c>.<dt> <Qd>,<Dn>,<Dm>                    ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1_0_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_0Op_1_1Xn_1XM_0VmVmVmVm : VQD<op><c>.<dt> <Qd>,<Dn>,<Dm[x]>                 ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1XQ_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_1_1_0_0Xn_1XM_0VmVmVmVm : VQDMULH<c>.<dt> <Qd>,<Qn>,<Dm[x]>                 ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_1_0_1_1XnXQXM_0VmVmVmVm : VQDMULH<c>.<dt> <Qd>,<Qn>,<Qm>                    ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_1_1_0_1Xn_0XM_0VmVmVmVm : VQDMULL<c>.<dt> <Qd>,<Dn>,<Dm>                    ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1_0_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_1_0_1_1Xn_1XM_0VmVmVmVm : VQDMULL<c>.<dt> <Qd>,<Dn>,<Dm[x]>                 ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_1_0VdVdVdVd_0_0_1_0OpOpXM_0VmVmVmVm : VQMOV{U}N<c>.<type><size> <Dd>,<Qm>               ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_0VdVdVdVd_0_1_1_1_1XQXM_0VmVmVmVm : VQNEG<c>.<dt> <Qd>,<Qm>                           ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1XQ_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_1_1_0_1Xn_1XM_0VmVmVmVm : VQRDMULH<c>.<dt> <Qd>,<Qn>,<Dm[x]>                ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_1_0_1_1XnXQXM_0VmVmVmVm : VQRDMULH<c>.<dt> <Qd>,<Qn>,<Qm>                   ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_1_0_1XnXQXM_1VmVmVmVm : VQRSHL<c>.<type><size> <Qd>,<Qm>,<Qn>             ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_1_0_0Op_0_1XM_1VmVmVmVm : VQRSHR{U}N<c>.<type><size> <Dd>,<Qm>,#<imm>       ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_1_0_0XnXQXM_1VmVmVmVm : VQSHL<c>.<type><size> <Qd>,<Qm>,<Qn>              ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_0_1_1OpXLXQXM_1VmVmVmVm : VQSHL{U}<c>.<type><size> <Qd>,<Qm>,#<imm>         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_1_0_0Op_0_0XM_1VmVmVmVm : VQSHR{U}N<c>.<type><size> <Dd>,<Qm>,#<imm>        ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_0_1_0XnXQXM_1VmVmVmVm : VQSUB<c>.<type><size> <Qd>,<Qn>,<Qm>              ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_0_1_0_0Xn_0XM_0VmVmVmVm : VRADDHN<c>.<dt> <Dd>,<Qn>,<Qm>                    ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_1_1VdVdVdVd_0_1_0XF_0XQXM_0VmVmVmVm : VRECPE<c>.<dt> <Qd>,<Qm>                          ~ [Advanced SIMD (F = 1 UNDEFINED in integer-only variants)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0Vd_0SzVnVnVnVnVdVdVdVd_1_1_1_1XnXQXM_1VmVmVmVm : VRECPS<c>.F32 <Qd>,<Qn>,<Qm>                      ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_0_0VdVdVdVd_0_0_0OpOpXQXM_0VmVmVmVm : VREV<n><c>.<size> <Qd>,<Qm>                       ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_0_0_1XnXQXM_0VmVmVmVm : VRHADD<c> <Qd>,<Qn>,<Qm>                          ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_1_0_1XnXQXM_0VmVmVmVm : VRSHL<c>.<type><size> <Qd>,<Qm>,<Qn>              ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_0_0_1_0XLXQXM_1VmVmVmVm : VRSHR<c>.<type><size> <Qd>,<Qm>,#<imm>            ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_1_0_0_0_0_1XM_1VmVmVmVm : VRSHRN<c>.I<size> <Dd>,<Qm>,#<imm>                ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_1_1VdVdVdVd_0_1_0XF_1XQXM_0VmVmVmVm : VRSQRTE<c>.<dt> <Qd>,<Qm>                         ~ [Advanced SIMD (F = 1 UNDEFINED in integer-only variants)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0Vd_1SzVnVnVnVnVdVdVdVd_1_1_1_1XnXQXM_1VmVmVmVm : VRSQRTS<c>.F32 <Qd>,<Qn>,<Qm>                     ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_0_0_1_1XLXQXM_1VmVmVmVm : VRSRA<c>.<type><size> <Qd>,<Qm>,#<imm>            ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_0_1_1_0Xn_0XM_0VmVmVmVm : VRSUBHN<c>.<dt> <Dd>,<Qn>,<Qm>                    ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_0_1_0_1XLXQXM_1VmVmVmVm : VSHL<c>.I<size> <Qd>,<Qm>,#<imm>                  ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_0_1_0_0XnXQXM_0VmVmVmVm : VSHL<c>.I<size> <Qd>,<Qm>,<Qn>                    ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_1_0_1_0_0_0XM_1VmVmVmVm : VSHLL<c>.<type><size> <Qd>,<Dm>,#<imm>            ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_1_0VdVdVdVd_0_0_1_1_0_0XM_0VmVmVmVm : VSHLL<c>.<type><size> <Qd>,<Dm>,#<imm>            ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_0_0_0_0XLXQXM_1VmVmVmVm : VSHR<c>.<type><size> <Qd>,<Qm>,#<imm>             ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_1_0_0_0_0_0XM_1VmVmVmVm : VSHRN<c>.I<size> <Dd>,<Qm>,#<imm>                 ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_0_1_0_1XLXQXM_1VmVmVmVm : VSLI<c>.<size> <Qd>,<Qm>,#<imm>                   ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_0_1Vd_1_1_0_0_0_1VdVdVdVd_1_0_1Sz_1_1XM_0VmVmVmVm : VSQRT<c>.F64 <Dd>,<Dm>                            ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_0_0_0_1XLXQXM_1VmVmVmVm : VSRA<c>.<type><size> <Qd>,<Qm>,#<imm>             ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1VdIiIiIiIiIiIiVdVdVdVd_0_1_0_0XLXQXM_1VmVmVmVm : VSRI<c>.<size> <Qd>,<Qm>,#<imm>                   ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_0Vd_0_0RnRnRnRnVdVdVdVdTyTyTyTyXsXsXaXaRmRmRmRm : VST1<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_0_0RnRnRnRnVdVdVdVdXsXs_0_0XiXiXiXiRmRmRmRm : VST1<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_0Vd_0_0RnRnRnRnVdVdVdVdTyTyTyTyXsXsXaXaRmRmRmRm : VST2<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_0_0RnRnRnRnVdVdVdVdXsXs_0_1XiXiXiXiRmRmRmRm : VST2<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_0_0RnRnRnRnVdVdVdVdXsXs_1_0XiXiXiXiRmRmRmRm : VST3<c>.<size> <list>,[<Rn>]{!}                   ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_0Vd_0_0RnRnRnRnVdVdVdVdTyTyTyTyXsXsXaXaRmRmRmRm : VST3<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_0Vd_0_0RnRnRnRnVdVdVdVdTyTyTyTyXsXsXaXaRmRmRmRm : VST4<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_0_0_1_1Vd_0_0RnRnRnRnVdVdVdVdXsXs_1_1XiXiXiXiRmRmRmRm : VST4<c>.<size> <list>,[<Rn>{@<align>}]{!}         ~ [Advanced SIMD]
~TODO T2 / A2 : _1_1_1_0_1_1_0XPXUVdXw_0RnRnRnRnVdVdVdVd_1_0_1_0IiIiIiIiIiIiIiIi : VSTM{mode}<c> <Rn>{!},<list>                      ~ [VFPv2, VFPv3]
~TODO T1 / A1 : _1_1_1_0_1_1_0XPXUVdXw_0RnRnRnRnVdVdVdVd_1_0_1_1IiIiIiIiIiIiIiIi : VSTM{mode}<c> <Rn>{!},<list>                      ~ [VFPv2, VFPv3, Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_0_1XUVd_0_0RnRnRnRnVdVdVdVd_1_0_1_1IiIiIiIiIiIiIiIi : VSTR<c> <Dd>,[<Rn>,#+/-<imm>]                     ~ [VFPv2, VFPv3, Advanced SIMD]
~TODO T2 / A2 : _1_1_1_0_1_1_0_1XUVd_0_0RnRnRnRnVdVdVdVd_1_0_1_0IiIiIiIiIiIiIiIi : VSTR<c> <Sd>,[<Rn>,#+/-<imm>]                     ~ [VFPv2, VFPv3]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_1_0_0_0XnXQXM_0VmVmVmVm : VSUB<c>.<dt> <Qd>,<Qn>,<Qm>                       ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0Vd_1SzVnVnVnVnVdVdVdVd_1_1_0_1XnXQXM_0VmVmVmVm : VSUB<c>.F32 <Qd>,<Qn>,<Qm>                        ~ [Advanced SIMD (UNDEFINED in integer-only variant)]
~TODO T2 / A2 : _1_1_1_0_1_1_1_0_0Vd_1_1VnVnVnVnVdVdVdVd_1_0_1SzXn_1XM_0VmVmVmVm : VSUB<c>.F64 <Dd>,<Dn>,<Dm>                        ~ [VFPv2, VFPv3 (sz = 1 UNDEFINED in single-precision only variants)]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_0_1_1_0Xn_0XM_0VmVmVmVm : VSUBHN<c>.<dt> <Dd>,<Qn>,<Qm>                     ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1XU_1_1_1_1_1VdXsXsVnVnVnVnVdVdVdVd_0_0_1OpXn_0XM_0VmVmVmVm : VSUBL<c>.<dt> <Qd>,<Dn>,<Dm>                      ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_1_1_1_1_1_1Vd_1_1XsXs_1_0VdVdVdVd_0_0_0_0_0XQXM_0VmVmVmVm : VSWP<c> <Qd>,<Qm>                                 ~ [Advanced SIMD]
~TODO T1 / A1 : _1_1_1_0_1_1_1_1_0VdXsXsVnVnVnVnVdVdVdVd_1_0_0_0XnXQXM_1VmVmVmVm : VTST<c>.<size> <Qd>,<Qn>,<Qm>                     ~ [Advanced SIMD]
      A1 : CcCcCcCc_0_0_1_1_0_0_1_0_0_0_0_0_1_1_1_1_0_0_0_0_0_0_0_0_0_0_1_0 : WFE<c>                                            ~ [ARMv6K, ARMv7 (executes as NOP in ARMv6T2)]
      T2 : _1_1_1_1_0_0_1_1_1_0_1_0_1_1_1_1_1_0_0_0_0_0_0_0_0_0_0_0_0_0_1_0 : WFE<c>.W                                          ~ [ARMv7 (executes as NOP in ARMv6T2)]
      A1 : CcCcCcCc_0_0_1_1_0_0_1_0_0_0_0_0_1_1_1_1_0_0_0_0_0_0_0_0_0_0_1_1 : WFI<c>                                            ~ [ARMv6K, ARMv7 (executes as NOP in ARMv6T2)]
      T2 : _1_1_1_1_0_0_1_1_1_0_1_0_1_1_1_1_1_0_0_0_0_0_0_0_0_0_0_0_0_0_1_1 : WFI<c>.W                                          ~ [ARMv7 (executes as NOP in ARMv6T2)]
      A1 : CcCcCcCc_0_0_1_1_0_0_1_0_0_0_0_0_1_1_1_1_0_0_0_0_0_0_0_0_0_0_0_1 : YIELD<c>                                          ~ [ARMv6K, ARMv7 (executes as NOP in ARMv6T2)]
      T2 : _1_1_1_1_0_0_1_1_1_0_1_0_1_1_1_1_1_0_0_0_0_0_0_0_0_0_0_0_0_0_0_1 : YIELD<c>.W                                        ~ [ARMv7 (executes as NOP in ARMv6T2)]
