CPUtop Project Status
Project File:	P1.xise	Parser Errors:
Module Name:	CPUtop	Implementation State:	New
Target Device:	xc3s500e-4fg320	Errors:
Product Version:	ISE 14.6	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report	Current	周六 4月 4 06:38:49 2020	0	0	2 Infos (2 new)
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Current	周日 4月 5 15:47:11 2020

Date Generated: 04/05/2020 - 16:47:11 <