/*
  Name: pci
  Copyright: 
  Author: Joseph Emmanuel DL Dayo
  Date: 22/01/00 05:28
  Description: The PCI bus driver for DEX-OS using PCI bios to ensure maximum
               compatibility, some code derived from the ChaOS Operating System and
               most probably Linux credits to Fixa.
                
    DEX educational extensible operating system 1.0 Beta
    Copyright (C) 2004  Joseph Emmanuel DL Dayo
    
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.
    
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
    
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 
*/
#define PCI_FUNCTION_ID 0xB1
#define PCI_BIOS_PRESENT 0x1
#define FIND_PCI_DEVICE  0x2
#define FIND_PCI_CLASS_CODE 0x3
#define GENERATE_SPECIAL_CYCLE 0x6
#define READ_CONFIG_BYTE 0x8
#define READ_CONFIG_WORD 0x9
#define READ_CONFIG_DWORD 0xA
#define WRITE_CONFIG_BYTE 0xB
#define WRITE_CONFIG_WORD 0xC
#define WRITE_CONFIG_DWORD 0xD

/*
 * Under PCI, each device has 256 bytes of configuration address space,
 * of which the first 64 bytes are standardized as follows:
 */
 
#define PCI_VENDOR_ID		0x00	/* 16 bits */
#define PCI_DEVICE_ID		0x02	/* 16 bits */
#define PCI_COMMAND		0x04	/* 16 bits */
#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */

#define PCI_STATUS		0x06	/* 16 bits */
#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
#define  PCI_STATUS_DEVSEL_FAST	0x000	
#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
#define  PCI_STATUS_DEVSEL_SLOW 0x400
#define  PCI_STATUS_SIG_TARGET_ABORT 0x800  /* Set on target abort */
#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define  PCI_STATUS_DETECTED_PARITY 0x8000  /* Set on parity error */

#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
					   revision */
#define PCI_REVISION_ID         0x08    /* Revision ID */
#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE        0x0a    /* Device class */

#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
#define  PCI_HEADER_TYPE_NORMAL	0
#define  PCI_HEADER_TYPE_BRIDGE 1
#define  PCI_HEADER_TYPE_CARDBUS 2

#define PCI_BIST		0x0f	/* 8 bits */
#define PCI_BIST_CODE_MASK	0x0f	/* Return result */
#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */

/*
 * Base addresses specify locations in memory or I/O space.
 * Decoded size can be determined by writing a value of 
 * 0xffffffff to the register, and reading it back.  Only 
 * 1 bits are decoded.
 */
#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
#define  PCI_BASE_ADDRESS_SPACE	0x01	/* 0 = memory, 1 = I/O */
#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fUL)
#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03UL)
/* bit 1 is reserved if address_space = 1 */

/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS		0x28
#define PCI_SUBSYSTEM_VENDOR_ID	0x2c
#define PCI_SUBSYSTEM_ID	0x2e  
#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
#define  PCI_ROM_ADDRESS_ENABLE	0x01
#define PCI_ROM_ADDRESS_MASK	(~0x7ffUL)

#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */

/* 0x35-0x3b are reserved */
#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
#define PCI_MIN_GNT		0x3e	/* 8 bits */
#define PCI_MAX_LAT		0x3f	/* 8 bits */

/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
#define PCI_IO_LIMIT		0x1d
#define  PCI_IO_RANGE_TYPE_MASK	0x0fUL	/* I/O bridging type */
#define  PCI_IO_RANGE_TYPE_16	0x00
#define  PCI_IO_RANGE_TYPE_32	0x01
#define  PCI_IO_RANGE_MASK	(~0x0fUL)
#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
#define PCI_MEMORY_LIMIT	0x22
#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
#define  PCI_MEMORY_RANGE_MASK	(~0x0fUL)
#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT	0x26
#define  PCI_PREF_RANGE_TYPE_MASK 0x0fUL
#define  PCI_PREF_RANGE_TYPE_32	0x00
#define  PCI_PREF_RANGE_TYPE_64	0x01
#define  PCI_PREF_RANGE_MASK	(~0x0fUL)
#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32	0x2c
#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16	0x32
/* 0x34 same as for htype 0 */
/* 0x35-0x3b is reserved */
#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL	0x3e
#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
#define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
#define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
#define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */

/* Header type 2 (CardBus bridges) */
#define PCI_CB_CAPABILITY_LIST	0x14
/* 0x15 reserved */
#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_0	0x1c
#define PCI_CB_MEMORY_LIMIT_0	0x20
#define PCI_CB_MEMORY_BASE_1	0x24
#define PCI_CB_MEMORY_LIMIT_1	0x28
#define PCI_CB_IO_BASE_0	0x2c
#define PCI_CB_IO_BASE_0_HI	0x2e
#define PCI_CB_IO_LIMIT_0	0x30
#define PCI_CB_IO_LIMIT_0_HI	0x32
#define PCI_CB_IO_BASE_1	0x34
#define PCI_CB_IO_BASE_1_HI	0x36
#define PCI_CB_IO_LIMIT_1	0x38
#define PCI_CB_IO_LIMIT_1_HI	0x3a
#define  PCI_CB_IO_RANGE_MASK	(~0x03UL)
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL	0x3e
#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
#define  PCI_CB_BRIDGE_CTL_SERR		0x02
#define  PCI_CB_BRIDGE_CTL_ISA		0x04
#define  PCI_CB_BRIDGE_CTL_VGA		0x08
#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20
#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
#define PCI_CB_SUBSYSTEM_ID	0x42
#define PCI_CB_LEGACY_MODE_BASE	0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
/* 0x48-0x7f reserved */

/* Capability lists */

#define PCI_CAP_LIST_ID		0	/* Capability ID */
#define  PCI_CAP_ID_PM		0x01	/* Power Management */
#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF		4

/* Power Management Registers */

#define PCI_PM_PMC              2       /* PM Capabilities Register */
#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
#define  PCI_PM_CAP_AUX_POWER	0x01C0	/* Auxilliary power support mask */
#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
#define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
#define  PCI_PM_CAP_PME_MASK    0xF800  /* PME Mask of all supported states */
#define  PCI_PM_CAP_PME_D0      0x0800  /* PME# from D0 */
#define  PCI_PM_CAP_PME_D1      0x1000  /* PME# from D1 */
#define  PCI_PM_CAP_PME_D2      0x2000  /* PME# from D2 */
#define  PCI_PM_CAP_PME_D3      0x4000  /* PME# from D3 (hot) */
#define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
#define PCI_PM_CTRL		4	/* PM control and status register */
#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
#define PCI_PM_DATA_REGISTER	7	/* (??) */
#define PCI_PM_SIZEOF		8

/* AGP registers */

#define PCI_AGP_VERSION		2	/* BCD version number */
#define PCI_AGP_RFU		3	/* Rest of capability flags */
#define PCI_AGP_STATUS		4	/* Status register */
#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
#define PCI_AGP_COMMAND		8	/* Control register */
#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow processing of 64-bit addresses */
#define  PCI_AGP_COMMAND_FW	0x0010 	/* Force FW transfers */
#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate */
#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate */
#define PCI_AGP_SIZEOF		12

/* Slot Identification */

#define PCI_SID_ESR		2	/* Expansion Slot Register */
#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */

/* Message Signalled Interrupts registers */

#define PCI_MSI_FLAGS		2	/* Various flags */
#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
#define PCI_MSI_RFU		3	/* Rest of capability flags */
#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */

/* Include the ID list */

/*
 * The PCI interface treats multi-function devices as independent
 * devices.  The slot/function address of each device is encoded
 * in a single byte as follows:
 *
 *	7:3 = slot
 *	2:0 = function
 */
#define PCI_DEVFN(slot,func)	((((slot) & 0x1f) << 3) | ((func) & 0x07))
#define PCI_SLOT(devfn)		(((devfn) >> 3) & 0x1f)
#define PCI_FUNC(devfn)		((devfn) & 0x07)

#define PCI_ANY_ID (~0)


struct resource {
	unsigned int begin;
	unsigned int end;
};


/*
 * The pci_dev structure is used to describe both PCI and ISAPnP devices.
 */
struct pci_dev {
	unsigned int	dev;
	unsigned int    bus;
	unsigned short	vendor;
	unsigned short	device;
	unsigned short	class;		/* 3 bytes: (base2,sub,prog-if) */
	unsigned char   revision;
	struct resource resource[6];
	unsigned int    current_state;  /* Current operating state. In ACPI-speak,
					   this is D0-D3, D0 being fully functional,
					   and D3 being off. */

	char		name[80];	/* device name */
};

struct pci_device_id {
	unsigned int vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
	unsigned int subvendor, subdevice;	/* Subsystem ID's or PCI_ANY_ID */
	unsigned int class, class_mask;		/* (class,subclass,prog-if) triplet */
	unsigned long driver_data;		/* Data private to the driver */
};

typedef struct pci_device_s
{
    unsigned int ven_id;
    unsigned int id;
    char *name;
    char *description;
} pci_device;
 


typedef struct pci_class_s
{
    unsigned int id;
    char *name;
} pci_class;


typedef struct pci_vendor_s
{
    unsigned int id;
    char *shortname;
    char *name;
} pci_vendor;


typedef struct _pci_directory 
{
    char omagic[4];
    DWORD entrypoint;
    BYTE rev_level;
    BYTE length;
    BYTE checksum;
    BYTE reserved[5];
} pci_directory;

//this structure is used by DEX to make an indirect 32-bit FAR call
typedef struct __attribute__((packed)) _far_pointer 
{
    DWORD offset;
    WORD selector;
} far_pointer;


#include "pci_database.c"


far_pointer pcibiosentry;
far_pointer pcibios;

int pci_num=0;
struct pci_dev	*pci[32]={NULL,};
int pci_type=0;

#define PCI_CONF1_ADDRESS(dev, reg) \
	(0x80000000 | (dev << 11) | (reg & ~3))


extern DWORD pcibios_call(DWORD func_number);

extern int pci_finddevice(WORD deviceid,WORD vendorid, 
           WORD index,char *busnumber, WORD *devnumber);
extern int pci_findclass(WORD classcode, WORD index,char 
           *busnumber, WORD *devnumber);
           
extern int   pci_writeconfigdword(char bus, char devfunc, WORD register, DWORD data);
extern int   pci_writeconfigword(char bus, char devfunc, WORD register, WORD data);
extern int   pci_writeconfigbyte(char bus, char devfunc, WORD register, BYTE data);
extern DWORD pci_readconfigdword(char bus, char devfunc, WORD register);
extern WORD  pci_readconfigword(char bus, char devfunc, WORD register);
extern BYTE  pci_readconfigbyte(char bus, char devfunc, WORD register);

static unsigned int pci_size(unsigned int base, unsigned long mask)
{
	unsigned int size = mask & base;		/* Find the significant bits */
	size = size & ~(size-1);	/* Get the lowest of them to find the decode size */
	return size-1;			/* extent = size - 1 */
}

int pci_find_capability(int dev, int cap)
{
	unsigned short status;
	unsigned char pos, id;
	int ttl = 48;

	status = pci_readconfigword(0, dev << 3, PCI_STATUS);
	if (!(status & PCI_STATUS_CAP_LIST))
		return 0;

	pos = pci_readconfigbyte(0, dev << 3, PCI_CAPABILITY_LIST);

	while (ttl-- && pos >= 0x40) {
		pos &= ~3;
		id = pci_readconfigbyte(0, dev << 3, pos + PCI_CAP_LIST_ID);
		if (id == 0xff)
			break;
		if (id == cap)
		{
			return pos;
		}
		pos = pci_readconfigbyte(0, dev << 3, pos + PCI_CAP_LIST_NEXT);
	}
	return 0;
}

void pci_enable_device(struct pci_dev *dev)
{
	int pm = pci_find_capability(dev->dev, PCI_CAP_ID_PM);

	if(pm == 0) return; //brak obsługi PM
	
	// ustawiamy na D0
	pci_writeconfigword(0, dev->dev << 3, pm + PCI_PM_CTRL, 0);
	dev->current_state = 0;
}


void pci_detectdevices()
{
int index = 0, i;
    printf("Checking PCI device for Vendor ID...%d ",index);
    while (pci_devices[index].ven_id)
    {
        char bus,dev;
        DWORD begin, size;
        if (pci_finddevice(pci_devices[index].id, pci_devices[index].ven_id, 0,& bus, &dev) == 0)					 
                {
                    struct pci_dev *device;
                    device = malloc(sizeof(struct pci_dev));

                    pci[pci_num] = device;
                    device->class = pci_readconfigword(bus,dev,PCI_CLASS_DEVICE);
                    device->revision = pci_readconfigbyte(bus,dev,PCI_REVISION_ID);
                    device->current_state = 3;
                    device->dev = (dev >> 3);
                    device->vendor = pci_devices[index].ven_id;
                    device->device = pci_devices[index].id;
                    strcpy(device->name,pci_devices[index].name);
                    //configure device resource
                     for(i=0;i<6;i++)
                        {
                    	        begin = pci_readconfigdword(bus,dev, PCI_BASE_ADDRESS_0 + i * 4);
                            	pci_writeconfigdword(bus,dev, PCI_BASE_ADDRESS_0 + i * 4, 0xFFFFFFFF);
                            	size = pci_readconfigdword(bus,dev, PCI_BASE_ADDRESS_0 + i * 4);
                            	pci_writeconfigdword(bus,dev, PCI_BASE_ADDRESS_0 + i * 4, begin);
                            
                            	device->resource[i].begin = begin;
                            
                            	if (!size || size == 0xffffffff)
                            	{
                            	    device->resource[i].end=0;
                            	    continue;
                            	}
                            	if (begin == 0xffffffff)
                            	    begin = 0;
                            	if ((begin & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
                            	    device->resource[i].begin = begin & PCI_BASE_ADDRESS_MEM_MASK;
                            	    size = pci_size(size, PCI_BASE_ADDRESS_MEM_MASK);
                            	} 
                                       else 
                                {
                            	    device->resource[i].begin = begin & PCI_BASE_ADDRESS_IO_MASK;
                            	    size = pci_size(size, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
                            	}
                            	
                            	device->resource[i].end = device->resource[i].begin + (unsigned long) size;
                        }
                    
                   /**********For debugging purposes*************/         
                      printf("PCI: %s  dev: %d bus: %d\n", device->name, (unsigned int) device->dev, bus);		    
                      printf("     Vendor_ID: %04x, Device_ID: %04x, Class_ID: %x, Revision: %d\n", 
                      	device->vendor, device->device, device->class, device->revision);
                     /* for(i=0;i<6;i+=2)
                            {
                                printf("%d: 0x%04x - 0x%04x, %d: 0x%04x - 0x%04x\n",
                                    	i, device->resource[i].begin, device->resource[i].end,
                                    	i+1, device->resource[i+1].begin, device->resource[i+1].end);
                            }*/
                   /**********************************************/     
                    pci_num++;
                };
        index++;
    };
};

int detect_pci_bios()
{
    DWORD bios_location = 0xE0000,
          bios_end_location = 0xFFFFF;
    pci_directory *dir;
    do 
    {
    dir = (pci_directory*) bios_location;
    
    if (dir->omagic[0] == '_' &&
        dir->omagic[1] == '3' &&
        dir->omagic[2] == '2' &&
        dir->omagic[3] == '_')
        {
 
                printf("PCI Bios Service Directory detected at 0x%X\n",bios_location);
                pcibiosentry.offset = dir->entrypoint;
                pcibiosentry.selector = SYS_CODE_SEL;
                printf("Entrypoint detected at: 0x%X\n",pcibiosentry);
                pcibios.offset = pcibios_call(0x49435024);
                pcibios.selector = SYS_CODE_SEL;
                
                if (pcibios.offset==-1) return -1;
                                                
                printf("PCI bios entry is located at: 0x%x\n", pcibios.offset);
                return 1;
        };          
    bios_location ++;
    } while (bios_location < bios_end_location - 16);
    
    return -1;
};


//get the name of a vendor based on the vendor ID
const char *pci_getvendorname(int id)
{
    int i= 0;
    
    while (pci_vendors[i].id!=0)
        {
                if (pci_vendors[i].id == id)
                return pci_vendors[i].name;
                i++;
        };
    
    //this should return "Unknown"
    return pci_vendors[i].name;
};

void pci_sendmessage(int func, int data)
{
    if (func == DEVMGR_MESSAGESTR)
        {
                int i;
                printf("PCI bus driver for DEX-OS 1.0\n");
                printf("============Known PCI device listing================\n");
                
                for (i=0;i < pci_num ; i++)
                {
                      struct pci_dev *device = pci[i];          
                      printf("%-3d   %s  dev: %d bus: %d\n", i+1, device->name, (unsigned int) device->dev, 0);		    
                      printf("     Vendor_ID: %04x(%s), Device_ID: %04x, Class_ID: %x, Revision: %d\n", 
                       	      device->vendor, pci_getvendorname(device->vendor),
                              device->device, device->class, device->revision);

                };
                
        };    
};

#define PCI_IO_PORT 0xCF8

void init_pci(void)
{

    unsigned int tmp;
    devmgr_pci mypci;
    
    if (detect_pci_bios()!=-1)
        {
					printf("ASDASDASDASDASDASDASDADSADA");
                pci_detectdevices();
                /*Fill up the devmgr_pci structure*/
                mypci.hdr.size = sizeof(mypci);
                mypci.hdr.type = DEVMGR_PCI;
                strcpy(mypci.hdr.name,"pci_drv");
                strcpy(mypci.hdr.description,"DEX PCI/AGP bus driver");
                
                /*Fill up the public functions*/
                mypci.pci_readconfigbyte = pci_readconfigbyte;
                mypci.pci_readconfigword = pci_readconfigword;
                mypci.pci_readconfigdword = pci_readconfigdword;

                mypci.pci_writeconfigbyte = pci_readconfigbyte;
                mypci.pci_writeconfigword = pci_readconfigword;
                mypci.pci_writeconfigdword = pci_readconfigdword;

                mypci.pci_finddevice = pci_finddevice;
                mypci.pci_findclass = pci_findclass;
                mypci.hdr.sendmessage = pci_sendmessage;
                mypci.pci_init = 0;
                //Register this device to the device manager
                devmgr_register((devmgr_generic*) &mypci);
                
        };
        
    
    
}


