v2.0.0
Public Member Functions | Data Fields
m33_hw_t Struct Reference

## Public Member Functions
| _REG_ (M33_ITM_STIM0_OFFSET) io_rw_32 itm_stim[32]
| _REG_ (M33_ITM_TER0_OFFSET) io_rw_32 itm_ter0
| _REG_ (M33_ITM_TPR_OFFSET) io_rw_32 itm_tpr
| _REG_ (M33_ITM_TCR_OFFSET) io_rw_32 itm_tcr
| _REG_ (M33_INT_ATREADY_OFFSET) io_ro_32 int_atready
| _REG_ (M33_INT_ATVALID_OFFSET) io_rw_32 int_atvalid
| _REG_ (M33_ITM_ITCTRL_OFFSET) io_rw_32 itm_itctrl
| _REG_ (M33_ITM_DEVARCH_OFFSET) io_ro_32 itm_devarch
| _REG_ (M33_ITM_DEVTYPE_OFFSET) io_ro_32 itm_devtype
| _REG_ (M33_ITM_PIDR4_OFFSET) io_ro_32 itm_pidr4
| _REG_ (M33_ITM_PIDR5_OFFSET) io_rw_32 itm_pidr5
| _REG_ (M33_ITM_PIDR6_OFFSET) io_rw_32 itm_pidr6
| _REG_ (M33_ITM_PIDR7_OFFSET) io_rw_32 itm_pidr7
| _REG_ (M33_ITM_PIDR0_OFFSET) io_ro_32 itm_pidr0
| _REG_ (M33_ITM_PIDR1_OFFSET) io_ro_32 itm_pidr1
| _REG_ (M33_ITM_PIDR2_OFFSET) io_ro_32 itm_pidr2
| _REG_ (M33_ITM_PIDR3_OFFSET) io_ro_32 itm_pidr3
| _REG_ (M33_ITM_CIDR0_OFFSET) io_ro_32 itm_cidr[4]
| _REG_ (M33_DWT_CTRL_OFFSET) io_rw_32 dwt_ctrl
| _REG_ (M33_DWT_CYCCNT_OFFSET) io_rw_32 dwt_cyccnt
| _REG_ (M33_DWT_EXCCNT_OFFSET) io_rw_32 dwt_exccnt
| _REG_ (M33_DWT_LSUCNT_OFFSET) io_rw_32 dwt_lsucnt
| _REG_ (M33_DWT_FOLDCNT_OFFSET) io_rw_32 dwt_foldcnt
| _REG_ (M33_DWT_COMP0_OFFSET) io_rw_32 dwt_comp0
| _REG_ (M33_DWT_FUNCTION0_OFFSET) io_rw_32 dwt_function0
| _REG_ (M33_DWT_COMP1_OFFSET) io_rw_32 dwt_comp1
| _REG_ (M33_DWT_FUNCTION1_OFFSET) io_rw_32 dwt_function1
| _REG_ (M33_DWT_COMP2_OFFSET) io_rw_32 dwt_comp2
| _REG_ (M33_DWT_FUNCTION2_OFFSET) io_rw_32 dwt_function2
| _REG_ (M33_DWT_COMP3_OFFSET) io_rw_32 dwt_comp3
| _REG_ (M33_DWT_FUNCTION3_OFFSET) io_rw_32 dwt_function3
| _REG_ (M33_DWT_DEVARCH_OFFSET) io_ro_32 dwt_devarch
| _REG_ (M33_DWT_DEVTYPE_OFFSET) io_ro_32 dwt_devtype
| _REG_ (M33_DWT_PIDR4_OFFSET) io_ro_32 dwt_pidr4
| _REG_ (M33_DWT_PIDR5_OFFSET) io_rw_32 dwt_pidr5
| _REG_ (M33_DWT_PIDR6_OFFSET) io_rw_32 dwt_pidr6
| _REG_ (M33_DWT_PIDR7_OFFSET) io_rw_32 dwt_pidr7
| _REG_ (M33_DWT_PIDR0_OFFSET) io_ro_32 dwt_pidr0
| _REG_ (M33_DWT_PIDR1_OFFSET) io_ro_32 dwt_pidr1
| _REG_ (M33_DWT_PIDR2_OFFSET) io_ro_32 dwt_pidr2
| _REG_ (M33_DWT_PIDR3_OFFSET) io_ro_32 dwt_pidr3
| _REG_ (M33_DWT_CIDR0_OFFSET) io_ro_32 dwt_cidr[4]
| _REG_ (M33_FP_CTRL_OFFSET) io_rw_32 fp_ctrl
| _REG_ (M33_FP_REMAP_OFFSET) io_ro_32 fp_remap
| _REG_ (M33_FP_COMP0_OFFSET) io_rw_32 fp_comp[8]
| _REG_ (M33_FP_DEVARCH_OFFSET) io_ro_32 fp_devarch
| _REG_ (M33_FP_DEVTYPE_OFFSET) io_ro_32 fp_devtype
| _REG_ (M33_FP_PIDR4_OFFSET) io_ro_32 fp_pidr4
| _REG_ (M33_FP_PIDR5_OFFSET) io_rw_32 fp_pidr5
| _REG_ (M33_FP_PIDR6_OFFSET) io_rw_32 fp_pidr6
| _REG_ (M33_FP_PIDR7_OFFSET) io_rw_32 fp_pidr7
| _REG_ (M33_FP_PIDR0_OFFSET) io_ro_32 fp_pidr0
| _REG_ (M33_FP_PIDR1_OFFSET) io_ro_32 fp_pidr1
| _REG_ (M33_FP_PIDR2_OFFSET) io_ro_32 fp_pidr2
| _REG_ (M33_FP_PIDR3_OFFSET) io_ro_32 fp_pidr3
| _REG_ (M33_FP_CIDR0_OFFSET) io_ro_32 fp_cidr[4]
| _REG_ (M33_ICTR_OFFSET) io_ro_32 ictr
| _REG_ (M33_ACTLR_OFFSET) io_rw_32 actlr
| _REG_ (M33_SYST_CSR_OFFSET) io_rw_32 syst_csr
| _REG_ (M33_SYST_RVR_OFFSET) io_rw_32 syst_rvr
| _REG_ (M33_SYST_CVR_OFFSET) io_rw_32 syst_cvr
| _REG_ (M33_SYST_CALIB_OFFSET) io_ro_32 syst_calib
| _REG_ (M33_NVIC_ISER0_OFFSET) io_rw_32 nvic_iser[2]
| _REG_ (M33_NVIC_ICER0_OFFSET) io_rw_32 nvic_icer[2]
| _REG_ (M33_NVIC_ISPR0_OFFSET) io_rw_32 nvic_ispr[2]
| _REG_ (M33_NVIC_ICPR0_OFFSET) io_rw_32 nvic_icpr[2]
| _REG_ (M33_NVIC_IABR0_OFFSET) io_rw_32 nvic_iabr[2]
| _REG_ (M33_NVIC_ITNS0_OFFSET) io_rw_32 nvic_itns[2]
| _REG_ (M33_NVIC_IPR0_OFFSET) io_rw_32 nvic_ipr[16]
| _REG_ (M33_CPUID_OFFSET) io_ro_32 cpuid
| _REG_ (M33_ICSR_OFFSET) io_rw_32 icsr
| _REG_ (M33_VTOR_OFFSET) io_rw_32 vtor
| _REG_ (M33_AIRCR_OFFSET) io_rw_32 aircr
| _REG_ (M33_SCR_OFFSET) io_rw_32 scr
| _REG_ (M33_CCR_OFFSET) io_rw_32 ccr
| _REG_ (M33_SHPR1_OFFSET) io_rw_32 shpr[3]
| _REG_ (M33_SHCSR_OFFSET) io_rw_32 shcsr
| _REG_ (M33_CFSR_OFFSET) io_rw_32 cfsr
| _REG_ (M33_HFSR_OFFSET) io_rw_32 hfsr
| _REG_ (M33_DFSR_OFFSET) io_rw_32 dfsr
| _REG_ (M33_MMFAR_OFFSET) io_rw_32 mmfar
| _REG_ (M33_BFAR_OFFSET) io_rw_32 bfar
| _REG_ (M33_ID_PFR0_OFFSET) io_ro_32 id_pfr[2]
| _REG_ (M33_ID_DFR0_OFFSET) io_ro_32 id_dfr0
| _REG_ (M33_ID_AFR0_OFFSET) io_ro_32 id_afr0
| _REG_ (M33_ID_MMFR0_OFFSET) io_ro_32 id_mmfr[4]
| _REG_ (M33_ID_ISAR0_OFFSET) io_ro_32 id_isar[6]
| _REG_ (M33_CTR_OFFSET) io_ro_32 ctr
| _REG_ (M33_CPACR_OFFSET) io_rw_32 cpacr
| _REG_ (M33_NSACR_OFFSET) io_rw_32 nsacr
| _REG_ (M33_MPU_TYPE_OFFSET) io_ro_32 mpu_type
| _REG_ (M33_MPU_CTRL_OFFSET) io_rw_32 mpu_ctrl
| _REG_ (M33_MPU_RNR_OFFSET) io_rw_32 mpu_rnr
| _REG_ (M33_MPU_RBAR_OFFSET) io_rw_32 mpu_rbar
| _REG_ (M33_MPU_RLAR_OFFSET) io_rw_32 mpu_rlar
| _REG_ (M33_MPU_RBAR_A1_OFFSET) io_rw_32 mpu_rbar_a1
| _REG_ (M33_MPU_RLAR_A1_OFFSET) io_rw_32 mpu_rlar_a1
| _REG_ (M33_MPU_RBAR_A2_OFFSET) io_rw_32 mpu_rbar_a2
| _REG_ (M33_MPU_RLAR_A2_OFFSET) io_rw_32 mpu_rlar_a2
| _REG_ (M33_MPU_RBAR_A3_OFFSET) io_rw_32 mpu_rbar_a3
| _REG_ (M33_MPU_RLAR_A3_OFFSET) io_rw_32 mpu_rlar_a3
| _REG_ (M33_MPU_MAIR0_OFFSET) io_rw_32 mpu_mair[2]
| _REG_ (M33_SAU_CTRL_OFFSET) io_rw_32 sau_ctrl
| _REG_ (M33_SAU_TYPE_OFFSET) io_ro_32 sau_type
| _REG_ (M33_SAU_RNR_OFFSET) io_rw_32 sau_rnr
| _REG_ (M33_SAU_RBAR_OFFSET) io_rw_32 sau_rbar
| _REG_ (M33_SAU_RLAR_OFFSET) io_rw_32 sau_rlar
| _REG_ (M33_SFSR_OFFSET) io_rw_32 sfsr
| _REG_ (M33_SFAR_OFFSET) io_rw_32 sfar
| _REG_ (M33_DHCSR_OFFSET) io_rw_32 dhcsr
| _REG_ (M33_DCRSR_OFFSET) io_rw_32 dcrsr
| _REG_ (M33_DCRDR_OFFSET) io_rw_32 dcrdr
| _REG_ (M33_DEMCR_OFFSET) io_rw_32 demcr
| _REG_ (M33_DSCSR_OFFSET) io_rw_32 dscsr
| _REG_ (M33_STIR_OFFSET) io_rw_32 stir
| _REG_ (M33_FPCCR_OFFSET) io_rw_32 fpccr
| _REG_ (M33_FPCAR_OFFSET) io_rw_32 fpcar
| _REG_ (M33_FPDSCR_OFFSET) io_rw_32 fpdscr
| _REG_ (M33_MVFR0_OFFSET) io_ro_32 mvfr[3]
| _REG_ (M33_DDEVARCH_OFFSET) io_ro_32 ddevarch
| _REG_ (M33_DDEVTYPE_OFFSET) io_ro_32 ddevtype
| _REG_ (M33_DPIDR4_OFFSET) io_ro_32 dpidr4
| _REG_ (M33_DPIDR5_OFFSET) io_rw_32 dpidr5
| _REG_ (M33_DPIDR6_OFFSET) io_rw_32 dpidr6
| _REG_ (M33_DPIDR7_OFFSET) io_rw_32 dpidr7
| _REG_ (M33_DPIDR0_OFFSET) io_ro_32 dpidr0
| _REG_ (M33_DPIDR1_OFFSET) io_ro_32 dpidr1
| _REG_ (M33_DPIDR2_OFFSET) io_ro_32 dpidr2
| _REG_ (M33_DPIDR3_OFFSET) io_ro_32 dpidr3
| _REG_ (M33_DCIDR0_OFFSET) io_ro_32 dcidr[4]
| _REG_ (M33_TRCPRGCTLR_OFFSET) io_rw_32 trcprgctlr
| _REG_ (M33_TRCSTATR_OFFSET) io_ro_32 trcstatr
| _REG_ (M33_TRCCONFIGR_OFFSET) io_rw_32 trcconfigr
| _REG_ (M33_TRCEVENTCTL0R_OFFSET) io_rw_32 trceventctl0r
| _REG_ (M33_TRCEVENTCTL1R_OFFSET) io_rw_32 trceventctl1r
| _REG_ (M33_TRCSTALLCTLR_OFFSET) io_rw_32 trcstallctlr
| _REG_ (M33_TRCTSCTLR_OFFSET) io_rw_32 trctsctlr
| _REG_ (M33_TRCSYNCPR_OFFSET) io_ro_32 trcsyncpr
| _REG_ (M33_TRCCCCTLR_OFFSET) io_rw_32 trcccctlr
| _REG_ (M33_TRCVICTLR_OFFSET) io_rw_32 trcvictlr
| _REG_ (M33_TRCCNTRLDVR0_OFFSET) io_rw_32 trccntrldvr0
| _REG_ (M33_TRCIDR8_OFFSET) io_ro_32 trcidr8
| _REG_ (M33_TRCIDR9_OFFSET) io_ro_32 trcidr9
| _REG_ (M33_TRCIDR10_OFFSET) io_ro_32 trcidr10
| _REG_ (M33_TRCIDR11_OFFSET) io_ro_32 trcidr11
| _REG_ (M33_TRCIDR12_OFFSET) io_ro_32 trcidr12
| _REG_ (M33_TRCIDR13_OFFSET) io_ro_32 trcidr13
| _REG_ (M33_TRCIMSPEC_OFFSET) io_ro_32 trcimspec
| _REG_ (M33_TRCIDR0_OFFSET) io_ro_32 trcidr0
| _REG_ (M33_TRCIDR1_OFFSET) io_ro_32 trcidr1
| _REG_ (M33_TRCIDR2_OFFSET) io_ro_32 trcidr2
| _REG_ (M33_TRCIDR3_OFFSET) io_ro_32 trcidr3
| _REG_ (M33_TRCIDR4_OFFSET) io_ro_32 trcidr4
| _REG_ (M33_TRCIDR5_OFFSET) io_ro_32 trcidr5
| _REG_ (M33_TRCIDR6_OFFSET) io_rw_32 trcidr6
| _REG_ (M33_TRCIDR7_OFFSET) io_rw_32 trcidr7
| _REG_ (M33_TRCRSCTLR2_OFFSET) io_rw_32 trcrsctlr[2]
| _REG_ (M33_TRCSSCSR_OFFSET) io_rw_32 trcsscsr
| _REG_ (M33_TRCSSPCICR_OFFSET) io_rw_32 trcsspcicr
| _REG_ (M33_TRCPDCR_OFFSET) io_rw_32 trcpdcr
| _REG_ (M33_TRCPDSR_OFFSET) io_ro_32 trcpdsr
| _REG_ (M33_TRCITATBIDR_OFFSET) io_rw_32 trcitatbidr
| _REG_ (M33_TRCITIATBINR_OFFSET) io_rw_32 trcitiatbinr
| _REG_ (M33_TRCITIATBOUTR_OFFSET) io_rw_32 trcitiatboutr
| _REG_ (M33_TRCCLAIMSET_OFFSET) io_rw_32 trcclaimset
| _REG_ (M33_TRCCLAIMCLR_OFFSET) io_rw_32 trcclaimclr
| _REG_ (M33_TRCAUTHSTATUS_OFFSET) io_ro_32 trcauthstatus
| _REG_ (M33_TRCDEVARCH_OFFSET) io_ro_32 trcdevarch
| _REG_ (M33_TRCDEVID_OFFSET) io_rw_32 trcdevid
| _REG_ (M33_TRCDEVTYPE_OFFSET) io_ro_32 trcdevtype
| _REG_ (M33_TRCPIDR4_OFFSET) io_ro_32 trcpidr4
| _REG_ (M33_TRCPIDR5_OFFSET) io_rw_32 trcpidr5
| _REG_ (M33_TRCPIDR6_OFFSET) io_rw_32 trcpidr6
| _REG_ (M33_TRCPIDR7_OFFSET) io_rw_32 trcpidr7
| _REG_ (M33_TRCPIDR0_OFFSET) io_ro_32 trcpidr0
| _REG_ (M33_TRCPIDR1_OFFSET) io_ro_32 trcpidr1
| _REG_ (M33_TRCPIDR2_OFFSET) io_ro_32 trcpidr2
| _REG_ (M33_TRCPIDR3_OFFSET) io_ro_32 trcpidr3
| _REG_ (M33_TRCCIDR0_OFFSET) io_ro_32 trccidr[4]
| _REG_ (M33_CTICONTROL_OFFSET) io_rw_32 cticontrol
| _REG_ (M33_CTIINTACK_OFFSET) io_rw_32 ctiintack
| _REG_ (M33_CTIAPPSET_OFFSET) io_rw_32 ctiappset
| _REG_ (M33_CTIAPPCLEAR_OFFSET) io_rw_32 ctiappclear
| _REG_ (M33_CTIAPPPULSE_OFFSET) io_rw_32 ctiapppulse
| _REG_ (M33_CTIINEN0_OFFSET) io_rw_32 ctiinen[8]
| _REG_ (M33_CTIOUTEN0_OFFSET) io_rw_32 ctiouten[8]
| _REG_ (M33_CTITRIGINSTATUS_OFFSET) io_ro_32 ctitriginstatus
| _REG_ (M33_CTITRIGOUTSTATUS_OFFSET) io_ro_32 ctitrigoutstatus
| _REG_ (M33_CTICHINSTATUS_OFFSET) io_ro_32 ctichinstatus
| _REG_ (M33_CTIGATE_OFFSET) io_rw_32 ctigate
| _REG_ (M33_ASICCTL_OFFSET) io_rw_32 asicctl
| _REG_ (M33_ITCHOUT_OFFSET) io_rw_32 itchout
| _REG_ (M33_ITTRIGOUT_OFFSET) io_rw_32 ittrigout
| _REG_ (M33_ITCHIN_OFFSET) io_ro_32 itchin
| _REG_ (M33_ITCTRL_OFFSET) io_rw_32 itctrl
| _REG_ (M33_DEVARCH_OFFSET) io_ro_32 devarch
| _REG_ (M33_DEVID_OFFSET) io_ro_32 devid
| _REG_ (M33_DEVTYPE_OFFSET) io_ro_32 devtype
| _REG_ (M33_PIDR4_OFFSET) io_ro_32 pidr4
| _REG_ (M33_PIDR5_OFFSET) io_rw_32 pidr5
| _REG_ (M33_PIDR6_OFFSET) io_rw_32 pidr6
| _REG_ (M33_PIDR7_OFFSET) io_rw_32 pidr7
| _REG_ (M33_PIDR0_OFFSET) io_ro_32 pidr0
| _REG_ (M33_PIDR1_OFFSET) io_ro_32 pidr1
| _REG_ (M33_PIDR2_OFFSET) io_ro_32 pidr2
| _REG_ (M33_PIDR3_OFFSET) io_ro_32 pidr3
| _REG_ (M33_CIDR0_OFFSET) io_ro_32 cidr[4]

## Data Fields
uint32_t | _pad0 [864]
uint32_t | _pad1 [15]
uint32_t | _pad2 [15]
uint32_t | _pad3 [27]
uint32_t | _pad4
uint32_t | _pad5
uint32_t | _pad6 [46]
uint32_t | _pad7 [3]
uint32_t | _pad8
uint32_t | _pad9
uint32_t | _pad10
uint32_t | _pad11
uint32_t | _pad12
uint32_t | _pad13
uint32_t | _pad14
uint32_t | _pad15
uint32_t | _pad16
uint32_t | _pad17
uint32_t | _pad18 [984]
uint32_t | _pad19 [3]
uint32_t | _pad20 [997]
uint32_t | _pad21 [3]
uint32_t | _pad22 [11265]
uint32_t | _pad23
uint32_t | _pad24 [56]
uint32_t | _pad25 [30]
uint32_t | _pad26 [30]
uint32_t | _pad27 [30]
uint32_t | _pad28 [30]
uint32_t | _pad29 [30]
uint32_t | _pad30 [30]
uint32_t | _pad31 [560]
uint32_t | _pad32
uint32_t | _pad33
uint32_t | _pad34 [2]
uint32_t | _pad35
uint32_t | _pad36 [2]
uint32_t | _pad37
uint32_t | _pad38 [2]
uint32_t | _pad39 [61]
uint32_t | _pad40 [12]
uint32_t | _pad41 [28]
uint32_t | _pad42 [3]
uint32_t | _pad43 [51201]
uint32_t | _pad44
uint32_t | _pad45 [3]
uint32_t | _pad46
uint32_t | _pad47 [17]
uint32_t | _pad48 [47]
uint32_t | _pad49 [15]
uint32_t | _pad50 [10]
uint32_t | _pad51 [7]
uint32_t | _pad52 [2]
uint32_t | _pad53 [36]
uint32_t | _pad54 [7]
uint32_t | _pad55 [19]
uint32_t | _pad56 [755]
uint32_t | _pad57 [3]
uint32_t | _pad58
uint32_t | _pad59 [40]
uint32_t | _pad60 [4]
uint32_t | _pad61 [2]
uint32_t | _pad62 [3]
uint32_t | _pad63 [24]
uint32_t | _pad64 [28]
uint32_t | _pad65
uint32_t | _pad66 [871]
uint32_t | _pad67 [2]
uint32_t | _pad68 [2]
uint32_t | _pad69 [46]
uint32_t | _pad70 [2]

The documentation for this struct was generated from the following file:

- include/hardware/structs/m33.h