v2.0.0
clocks.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_CLOCKS_H
9#define _HARDWARE_STRUCTS_CLOCKS_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/clocks.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_clocks
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
30 typedef enum clock_num_rp2350 {
31 clk_gpout0 = 0,
32 clk_gpout1 = 1,
33 clk_gpout2 = 2,
34 clk_gpout3 = 3,
35 clk_ref = 4,
36 clk_sys = 5,
37 clk_peri = 6,
38 clk_hstx = 7,
39 clk_usb = 8,
40 clk_adc = 9,
41 CLK_COUNT
42} clock_num_t;
44
48 typedef enum clock_dest_num_rp2350 {
49 CLK_DEST_SYS_CLOCKS = 0,
50 CLK_DEST_SYS_ACCESSCTRL = 1,
51 CLK_DEST_ADC = 2,
52 CLK_DEST_SYS_ADC = 3,
53 CLK_DEST_SYS_BOOTRAM = 4,
54 CLK_DEST_SYS_BUSCTRL = 5,
55 CLK_DEST_SYS_BUSFABRIC = 6,
56 CLK_DEST_SYS_DMA = 7,
57 CLK_DEST_SYS_GLITCH_DETECTOR = 8,
58 CLK_DEST_HSTX = 9,
59 CLK_DEST_SYS_HSTX = 10,
60 CLK_DEST_SYS_I2C0 = 11,
61 CLK_DEST_SYS_I2C1 = 12,
62 CLK_DEST_SYS_IO = 13,
63 CLK_DEST_SYS_JTAG = 14,
64 CLK_DEST_REF_OTP = 15,
65 CLK_DEST_SYS_OTP = 16,
66 CLK_DEST_SYS_PADS = 17,
67 CLK_DEST_SYS_PIO0 = 18,
68 CLK_DEST_SYS_PIO1 = 19,
69 CLK_DEST_SYS_PIO2 = 20,
70 CLK_DEST_SYS_PLL_SYS = 21,
71 CLK_DEST_SYS_PLL_USB = 22,
72 CLK_DEST_REF_POWMAN = 23,
73 CLK_DEST_SYS_POWMAN = 24,
74 CLK_DEST_SYS_PWM = 25,
75 CLK_DEST_SYS_RESETS = 26,
76 CLK_DEST_SYS_ROM = 27,
77 CLK_DEST_SYS_ROSC = 28,
78 CLK_DEST_SYS_PSM = 29,
79 CLK_DEST_SYS_SHA256 = 30,
80 CLK_DEST_SYS_SIO = 31,
81 CLK_DEST_PERI_SPI0 = 32,
82 CLK_DEST_SYS_SPI0 = 33,
83 CLK_DEST_PERI_SPI1 = 34,
84 CLK_DEST_SYS_SPI1 = 35,
85 CLK_DEST_SYS_SRAM0 = 36,
86 CLK_DEST_SYS_SRAM1 = 37,
87 CLK_DEST_SYS_SRAM2 = 38,
88 CLK_DEST_SYS_SRAM3 = 39,
89 CLK_DEST_SYS_SRAM4 = 40,
90 CLK_DEST_SYS_SRAM5 = 41,
91 CLK_DEST_SYS_SRAM6 = 42,
92 CLK_DEST_SYS_SRAM7 = 43,
93 CLK_DEST_SYS_SRAM8 = 44,
94 CLK_DEST_SYS_SRAM9 = 45,
95 CLK_DEST_SYS_SYSCFG = 46,
96 CLK_DEST_SYS_SYSINFO = 47,
97 CLK_DEST_SYS_TBMAN = 48,
98 CLK_DEST_REF_TICKS = 49,
99 CLK_DEST_SYS_TICKS = 50,
100 CLK_DEST_SYS_TIMER0 = 51,
101 CLK_DEST_SYS_TIMER1 = 52,
102 CLK_DEST_SYS_TRNG = 53,
103 CLK_DEST_PERI_UART0 = 54,
104 CLK_DEST_SYS_UART0 = 55,
105 CLK_DEST_PERI_UART1 = 56,
106 CLK_DEST_SYS_UART1 = 57,
107 CLK_DEST_SYS_USBCTRL = 58,
108 CLK_DEST_USB = 59,
109 CLK_DEST_SYS_WATCHDOG = 60,
110 CLK_DEST_SYS_XIP = 61,
111 CLK_DEST_SYS_XOSC = 62,
112 NUM_CLOCK_DESTINATIONS
113} clock_dest_num_t;
114
116typedef struct {
117 _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
118 // Clock control, can be changed on-the-fly (except for auxsrc)
119 // 0x10000000 [28] ENABLED (0) clock generator is enabled
120 // 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by...
121 // 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the...
122 // 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors, can be...
123 // 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly
124 // 0x00000400 [10] KILL (0) Asynchronously kills the clock generator, enable must be...
125 // 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching
126 io_rw_32 ctrl;
127
128 _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
129 // 0xffff0000 [31:16] INT (0x0001) Integer part of clock divisor, 0 -> max+1, can be...
130 // 0x0000ffff [15:0] FRAC (0x0000) Fractional component of the divisor, can be changed on-the-fly
131 io_rw_32 div;
132
133 _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
134 // Indicates which src is currently selected (one-hot)
135 // 0x00000001 [0] CLK_GPOUT0_SELECTED (1) This slice does not have a glitchless mux (only the...
136 io_ro_32 selected;
137} clock_hw_t;
139
140typedef struct {
141 _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
142 // 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it...
143 // 0x00001000 [12] FRCE (0) Force a resus, for test purposes only
144 // 0x00000100 [8] ENABLE (0) Enable resus
145 // 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles +
146 io_rw_32 ctrl;
147
148 _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
149 // 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send...
150 io_ro_32 status;
151} clock_resus_hw_t;
152
153typedef struct {
154 _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
155 // Reference clock frequency in kHz
156 // 0x000fffff [19:0] FC0_REF_KHZ (0x00000)
157 io_rw_32 ref_khz;
158
159 _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
160 // Minimum pass frequency in kHz
161 // 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000)
162 io_rw_32 min_khz;
163
164 _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
165 // Maximum pass frequency in kHz
166 // 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff)
167 io_rw_32 max_khz;
168
169 _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
170 // Delays the start of frequency counting to allow the mux to settle +
171 // 0x00000007 [2:0] FC0_DELAY (0x1)
172 io_rw_32 delay;
173
174 _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
175 // The test interval is 0
176 // 0x0000000f [3:0] FC0_INTERVAL (0x8)
177 io_rw_32 interval;
178
179 _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
180 // Clock sent to frequency counter, set to 0 when not required +
181 // 0x000000ff [7:0] FC0_SRC (0x00)
182 io_rw_32 src;
183
184 _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
185 // Frequency counter status
186 // 0x10000000 [28] DIED (0) Test clock stopped during test
187 // 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1
188 // 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1
189 // 0x00010000 [16] FAIL (0) Test failed
190 // 0x00001000 [12] WAITING (0) Waiting for test clock to start
191 // 0x00000100 [8] RUNNING (0) Test running
192 // 0x00000010 [4] DONE (0) Test complete
193 // 0x00000001 [0] PASS (0) Test passed
194 io_ro_32 status;
195
196 _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
197 // Result of frequency measurement, only valid when status_done=1
198 // 0x3fffffe0 [29:5] KHZ (0x0000000)
199 // 0x0000001f [4:0] FRAC (0x00)
200 io_ro_32 result;
201} fc_hw_t;
202
203typedef struct {
204 clock_hw_t clk[10];
205
206 _REG_(CLOCKS_DFTCLK_XOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_XOSC_CTRL
207 // 0x00000003 [1:0] SRC (0x0)
208 io_rw_32 dftclk_xosc_ctrl;
209
210 _REG_(CLOCKS_DFTCLK_ROSC_CTRL_OFFSET) // CLOCKS_DFTCLK_ROSC_CTRL
211 // 0x00000003 [1:0] SRC (0x0)
212 io_rw_32 dftclk_rosc_ctrl;
213
214 _REG_(CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_LPOSC_CTRL
215 // 0x00000003 [1:0] SRC (0x0)
216 io_rw_32 dftclk_lposc_ctrl;
217
218 clock_resus_hw_t resus;
219
220 fc_hw_t fc0;
221
222 union {
223 struct {
224 _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
225 // enable clock in wake mode
226 // 0x80000000 [31] CLK_SYS_SIOB (1)
227 // 0x40000000 [30] CLK_SYS_SHA256 (1)
228 // 0x20000000 [29] CLK_SYS_RSM (1)
229 // 0x10000000 [28] CLK_SYS_ROSC (1)
230 // 0x08000000 [27] CLK_SYS_ROM (1)
231 // 0x04000000 [26] CLK_SYS_RESETS (1)
232 // 0x02000000 [25] CLK_SYS_PWM (1)
233 // 0x01000000 [24] CLK_SYS_POWMAN (1)
234 // 0x00800000 [23] CLK_REF_POWMAN (1)
235 // 0x00400000 [22] CLK_SYS_PLL_USB (1)
236 // 0x00200000 [21] CLK_SYS_PLL_SYS (1)
237 // 0x00100000 [20] CLK_SYS_PIO2 (1)
238 // 0x00080000 [19] CLK_SYS_PIO1 (1)
239 // 0x00040000 [18] CLK_SYS_PIO0 (1)
240 // 0x00020000 [17] CLK_SYS_PADS (1)
241 // 0x00010000 [16] CLK_SYS_OTP (1)
242 // 0x00008000 [15] CLK_REF_OTP (1)
243 // 0x00004000 [14] CLK_SYS_JTAG (1)
244 // 0x00002000 [13] CLK_SYS_IO (1)
245 // 0x00001000 [12] CLK_SYS_I2C1 (1)
246 // 0x00000800 [11] CLK_SYS_I2C0 (1)
247 // 0x00000400 [10] CLK_SYS_HSTX (1)
248 // 0x00000200 [9] CLK_HSTX (1)
249 // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1)
250 // 0x00000080 [7] CLK_SYS_DMA (1)
251 // 0x00000040 [6] CLK_SYS_BUSFABRIC (1)
252 // 0x00000020 [5] CLK_SYS_BUSCTRL (1)
253 // 0x00000010 [4] CLK_SYS_BOOTRAM (1)
254 // 0x00000008 [3] CLK_SYS_ADC (1)
255 // 0x00000004 [2] CLK_ADC (1)
256 // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1)
257 // 0x00000001 [0] CLK_SYS_CLOCKS (1)
258 io_rw_32 wake_en0;
259
260 _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
261 // enable clock in wake mode
262 // 0x40000000 [30] CLK_SYS_XOSC (1)
263 // 0x20000000 [29] CLK_SYS_XIP (1)
264 // 0x10000000 [28] CLK_SYS_WATCHDOG (1)
265 // 0x08000000 [27] CLK_USB (1)
266 // 0x04000000 [26] CLK_SYS_USBCTRL (1)
267 // 0x02000000 [25] CLK_SYS_UART1 (1)
268 // 0x01000000 [24] CLK_PERI_UART1 (1)
269 // 0x00800000 [23] CLK_SYS_UART0 (1)
270 // 0x00400000 [22] CLK_PERI_UART0 (1)
271 // 0x00200000 [21] CLK_SYS_TRNG (1)
272 // 0x00100000 [20] CLK_SYS_TIMER1 (1)
273 // 0x00080000 [19] CLK_SYS_TIMER0 (1)
274 // 0x00040000 [18] CLK_SYS_TICKS (1)
275 // 0x00020000 [17] CLK_REF_TICKS (1)
276 // 0x00010000 [16] CLK_SYS_TBMAN (1)
277 // 0x00008000 [15] CLK_SYS_SYSINFO (1)
278 // 0x00004000 [14] CLK_SYS_SYSCFG (1)
279 // 0x00002000 [13] CLK_SYS_SRAM9 (1)
280 // 0x00001000 [12] CLK_SYS_SRAM8 (1)
281 // 0x00000800 [11] CLK_SYS_SRAM7 (1)
282 // 0x00000400 [10] CLK_SYS_SRAM6 (1)
283 // 0x00000200 [9] CLK_SYS_SRAM5 (1)
284 // 0x00000100 [8] CLK_SYS_SRAM4 (1)
285 // 0x00000080 [7] CLK_SYS_SRAM3 (1)
286 // 0x00000040 [6] CLK_SYS_SRAM2 (1)
287 // 0x00000020 [5] CLK_SYS_SRAM1 (1)
288 // 0x00000010 [4] CLK_SYS_SRAM0 (1)
289 // 0x00000008 [3] CLK_SYS_SPI1 (1)
290 // 0x00000004 [2] CLK_PERI_SPI1 (1)
291 // 0x00000002 [1] CLK_SYS_SPI0 (1)
292 // 0x00000001 [0] CLK_PERI_SPI0 (1)
293 io_rw_32 wake_en1;
294 };
295 // (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes)
296 _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
297 // enable clock in wake mode
298 // 0x80000000 [31] CLK_SYS_SIO (1)
299 // 0x40000000 [30] CLK_SYS_SHA256 (1)
300 // 0x20000000 [29] CLK_SYS_PSM (1)
301 // 0x10000000 [28] CLK_SYS_ROSC (1)
302 // 0x08000000 [27] CLK_SYS_ROM (1)
303 // 0x04000000 [26] CLK_SYS_RESETS (1)
304 // 0x02000000 [25] CLK_SYS_PWM (1)
305 // 0x01000000 [24] CLK_SYS_POWMAN (1)
306 // 0x00800000 [23] CLK_REF_POWMAN (1)
307 // 0x00400000 [22] CLK_SYS_PLL_USB (1)
308 // 0x00200000 [21] CLK_SYS_PLL_SYS (1)
309 // 0x00100000 [20] CLK_SYS_PIO2 (1)
310 // 0x00080000 [19] CLK_SYS_PIO1 (1)
311 // 0x00040000 [18] CLK_SYS_PIO0 (1)
312 // 0x00020000 [17] CLK_SYS_PADS (1)
313 // 0x00010000 [16] CLK_SYS_OTP (1)
314 // 0x00008000 [15] CLK_REF_OTP (1)
315 // 0x00004000 [14] CLK_SYS_JTAG (1)
316 // 0x00002000 [13] CLK_SYS_IO (1)
317 // 0x00001000 [12] CLK_SYS_I2C1 (1)
318 // 0x00000800 [11] CLK_SYS_I2C0 (1)
319 // 0x00000400 [10] CLK_SYS_HSTX (1)
320 // 0x00000200 [9] CLK_HSTX (1)
321 // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1)
322 // 0x00000080 [7] CLK_SYS_DMA (1)
323 // 0x00000040 [6] CLK_SYS_BUSFABRIC (1)
324 // 0x00000020 [5] CLK_SYS_BUSCTRL (1)
325 // 0x00000010 [4] CLK_SYS_BOOTRAM (1)
326 // 0x00000008 [3] CLK_SYS_ADC (1)
327 // 0x00000004 [2] CLK_ADC (1)
328 // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1)
329 // 0x00000001 [0] CLK_SYS_CLOCKS (1)
330 io_rw_32 wake_en[2];
331 };
332
333 union {
334 struct {
335 _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
336 // enable clock in sleep mode
337 // 0x80000000 [31] CLK_SYS_SIOB (1)
338 // 0x40000000 [30] CLK_SYS_SHA256 (1)
339 // 0x20000000 [29] CLK_SYS_RSM (1)
340 // 0x10000000 [28] CLK_SYS_ROSC (1)
341 // 0x08000000 [27] CLK_SYS_ROM (1)
342 // 0x04000000 [26] CLK_SYS_RESETS (1)
343 // 0x02000000 [25] CLK_SYS_PWM (1)
344 // 0x01000000 [24] CLK_SYS_POWMAN (1)
345 // 0x00800000 [23] CLK_REF_POWMAN (1)
346 // 0x00400000 [22] CLK_SYS_PLL_USB (1)
347 // 0x00200000 [21] CLK_SYS_PLL_SYS (1)
348 // 0x00100000 [20] CLK_SYS_PIO2 (1)
349 // 0x00080000 [19] CLK_SYS_PIO1 (1)
350 // 0x00040000 [18] CLK_SYS_PIO0 (1)
351 // 0x00020000 [17] CLK_SYS_PADS (1)
352 // 0x00010000 [16] CLK_SYS_OTP (1)
353 // 0x00008000 [15] CLK_REF_OTP (1)
354 // 0x00004000 [14] CLK_SYS_JTAG (1)
355 // 0x00002000 [13] CLK_SYS_IO (1)
356 // 0x00001000 [12] CLK_SYS_I2C1 (1)
357 // 0x00000800 [11] CLK_SYS_I2C0 (1)
358 // 0x00000400 [10] CLK_SYS_HSTX (1)
359 // 0x00000200 [9] CLK_HSTX (1)
360 // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1)
361 // 0x00000080 [7] CLK_SYS_DMA (1)
362 // 0x00000040 [6] CLK_SYS_BUSFABRIC (1)
363 // 0x00000020 [5] CLK_SYS_BUSCTRL (1)
364 // 0x00000010 [4] CLK_SYS_BOOTRAM (1)
365 // 0x00000008 [3] CLK_SYS_ADC (1)
366 // 0x00000004 [2] CLK_ADC (1)
367 // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1)
368 // 0x00000001 [0] CLK_SYS_CLOCKS (1)
369 io_rw_32 sleep_en0;
370
371 _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
372 // enable clock in sleep mode
373 // 0x40000000 [30] CLK_SYS_XOSC (1)
374 // 0x20000000 [29] CLK_SYS_XIP (1)
375 // 0x10000000 [28] CLK_SYS_WATCHDOG (1)
376 // 0x08000000 [27] CLK_USB (1)
377 // 0x04000000 [26] CLK_SYS_USBCTRL (1)
378 // 0x02000000 [25] CLK_SYS_UART1 (1)
379 // 0x01000000 [24] CLK_PERI_UART1 (1)
380 // 0x00800000 [23] CLK_SYS_UART0 (1)
381 // 0x00400000 [22] CLK_PERI_UART0 (1)
382 // 0x00200000 [21] CLK_SYS_TRNG (1)
383 // 0x00100000 [20] CLK_SYS_TIMER1 (1)
384 // 0x00080000 [19] CLK_SYS_TIMER0 (1)
385 // 0x00040000 [18] CLK_SYS_TICKS (1)
386 // 0x00020000 [17] CLK_REF_TICKS (1)
387 // 0x00010000 [16] CLK_SYS_TBMAN (1)
388 // 0x00008000 [15] CLK_SYS_SYSINFO (1)
389 // 0x00004000 [14] CLK_SYS_SYSCFG (1)
390 // 0x00002000 [13] CLK_SYS_SRAM9 (1)
391 // 0x00001000 [12] CLK_SYS_SRAM8 (1)
392 // 0x00000800 [11] CLK_SYS_SRAM7 (1)
393 // 0x00000400 [10] CLK_SYS_SRAM6 (1)
394 // 0x00000200 [9] CLK_SYS_SRAM5 (1)
395 // 0x00000100 [8] CLK_SYS_SRAM4 (1)
396 // 0x00000080 [7] CLK_SYS_SRAM3 (1)
397 // 0x00000040 [6] CLK_SYS_SRAM2 (1)
398 // 0x00000020 [5] CLK_SYS_SRAM1 (1)
399 // 0x00000010 [4] CLK_SYS_SRAM0 (1)
400 // 0x00000008 [3] CLK_SYS_SPI1 (1)
401 // 0x00000004 [2] CLK_PERI_SPI1 (1)
402 // 0x00000002 [1] CLK_SYS_SPI0 (1)
403 // 0x00000001 [0] CLK_PERI_SPI0 (1)
404 io_rw_32 sleep_en1;
405 };
406 // (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes)
407 _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
408 // enable clock in sleep mode
409 // 0x80000000 [31] CLK_SYS_SIO (1)
410 // 0x40000000 [30] CLK_SYS_SHA256 (1)
411 // 0x20000000 [29] CLK_SYS_PSM (1)
412 // 0x10000000 [28] CLK_SYS_ROSC (1)
413 // 0x08000000 [27] CLK_SYS_ROM (1)
414 // 0x04000000 [26] CLK_SYS_RESETS (1)
415 // 0x02000000 [25] CLK_SYS_PWM (1)
416 // 0x01000000 [24] CLK_SYS_POWMAN (1)
417 // 0x00800000 [23] CLK_REF_POWMAN (1)
418 // 0x00400000 [22] CLK_SYS_PLL_USB (1)
419 // 0x00200000 [21] CLK_SYS_PLL_SYS (1)
420 // 0x00100000 [20] CLK_SYS_PIO2 (1)
421 // 0x00080000 [19] CLK_SYS_PIO1 (1)
422 // 0x00040000 [18] CLK_SYS_PIO0 (1)
423 // 0x00020000 [17] CLK_SYS_PADS (1)
424 // 0x00010000 [16] CLK_SYS_OTP (1)
425 // 0x00008000 [15] CLK_REF_OTP (1)
426 // 0x00004000 [14] CLK_SYS_JTAG (1)
427 // 0x00002000 [13] CLK_SYS_IO (1)
428 // 0x00001000 [12] CLK_SYS_I2C1 (1)
429 // 0x00000800 [11] CLK_SYS_I2C0 (1)
430 // 0x00000400 [10] CLK_SYS_HSTX (1)
431 // 0x00000200 [9] CLK_HSTX (1)
432 // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1)
433 // 0x00000080 [7] CLK_SYS_DMA (1)
434 // 0x00000040 [6] CLK_SYS_BUSFABRIC (1)
435 // 0x00000020 [5] CLK_SYS_BUSCTRL (1)
436 // 0x00000010 [4] CLK_SYS_BOOTRAM (1)
437 // 0x00000008 [3] CLK_SYS_ADC (1)
438 // 0x00000004 [2] CLK_ADC (1)
439 // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1)
440 // 0x00000001 [0] CLK_SYS_CLOCKS (1)
441 io_rw_32 sleep_en[2];
442 };
443
444 union {
445 struct {
446 _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
447 // indicates the state of the clock enable
448 // 0x80000000 [31] CLK_SYS_SIOB (0)
449 // 0x40000000 [30] CLK_SYS_SHA256 (0)
450 // 0x20000000 [29] CLK_SYS_RSM (0)
451 // 0x10000000 [28] CLK_SYS_ROSC (0)
452 // 0x08000000 [27] CLK_SYS_ROM (0)
453 // 0x04000000 [26] CLK_SYS_RESETS (0)
454 // 0x02000000 [25] CLK_SYS_PWM (0)
455 // 0x01000000 [24] CLK_SYS_POWMAN (0)
456 // 0x00800000 [23] CLK_REF_POWMAN (0)
457 // 0x00400000 [22] CLK_SYS_PLL_USB (0)
458 // 0x00200000 [21] CLK_SYS_PLL_SYS (0)
459 // 0x00100000 [20] CLK_SYS_PIO2 (0)
460 // 0x00080000 [19] CLK_SYS_PIO1 (0)
461 // 0x00040000 [18] CLK_SYS_PIO0 (0)
462 // 0x00020000 [17] CLK_SYS_PADS (0)
463 // 0x00010000 [16] CLK_SYS_OTP (0)
464 // 0x00008000 [15] CLK_REF_OTP (0)
465 // 0x00004000 [14] CLK_SYS_JTAG (0)
466 // 0x00002000 [13] CLK_SYS_IO (0)
467 // 0x00001000 [12] CLK_SYS_I2C1 (0)
468 // 0x00000800 [11] CLK_SYS_I2C0 (0)
469 // 0x00000400 [10] CLK_SYS_HSTX (0)
470 // 0x00000200 [9] CLK_HSTX (0)
471 // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0)
472 // 0x00000080 [7] CLK_SYS_DMA (0)
473 // 0x00000040 [6] CLK_SYS_BUSFABRIC (0)
474 // 0x00000020 [5] CLK_SYS_BUSCTRL (0)
475 // 0x00000010 [4] CLK_SYS_BOOTRAM (0)
476 // 0x00000008 [3] CLK_SYS_ADC (0)
477 // 0x00000004 [2] CLK_ADC (0)
478 // 0x00000002 [1] CLK_SYS_ACCESSCTRL (0)
479 // 0x00000001 [0] CLK_SYS_CLOCKS (0)
480 io_ro_32 enabled0;
481
482 _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
483 // indicates the state of the clock enable
484 // 0x40000000 [30] CLK_SYS_XOSC (0)
485 // 0x20000000 [29] CLK_SYS_XIP (0)
486 // 0x10000000 [28] CLK_SYS_WATCHDOG (0)
487 // 0x08000000 [27] CLK_USB (0)
488 // 0x04000000 [26] CLK_SYS_USBCTRL (0)
489 // 0x02000000 [25] CLK_SYS_UART1 (0)
490 // 0x01000000 [24] CLK_PERI_UART1 (0)
491 // 0x00800000 [23] CLK_SYS_UART0 (0)
492 // 0x00400000 [22] CLK_PERI_UART0 (0)
493 // 0x00200000 [21] CLK_SYS_TRNG (0)
494 // 0x00100000 [20] CLK_SYS_TIMER1 (0)
495 // 0x00080000 [19] CLK_SYS_TIMER0 (0)
496 // 0x00040000 [18] CLK_SYS_TICKS (0)
497 // 0x00020000 [17] CLK_REF_TICKS (0)
498 // 0x00010000 [16] CLK_SYS_TBMAN (0)
499 // 0x00008000 [15] CLK_SYS_SYSINFO (0)
500 // 0x00004000 [14] CLK_SYS_SYSCFG (0)
501 // 0x00002000 [13] CLK_SYS_SRAM9 (0)
502 // 0x00001000 [12] CLK_SYS_SRAM8 (0)
503 // 0x00000800 [11] CLK_SYS_SRAM7 (0)
504 // 0x00000400 [10] CLK_SYS_SRAM6 (0)
505 // 0x00000200 [9] CLK_SYS_SRAM5 (0)
506 // 0x00000100 [8] CLK_SYS_SRAM4 (0)
507 // 0x00000080 [7] CLK_SYS_SRAM3 (0)
508 // 0x00000040 [6] CLK_SYS_SRAM2 (0)
509 // 0x00000020 [5] CLK_SYS_SRAM1 (0)
510 // 0x00000010 [4] CLK_SYS_SRAM0 (0)
511 // 0x00000008 [3] CLK_SYS_SPI1 (0)
512 // 0x00000004 [2] CLK_PERI_SPI1 (0)
513 // 0x00000002 [1] CLK_SYS_SPI0 (0)
514 // 0x00000001 [0] CLK_PERI_SPI0 (0)
515 io_ro_32 enabled1;
516 };
517 // (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes)
518 _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
519 // indicates the state of the clock enable
520 // 0x80000000 [31] CLK_SYS_SIO (0)
521 // 0x40000000 [30] CLK_SYS_SHA256 (0)
522 // 0x20000000 [29] CLK_SYS_PSM (0)
523 // 0x10000000 [28] CLK_SYS_ROSC (0)
524 // 0x08000000 [27] CLK_SYS_ROM (0)
525 // 0x04000000 [26] CLK_SYS_RESETS (0)
526 // 0x02000000 [25] CLK_SYS_PWM (0)
527 // 0x01000000 [24] CLK_SYS_POWMAN (0)
528 // 0x00800000 [23] CLK_REF_POWMAN (0)
529 // 0x00400000 [22] CLK_SYS_PLL_USB (0)
530 // 0x00200000 [21] CLK_SYS_PLL_SYS (0)
531 // 0x00100000 [20] CLK_SYS_PIO2 (0)
532 // 0x00080000 [19] CLK_SYS_PIO1 (0)
533 // 0x00040000 [18] CLK_SYS_PIO0 (0)
534 // 0x00020000 [17] CLK_SYS_PADS (0)
535 // 0x00010000 [16] CLK_SYS_OTP (0)
536 // 0x00008000 [15] CLK_REF_OTP (0)
537 // 0x00004000 [14] CLK_SYS_JTAG (0)
538 // 0x00002000 [13] CLK_SYS_IO (0)
539 // 0x00001000 [12] CLK_SYS_I2C1 (0)
540 // 0x00000800 [11] CLK_SYS_I2C0 (0)
541 // 0x00000400 [10] CLK_SYS_HSTX (0)
542 // 0x00000200 [9] CLK_HSTX (0)
543 // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0)
544 // 0x00000080 [7] CLK_SYS_DMA (0)
545 // 0x00000040 [6] CLK_SYS_BUSFABRIC (0)
546 // 0x00000020 [5] CLK_SYS_BUSCTRL (0)
547 // 0x00000010 [4] CLK_SYS_BOOTRAM (0)
548 // 0x00000008 [3] CLK_SYS_ADC (0)
549 // 0x00000004 [2] CLK_ADC (0)
550 // 0x00000002 [1] CLK_SYS_ACCESSCTRL (0)
551 // 0x00000001 [0] CLK_SYS_CLOCKS (0)
552 io_ro_32 enabled[2];
553 };
554
555 _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
556 // Raw Interrupts
557 // 0x00000001 [0] CLK_SYS_RESUS (0)
558 io_ro_32 intr;
559
560 _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
561 // Interrupt Enable
562 // 0x00000001 [0] CLK_SYS_RESUS (0)
563 io_rw_32 inte;
564
565 _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
566 // Interrupt Force
567 // 0x00000001 [0] CLK_SYS_RESUS (0)
568 io_rw_32 intf;
569
570 _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
571 // Interrupt status after masking & forcing
572 // 0x00000001 [0] CLK_SYS_RESUS (0)
573 io_ro_32 ints;
574} clocks_hw_t;
575
576#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE)
577static_assert(sizeof (clocks_hw_t) == 0x00d4, "");
578
579#endif // _HARDWARE_STRUCTS_CLOCKS_H
580
address_mapped.h
clock_dest_num_rp2350
clock_dest_num_rp2350
Clock destination numbers on RP2350 (used as typedef clock_dest_num_t)
Definition: clocks.h:48
clock_dest_num_t
enum clock_dest_num_rp2040 clock_dest_num_t
Clock destination numbers on RP2040 (used as typedef clock_dest_num_t)
clock_num_rp2350
clock_num_rp2350
Clock numbers on RP2350 (used as typedef clock_num_t)
Definition: clocks.h:30
clock_num_t
enum clock_num_rp2040 clock_num_t
Clock numbers on RP2040 (used as typedef clock_num_t)
CLK_DEST_SYS_SRAM8
@ CLK_DEST_SYS_SRAM8
Select SYS_SRAM8 as clock destination.
Definition: clocks.h:93
CLK_DEST_REF_POWMAN
@ CLK_DEST_REF_POWMAN
Select REF_POWMAN as clock destination.
Definition: clocks.h:72
CLK_DEST_REF_TICKS
@ CLK_DEST_REF_TICKS
Select REF_TICKS as clock destination.
Definition: clocks.h:98
CLK_DEST_SYS_SHA256
@ CLK_DEST_SYS_SHA256
Select SYS_SHA256 as clock destination.
Definition: clocks.h:79
CLK_DEST_SYS_SRAM9
@ CLK_DEST_SYS_SRAM9
Select SYS_SRAM9 as clock destination.
Definition: clocks.h:94
CLK_DEST_SYS_ACCESSCTRL
@ CLK_DEST_SYS_ACCESSCTRL
Select SYS_ACCESSCTRL as clock destination.
Definition: clocks.h:50
CLK_DEST_SYS_SRAM7
@ CLK_DEST_SYS_SRAM7
Select SYS_SRAM7 as clock destination.
Definition: clocks.h:92
CLK_DEST_REF_OTP
@ CLK_DEST_REF_OTP
Select REF_OTP as clock destination.
Definition: clocks.h:64
CLK_DEST_HSTX
@ CLK_DEST_HSTX
Select HSTX as clock destination.
Definition: clocks.h:58
CLK_DEST_SYS_PIO2
@ CLK_DEST_SYS_PIO2
Select SYS_PIO2 as clock destination.
Definition: clocks.h:69
CLK_DEST_SYS_TIMER1
@ CLK_DEST_SYS_TIMER1
Select SYS_TIMER1 as clock destination.
Definition: clocks.h:101
CLK_DEST_SYS_TRNG
@ CLK_DEST_SYS_TRNG
Select SYS_TRNG as clock destination.
Definition: clocks.h:102
CLK_DEST_SYS_POWMAN
@ CLK_DEST_SYS_POWMAN
Select SYS_POWMAN as clock destination.
Definition: clocks.h:73
CLK_DEST_ADC
@ CLK_DEST_ADC
Select ADC as clock destination.
Definition: clocks.h:51
CLK_DEST_SYS_TIMER0
@ CLK_DEST_SYS_TIMER0
Select SYS_TIMER0 as clock destination.
Definition: clocks.h:100
CLK_DEST_SYS_TICKS
@ CLK_DEST_SYS_TICKS
Select SYS_TICKS as clock destination.
Definition: clocks.h:99
CLK_DEST_SYS_SRAM6
@ CLK_DEST_SYS_SRAM6
Select SYS_SRAM6 as clock destination.
Definition: clocks.h:91
CLK_DEST_USB
@ CLK_DEST_USB
Select USB as clock destination.
Definition: clocks.h:108
CLK_DEST_SYS_GLITCH_DETECTOR
@ CLK_DEST_SYS_GLITCH_DETECTOR
Select SYS_GLITCH_DETECTOR as clock destination.
Definition: clocks.h:57
CLK_DEST_SYS_BOOTRAM
@ CLK_DEST_SYS_BOOTRAM
Select SYS_BOOTRAM as clock destination.
Definition: clocks.h:53
CLK_DEST_SYS_OTP
@ CLK_DEST_SYS_OTP
Select SYS_OTP as clock destination.
Definition: clocks.h:65
CLK_DEST_SYS_HSTX
@ CLK_DEST_SYS_HSTX
Select SYS_HSTX as clock destination.
Definition: clocks.h:59
CLK_DEST_SYS_BUSCTRL
@ CLK_DEST_SYS_BUSCTRL
Select SYS_BUSCTRL as clock destination.
Definition: clocks.h:52
CLK_DEST_SYS_PIO1
@ CLK_DEST_SYS_PIO1
Select SYS_PIO1 as clock destination.
Definition: clocks.h:62
CLK_DEST_SYS_SIO
@ CLK_DEST_SYS_SIO
Select SYS_SIO as clock destination.
Definition: clocks.h:72
CLK_DEST_SYS_PSM
@ CLK_DEST_SYS_PSM
Select SYS_PSM as clock destination.
Definition: clocks.h:65
CLK_DEST_SYS_UART0
@ CLK_DEST_SYS_UART0
Select SYS_UART0 as clock destination.
Definition: clocks.h:88
CLK_DEST_SYS_TBMAN
@ CLK_DEST_SYS_TBMAN
Select SYS_TBMAN as clock destination.
Definition: clocks.h:85
CLK_DEST_SYS_PLL_USB
@ CLK_DEST_SYS_PLL_USB
Select SYS_PLL_USB as clock destination.
Definition: clocks.h:64
CLK_DEST_SYS_USBCTRL
@ CLK_DEST_SYS_USBCTRL
Select SYS_USBCTRL as clock destination.
Definition: clocks.h:91
CLK_DEST_PERI_UART0
@ CLK_DEST_PERI_UART0
Select PERI_UART0 as clock destination.
Definition: clocks.h:87
CLK_DEST_SYS_I2C1
@ CLK_DEST_SYS_I2C1
Select SYS_I2C1 as clock destination.
Definition: clocks.h:56
CLK_DEST_SYS_PADS
@ CLK_DEST_SYS_PADS
Select SYS_PADS as clock destination.
Definition: clocks.h:60
CLK_DEST_SYS_XIP
@ CLK_DEST_SYS_XIP
Select SYS_XIP as clock destination.
Definition: clocks.h:94
CLK_DEST_SYS_SRAM1
@ CLK_DEST_SYS_SRAM1
Select SYS_SRAM1 as clock destination.
Definition: clocks.h:78
CLK_DEST_SYS_SRAM4
@ CLK_DEST_SYS_SRAM4
Select SYS_SRAM4 as clock destination.
Definition: clocks.h:81
CLK_DEST_PERI_UART1
@ CLK_DEST_PERI_UART1
Select PERI_UART1 as clock destination.
Definition: clocks.h:89
CLK_DEST_SYS_WATCHDOG
@ CLK_DEST_SYS_WATCHDOG
Select SYS_WATCHDOG as clock destination.
Definition: clocks.h:93
CLK_DEST_SYS_ROSC
@ CLK_DEST_SYS_ROSC
Select SYS_ROSC as clock destination.
Definition: clocks.h:69
CLK_DEST_SYS_PIO0
@ CLK_DEST_SYS_PIO0
Select SYS_PIO0 as clock destination.
Definition: clocks.h:61
CLK_DEST_SYS_SRAM2
@ CLK_DEST_SYS_SRAM2
Select SYS_SRAM2 as clock destination.
Definition: clocks.h:79
CLK_DEST_SYS_SRAM5
@ CLK_DEST_SYS_SRAM5
Select SYS_SRAM5 as clock destination.
Definition: clocks.h:82
CLK_DEST_SYS_SPI1
@ CLK_DEST_SYS_SPI1
Select SYS_SPI1 as clock destination.
Definition: clocks.h:76
CLK_DEST_SYS_JTAG
@ CLK_DEST_SYS_JTAG
Select SYS_JTAG as clock destination.
Definition: clocks.h:58
CLK_DEST_SYS_IO
@ CLK_DEST_SYS_IO
Select SYS_IO as clock destination.
Definition: clocks.h:57
CLK_DEST_SYS_SYSINFO
@ CLK_DEST_SYS_SYSINFO
Select SYS_SYSINFO as clock destination.
Definition: clocks.h:84
CLK_DEST_PERI_SPI0
@ CLK_DEST_PERI_SPI0
Select PERI_SPI0 as clock destination.
Definition: clocks.h:73
CLK_DEST_SYS_SYSCFG
@ CLK_DEST_SYS_SYSCFG
Select SYS_SYSCFG as clock destination.
Definition: clocks.h:83
CLK_DEST_SYS_PWM
@ CLK_DEST_SYS_PWM
Select SYS_PWM as clock destination.
Definition: clocks.h:66
CLK_DEST_SYS_SRAM0
@ CLK_DEST_SYS_SRAM0
Select SYS_SRAM0 as clock destination.
Definition: clocks.h:77
CLK_DEST_SYS_CLOCKS
@ CLK_DEST_SYS_CLOCKS
Select SYS_CLOCKS as clock destination.
Definition: clocks.h:49
CLK_DEST_SYS_UART1
@ CLK_DEST_SYS_UART1
Select SYS_UART1 as clock destination.
Definition: clocks.h:90
CLK_DEST_SYS_SPI0
@ CLK_DEST_SYS_SPI0
Select SYS_SPI0 as clock destination.
Definition: clocks.h:74
CLK_DEST_SYS_PLL_SYS
@ CLK_DEST_SYS_PLL_SYS
Select SYS_PLL_SYS as clock destination.
Definition: clocks.h:63
CLK_DEST_SYS_BUSFABRIC
@ CLK_DEST_SYS_BUSFABRIC
Select SYS_BUSFABRIC as clock destination.
Definition: clocks.h:53
CLK_DEST_SYS_DMA
@ CLK_DEST_SYS_DMA
Select SYS_DMA as clock destination.
Definition: clocks.h:54
CLK_DEST_PERI_SPI1
@ CLK_DEST_PERI_SPI1
Select PERI_SPI1 as clock destination.
Definition: clocks.h:75
CLK_DEST_SYS_I2C0
@ CLK_DEST_SYS_I2C0
Select SYS_I2C0 as clock destination.
Definition: clocks.h:55
CLK_DEST_SYS_RESETS
@ CLK_DEST_SYS_RESETS
Select SYS_RESETS as clock destination.
Definition: clocks.h:67
CLK_DEST_SYS_SRAM3
@ CLK_DEST_SYS_SRAM3
Select SYS_SRAM3 as clock destination.
Definition: clocks.h:80
CLK_DEST_SYS_ADC
@ CLK_DEST_SYS_ADC
Select SYS_ADC as clock destination.
Definition: clocks.h:51
CLK_DEST_SYS_ROM
@ CLK_DEST_SYS_ROM
Select SYS_ROM as clock destination.
Definition: clocks.h:68
CLK_DEST_SYS_XOSC
@ CLK_DEST_SYS_XOSC
Select SYS_XOSC as clock destination.
Definition: clocks.h:95
clk_gpout0
@ clk_gpout0
Select CLK_GPOUT0 as clock source.
Definition: clocks.h:31
clk_gpout2
@ clk_gpout2
Select CLK_GPOUT2 as clock source.
Definition: clocks.h:33
clk_peri
@ clk_peri
Select CLK_PERI as clock source.
Definition: clocks.h:37
clk_gpout1
@ clk_gpout1
Select CLK_GPOUT1 as clock source.
Definition: clocks.h:32
clk_ref
@ clk_ref
Select CLK_REF as clock source.
Definition: clocks.h:35
clk_sys
@ clk_sys
Select CLK_SYS as clock source.
Definition: clocks.h:36
clk_usb
@ clk_usb
Select CLK_USB as clock source.
Definition: clocks.h:38
clk_gpout3
@ clk_gpout3
Select CLK_GPOUT3 as clock source.
Definition: clocks.h:34
clk_adc
@ clk_adc
Select CLK_ADC as clock source.
Definition: clocks.h:39
clk_hstx
@ clk_hstx
Select CLK_HSTX as clock source.
Definition: clocks.h:38
clock_hw_t
Definition: clocks.h:100
clock_resus_hw_t
Definition: clocks.h:124
clocks_hw_t
Definition: clocks.h:187
fc_hw_t
Definition: clocks.h:137