v2.0.0
usb.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_USB_H
9#define _HARDWARE_STRUCTS_USB_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/usb.h"
17#include "hardware/structs/usb_dpram.h"
18
19// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb
20//
21// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
22// _REG_(x) will link to the corresponding register in hardware/regs/usb.h.
23//
24// Bit-field descriptions are of the form:
25// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
26
27 typedef struct {
28 _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP
29 // Device address and endpoint control
30 // 0x000f0000 [19:16] ENDPOINT (0x0) Device endpoint to send data to
31 // 0x0000007f [6:0] ADDRESS (0x00) In device mode, the address that the device should respond to
32 io_rw_32 dev_addr_ctrl;
33
34 // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes)
35 _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1
36 // Interrupt endpoint 1
37 // 0x04000000 [26] INTEP_PREAMBLE (0) Interrupt EP requires preamble (is a low speed device on...
38 // 0x02000000 [25] INTEP_DIR (0) Direction of the interrupt endpoint
39 // 0x000f0000 [19:16] ENDPOINT (0x0) Endpoint number of the interrupt endpoint
40 // 0x0000007f [6:0] ADDRESS (0x00) Device address
41 io_rw_32 int_ep_addr_ctrl[15];
42
43 _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL
44 // Main control register
45 // 0x80000000 [31] SIM_TIMING (0) Reduced timings for simulation
46 // 0x00000002 [1] HOST_NDEVICE (0) Device mode = 0, Host mode = 1
47 // 0x00000001 [0] CONTROLLER_EN (0) Enable controller
48 io_rw_32 main_ctrl;
49
50 _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR
51 // Set the SOF (Start of Frame) frame number in the host controller
52 // 0x000007ff [10:0] COUNT (0x000)
53 io_wo_32 sof_wr;
54
55 _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD
56 // Read the last SOF (Start of Frame) frame number seen
57 // 0x000007ff [10:0] COUNT (0x000)
58 io_ro_32 sof_rd;
59
60 _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL
61 // SIE control register
62 // 0x80000000 [31] EP0_INT_STALL (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
63 // 0x40000000 [30] EP0_DOUBLE_BUF (0) Device: EP0 single buffered = 0, double buffered = 1
64 // 0x20000000 [29] EP0_INT_1BUF (0) Device: Set bit in BUFF_STATUS for every buffer completed on EP0
65 // 0x10000000 [28] EP0_INT_2BUF (0) Device: Set bit in BUFF_STATUS for every 2 buffers...
66 // 0x08000000 [27] EP0_INT_NAK (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
67 // 0x04000000 [26] DIRECT_EN (0) Direct bus drive enable
68 // 0x02000000 [25] DIRECT_DP (0) Direct control of DP
69 // 0x01000000 [24] DIRECT_DM (0) Direct control of DM
70 // 0x00040000 [18] TRANSCEIVER_PD (0) Power down bus transceiver
71 // 0x00020000 [17] RPU_OPT (0) Device: Pull-up strength (0=1K2, 1=2k3)
72 // 0x00010000 [16] PULLUP_EN (0) Device: Enable pull up resistor
73 // 0x00008000 [15] PULLDOWN_EN (0) Host: Enable pull down resistors
74 // 0x00002000 [13] RESET_BUS (0) Host: Reset bus
75 // 0x00001000 [12] RESUME (0) Device: Remote wakeup
76 // 0x00000800 [11] VBUS_EN (0) Host: Enable VBUS
77 // 0x00000400 [10] KEEP_ALIVE_EN (0) Host: Enable keep alive packet (for low speed bus)
78 // 0x00000200 [9] SOF_EN (0) Host: Enable SOF generation (for full speed bus)
79 // 0x00000100 [8] SOF_SYNC (0) Host: Delay packet(s) until after SOF
80 // 0x00000040 [6] PREAMBLE_EN (0) Host: Preable enable for LS device on FS hub
81 // 0x00000010 [4] STOP_TRANS (0) Host: Stop transaction
82 // 0x00000008 [3] RECEIVE_DATA (0) Host: Receive transaction (IN to host)
83 // 0x00000004 [2] SEND_DATA (0) Host: Send transaction (OUT from host)
84 // 0x00000002 [1] SEND_SETUP (0) Host: Send Setup packet
85 // 0x00000001 [0] START_TRANS (0) Host: Start transaction
86 io_rw_32 sie_ctrl;
87
88 _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS
89 // SIE status register
90 // 0x80000000 [31] DATA_SEQ_ERROR (0) Data Sequence Error
91 // 0x40000000 [30] ACK_REC (0) ACK received
92 // 0x20000000 [29] STALL_REC (0) Host: STALL received
93 // 0x10000000 [28] NAK_REC (0) Host: NAK received
94 // 0x08000000 [27] RX_TIMEOUT (0) RX timeout is raised by both the host and device if an...
95 // 0x04000000 [26] RX_OVERFLOW (0) RX overflow is raised by the Serial RX engine if the...
96 // 0x02000000 [25] BIT_STUFF_ERROR (0) Bit Stuff Error
97 // 0x01000000 [24] CRC_ERROR (0) CRC Error
98 // 0x00080000 [19] BUS_RESET (0) Device: bus reset received
99 // 0x00040000 [18] TRANS_COMPLETE (0) Transaction complete
100 // 0x00020000 [17] SETUP_REC (0) Device: Setup packet received
101 // 0x00010000 [16] CONNECTED (0) Device: connected
102 // 0x00000800 [11] RESUME (0) Host: Device has initiated a remote resume
103 // 0x00000400 [10] VBUS_OVER_CURR (0) VBUS over current detected
104 // 0x00000300 [9:8] SPEED (0x0) Host: device speed
105 // 0x00000010 [4] SUSPENDED (0) Bus in suspended state
106 // 0x0000000c [3:2] LINE_STATE (0x0) USB bus line state
107 // 0x00000001 [0] VBUS_DETECTED (0) Device: VBUS Detected
108 io_rw_32 sie_status;
109
110 _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL
111 // interrupt endpoint control register
112 // 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 => 15
113 io_rw_32 int_ep_ctrl;
114
115 _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS
116 // Buffer status register
117 // 0x80000000 [31] EP15_OUT (0)
118 // 0x40000000 [30] EP15_IN (0)
119 // 0x20000000 [29] EP14_OUT (0)
120 // 0x10000000 [28] EP14_IN (0)
121 // 0x08000000 [27] EP13_OUT (0)
122 // 0x04000000 [26] EP13_IN (0)
123 // 0x02000000 [25] EP12_OUT (0)
124 // 0x01000000 [24] EP12_IN (0)
125 // 0x00800000 [23] EP11_OUT (0)
126 // 0x00400000 [22] EP11_IN (0)
127 // 0x00200000 [21] EP10_OUT (0)
128 // 0x00100000 [20] EP10_IN (0)
129 // 0x00080000 [19] EP9_OUT (0)
130 // 0x00040000 [18] EP9_IN (0)
131 // 0x00020000 [17] EP8_OUT (0)
132 // 0x00010000 [16] EP8_IN (0)
133 // 0x00008000 [15] EP7_OUT (0)
134 // 0x00004000 [14] EP7_IN (0)
135 // 0x00002000 [13] EP6_OUT (0)
136 // 0x00001000 [12] EP6_IN (0)
137 // 0x00000800 [11] EP5_OUT (0)
138 // 0x00000400 [10] EP5_IN (0)
139 // 0x00000200 [9] EP4_OUT (0)
140 // 0x00000100 [8] EP4_IN (0)
141 // 0x00000080 [7] EP3_OUT (0)
142 // 0x00000040 [6] EP3_IN (0)
143 // 0x00000020 [5] EP2_OUT (0)
144 // 0x00000010 [4] EP2_IN (0)
145 // 0x00000008 [3] EP1_OUT (0)
146 // 0x00000004 [2] EP1_IN (0)
147 // 0x00000002 [1] EP0_OUT (0)
148 // 0x00000001 [0] EP0_IN (0)
149 io_rw_32 buf_status;
150
151 _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE
152 // Which of the double buffers should be handled
153 // 0x80000000 [31] EP15_OUT (0)
154 // 0x40000000 [30] EP15_IN (0)
155 // 0x20000000 [29] EP14_OUT (0)
156 // 0x10000000 [28] EP14_IN (0)
157 // 0x08000000 [27] EP13_OUT (0)
158 // 0x04000000 [26] EP13_IN (0)
159 // 0x02000000 [25] EP12_OUT (0)
160 // 0x01000000 [24] EP12_IN (0)
161 // 0x00800000 [23] EP11_OUT (0)
162 // 0x00400000 [22] EP11_IN (0)
163 // 0x00200000 [21] EP10_OUT (0)
164 // 0x00100000 [20] EP10_IN (0)
165 // 0x00080000 [19] EP9_OUT (0)
166 // 0x00040000 [18] EP9_IN (0)
167 // 0x00020000 [17] EP8_OUT (0)
168 // 0x00010000 [16] EP8_IN (0)
169 // 0x00008000 [15] EP7_OUT (0)
170 // 0x00004000 [14] EP7_IN (0)
171 // 0x00002000 [13] EP6_OUT (0)
172 // 0x00001000 [12] EP6_IN (0)
173 // 0x00000800 [11] EP5_OUT (0)
174 // 0x00000400 [10] EP5_IN (0)
175 // 0x00000200 [9] EP4_OUT (0)
176 // 0x00000100 [8] EP4_IN (0)
177 // 0x00000080 [7] EP3_OUT (0)
178 // 0x00000040 [6] EP3_IN (0)
179 // 0x00000020 [5] EP2_OUT (0)
180 // 0x00000010 [4] EP2_IN (0)
181 // 0x00000008 [3] EP1_OUT (0)
182 // 0x00000004 [2] EP1_IN (0)
183 // 0x00000002 [1] EP0_OUT (0)
184 // 0x00000001 [0] EP0_IN (0)
185 io_ro_32 buf_cpu_should_handle;
186
187 _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT
188 // Device only: Can be set to ignore the buffer control register for this endpoint in case you...
189 // 0x80000000 [31] EP15_OUT (0)
190 // 0x40000000 [30] EP15_IN (0)
191 // 0x20000000 [29] EP14_OUT (0)
192 // 0x10000000 [28] EP14_IN (0)
193 // 0x08000000 [27] EP13_OUT (0)
194 // 0x04000000 [26] EP13_IN (0)
195 // 0x02000000 [25] EP12_OUT (0)
196 // 0x01000000 [24] EP12_IN (0)
197 // 0x00800000 [23] EP11_OUT (0)
198 // 0x00400000 [22] EP11_IN (0)
199 // 0x00200000 [21] EP10_OUT (0)
200 // 0x00100000 [20] EP10_IN (0)
201 // 0x00080000 [19] EP9_OUT (0)
202 // 0x00040000 [18] EP9_IN (0)
203 // 0x00020000 [17] EP8_OUT (0)
204 // 0x00010000 [16] EP8_IN (0)
205 // 0x00008000 [15] EP7_OUT (0)
206 // 0x00004000 [14] EP7_IN (0)
207 // 0x00002000 [13] EP6_OUT (0)
208 // 0x00001000 [12] EP6_IN (0)
209 // 0x00000800 [11] EP5_OUT (0)
210 // 0x00000400 [10] EP5_IN (0)
211 // 0x00000200 [9] EP4_OUT (0)
212 // 0x00000100 [8] EP4_IN (0)
213 // 0x00000080 [7] EP3_OUT (0)
214 // 0x00000040 [6] EP3_IN (0)
215 // 0x00000020 [5] EP2_OUT (0)
216 // 0x00000010 [4] EP2_IN (0)
217 // 0x00000008 [3] EP1_OUT (0)
218 // 0x00000004 [2] EP1_IN (0)
219 // 0x00000002 [1] EP0_OUT (0)
220 // 0x00000001 [0] EP0_IN (0)
221 io_rw_32 abort;
222
223 _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE
224 // Device only: Used in conjunction with `EP_ABORT`
225 // 0x80000000 [31] EP15_OUT (0)
226 // 0x40000000 [30] EP15_IN (0)
227 // 0x20000000 [29] EP14_OUT (0)
228 // 0x10000000 [28] EP14_IN (0)
229 // 0x08000000 [27] EP13_OUT (0)
230 // 0x04000000 [26] EP13_IN (0)
231 // 0x02000000 [25] EP12_OUT (0)
232 // 0x01000000 [24] EP12_IN (0)
233 // 0x00800000 [23] EP11_OUT (0)
234 // 0x00400000 [22] EP11_IN (0)
235 // 0x00200000 [21] EP10_OUT (0)
236 // 0x00100000 [20] EP10_IN (0)
237 // 0x00080000 [19] EP9_OUT (0)
238 // 0x00040000 [18] EP9_IN (0)
239 // 0x00020000 [17] EP8_OUT (0)
240 // 0x00010000 [16] EP8_IN (0)
241 // 0x00008000 [15] EP7_OUT (0)
242 // 0x00004000 [14] EP7_IN (0)
243 // 0x00002000 [13] EP6_OUT (0)
244 // 0x00001000 [12] EP6_IN (0)
245 // 0x00000800 [11] EP5_OUT (0)
246 // 0x00000400 [10] EP5_IN (0)
247 // 0x00000200 [9] EP4_OUT (0)
248 // 0x00000100 [8] EP4_IN (0)
249 // 0x00000080 [7] EP3_OUT (0)
250 // 0x00000040 [6] EP3_IN (0)
251 // 0x00000020 [5] EP2_OUT (0)
252 // 0x00000010 [4] EP2_IN (0)
253 // 0x00000008 [3] EP1_OUT (0)
254 // 0x00000004 [2] EP1_IN (0)
255 // 0x00000002 [1] EP0_OUT (0)
256 // 0x00000001 [0] EP0_IN (0)
257 io_rw_32 abort_done;
258
259 _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM
260 // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register...
261 // 0x00000002 [1] EP0_OUT (0)
262 // 0x00000001 [0] EP0_IN (0)
263 io_rw_32 ep_stall_arm;
264
265 _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL
266 // Used by the host controller
267 // 0x03ff0000 [25:16] DELAY_FS (0x010) NAK polling interval for a full speed device
268 // 0x000003ff [9:0] DELAY_LS (0x010) NAK polling interval for a low speed device
269 io_rw_32 nak_poll;
270
271 _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK
272 // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set
273 // 0x80000000 [31] EP15_OUT (0)
274 // 0x40000000 [30] EP15_IN (0)
275 // 0x20000000 [29] EP14_OUT (0)
276 // 0x10000000 [28] EP14_IN (0)
277 // 0x08000000 [27] EP13_OUT (0)
278 // 0x04000000 [26] EP13_IN (0)
279 // 0x02000000 [25] EP12_OUT (0)
280 // 0x01000000 [24] EP12_IN (0)
281 // 0x00800000 [23] EP11_OUT (0)
282 // 0x00400000 [22] EP11_IN (0)
283 // 0x00200000 [21] EP10_OUT (0)
284 // 0x00100000 [20] EP10_IN (0)
285 // 0x00080000 [19] EP9_OUT (0)
286 // 0x00040000 [18] EP9_IN (0)
287 // 0x00020000 [17] EP8_OUT (0)
288 // 0x00010000 [16] EP8_IN (0)
289 // 0x00008000 [15] EP7_OUT (0)
290 // 0x00004000 [14] EP7_IN (0)
291 // 0x00002000 [13] EP6_OUT (0)
292 // 0x00001000 [12] EP6_IN (0)
293 // 0x00000800 [11] EP5_OUT (0)
294 // 0x00000400 [10] EP5_IN (0)
295 // 0x00000200 [9] EP4_OUT (0)
296 // 0x00000100 [8] EP4_IN (0)
297 // 0x00000080 [7] EP3_OUT (0)
298 // 0x00000040 [6] EP3_IN (0)
299 // 0x00000020 [5] EP2_OUT (0)
300 // 0x00000010 [4] EP2_IN (0)
301 // 0x00000008 [3] EP1_OUT (0)
302 // 0x00000004 [2] EP1_IN (0)
303 // 0x00000002 [1] EP0_OUT (0)
304 // 0x00000001 [0] EP0_IN (0)
305 io_rw_32 ep_nak_stall_status;
306
307 _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING
308 // Where to connect the USB controller
309 // 0x00000008 [3] SOFTCON (0)
310 // 0x00000004 [2] TO_DIGITAL_PAD (0)
311 // 0x00000002 [1] TO_EXTPHY (0)
312 // 0x00000001 [0] TO_PHY (0)
313 io_rw_32 muxing;
314
315 _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR
316 // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO
317 // 0x00000020 [5] OVERCURR_DETECT_EN (0)
318 // 0x00000010 [4] OVERCURR_DETECT (0)
319 // 0x00000008 [3] VBUS_DETECT_OVERRIDE_EN (0)
320 // 0x00000004 [2] VBUS_DETECT (0)
321 // 0x00000002 [1] VBUS_EN_OVERRIDE_EN (0)
322 // 0x00000001 [0] VBUS_EN (0)
323 io_rw_32 pwr;
324
325 _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT
326 // Note that most functions are driven directly from usb_fsls controller
327 // 0x00400000 [22] DM_OVV (0) Status bit from USB PHY
328 // 0x00200000 [21] DP_OVV (0) Status bit from USB PHY
329 // 0x00100000 [20] DM_OVCN (0) Status bit from USB PHY
330 // 0x00080000 [19] DP_OVCN (0) Status bit from USB PHY
331 // 0x00040000 [18] RX_DM (0) Status bit from USB PHY +
332 // 0x00020000 [17] RX_DP (0) Status bit from USB PHY +
333 // 0x00010000 [16] RX_DD (0) Status bit from USB PHY +
334 // 0x00008000 [15] TX_DIFFMODE (0)
335 // 0x00004000 [14] TX_FSSLEW (0)
336 // 0x00002000 [13] TX_PD (0)
337 // 0x00001000 [12] RX_PD (0)
338 // 0x00000800 [11] TX_DM (0) Value to drive to USB PHY when override enable is set...
339 // 0x00000400 [10] TX_DP (0) Value to drive to USB PHY when override enable is set...
340 // 0x00000200 [9] TX_DM_OE (0) Value to drive to USB PHY when override enable is set...
341 // 0x00000100 [8] TX_DP_OE (0) Value to drive to USB PHY when override enable is set...
342 // 0x00000040 [6] DM_PULLDN_EN (0) Value to drive to USB PHY when override enable is set...
343 // 0x00000020 [5] DM_PULLUP_EN (0) Value to drive to USB PHY when override enable is set...
344 // 0x00000010 [4] DM_PULLUP_HISEL (0) when dm_pullup_en is set high, this enables second resistor
345 // 0x00000004 [2] DP_PULLDN_EN (0) Value to drive to USB PHY when override enable is set...
346 // 0x00000002 [1] DP_PULLUP_EN (0) Value to drive to USB PHY when override enable is set...
347 // 0x00000001 [0] DP_PULLUP_HISEL (0) when dp_pullup_en is set high, this enables second resistor
348 io_rw_32 phy_direct;
349
350 _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE
351 // 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0)
352 // 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0)
353 // 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0)
354 // 0x00000400 [10] TX_PD_OVERRIDE_EN (0)
355 // 0x00000200 [9] RX_PD_OVERRIDE_EN (0)
356 // 0x00000100 [8] TX_DM_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
357 // 0x00000080 [7] TX_DP_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
358 // 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
359 // 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
360 // 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
361 // 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
362 // 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
363 // 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0)
364 // 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0)
365 io_rw_32 phy_direct_override;
366
367 _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM
368 // Note that most functions are driven directly from usb_fsls controller
369 // 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY +
370 // 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY +
371 io_rw_32 phy_trim;
372
373 uint32_t _pad0;
374
375 _REG_(USB_INTR_OFFSET) // USB_INTR
376 // Raw Interrupts
377 // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
378 // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
379 // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
380 // 0x00010000 [16] SETUP_REQ (0) Device
381 // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
382 // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
383 // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
384 // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
385 // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
386 // 0x00000400 [10] STALL (0) Source: SIE_STATUS
387 // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
388 // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
389 // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
390 // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
391 // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
392 // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
393 // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
394 // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
395 // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
396 // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
397 io_ro_32 intr;
398
399 _REG_(USB_INTE_OFFSET) // USB_INTE
400 // Interrupt Enable
401 // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
402 // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
403 // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
404 // 0x00010000 [16] SETUP_REQ (0) Device
405 // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
406 // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
407 // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
408 // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
409 // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
410 // 0x00000400 [10] STALL (0) Source: SIE_STATUS
411 // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
412 // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
413 // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
414 // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
415 // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
416 // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
417 // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
418 // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
419 // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
420 // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
421 io_rw_32 inte;
422
423 _REG_(USB_INTF_OFFSET) // USB_INTF
424 // Interrupt Force
425 // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
426 // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
427 // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
428 // 0x00010000 [16] SETUP_REQ (0) Device
429 // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
430 // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
431 // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
432 // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
433 // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
434 // 0x00000400 [10] STALL (0) Source: SIE_STATUS
435 // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
436 // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
437 // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
438 // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
439 // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
440 // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
441 // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
442 // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
443 // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
444 // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
445 io_rw_32 intf;
446
447 _REG_(USB_INTS_OFFSET) // USB_INTS
448 // Interrupt status after masking & forcing
449 // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
450 // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
451 // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
452 // 0x00010000 [16] SETUP_REQ (0) Device
453 // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
454 // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
455 // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
456 // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
457 // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
458 // 0x00000400 [10] STALL (0) Source: SIE_STATUS
459 // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
460 // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
461 // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
462 // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
463 // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
464 // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
465 // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
466 // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
467 // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
468 // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
469 io_ro_32 ints;
470} usb_hw_t;
471
472#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE)
473static_assert(sizeof (usb_hw_t) == 0x009c, "");
474
475#endif // _HARDWARE_STRUCTS_USB_H
476
address_mapped.h
usb_hw_t
Definition: usb.h:27