v2.0.0
m33_eppb.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_M33_EPPB_H
9#define _HARDWARE_STRUCTS_M33_EPPB_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/m33_eppb.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33_eppb
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/m33_eppb.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
26#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
27#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
28#endif
29
30
31 typedef struct {
32 // (Description copied from array index 0 register M33_EPPB_NMI_MASK0 applies similarly to other array indexes)
33 _REG_(M33_EPPB_NMI_MASK0_OFFSET) // M33_EPPB_NMI_MASK0
34 // NMI mask for IRQs 0 through 31
35 // 0xffffffff [31:0] NMI_MASK0 (0x00000000)
36 io_rw_32 nmi_mask[2];
37
38 _REG_(M33_EPPB_SLEEPCTRL_OFFSET) // M33_EPPB_SLEEPCTRL
39 // Nonstandard sleep control register
40 // 0x00000004 [2] WICENACK (0) Status signal from the processor's interrupt controller
41 // 0x00000002 [1] WICENREQ (1) Request that the next processor deep sleep is a WIC sleep
42 // 0x00000001 [0] LIGHT_SLEEP (0) By default, any processor sleep will deassert the...
43 io_rw_32 sleepctrl;
44} m33_eppb_hw_t;
45
46#define eppb_hw ((m33_eppb_hw_t *)EPPB_BASE)
47static_assert(sizeof (m33_eppb_hw_t) == 0x000c, "");
48
49#endif // _HARDWARE_STRUCTS_M33_EPPB_H
50
address_mapped.h
m33_eppb_hw_t
Definition: m33_eppb.h:31