v2.0.0-develop
mpu.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_MPU_H
9#define _HARDWARE_STRUCTS_MPU_H
10
11#include "hardware/address_mapped.h"
12#include "hardware/regs/m33.h"
13
14// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
15//
16// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
17// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
18//
19// Bit-field descriptions are of the form:
20// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
21
22#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
23#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
24#endif
25
26 typedef struct {
27 _REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE
28 // The MPU Type Register indicates how many regions the MPU `FTSSS supports
29 // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
30 // 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data...
31 io_ro_32 type;
32
33 _REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL
34 // Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled...
35 // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for...
36 // 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less...
37 // 0x00000001 [0] ENABLE (0) Enables the MPU
38 io_rw_32 ctrl;
39
40 _REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR
41 // Selects the region currently accessed by MPU_RBAR and MPU_RLAR
42 // 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR
43 io_rw_32 rnr;
44
45 _REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR
46 // Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS
47 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
48 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
49 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
50 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region
51 io_rw_32 rbar;
52
53 _REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR
54 // Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS
55 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
56 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
57 // 0x00000001 [0] EN (0) Region enable
58 io_rw_32 rlar;
59
60 _REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1
61 // Provides indirect read and write access to the base address of the MPU region selected by...
62 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
63 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
64 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
65 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region
66 io_rw_32 rbar_a1;
67
68 _REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1
69 // Provides indirect read and write access to the limit address of the currently selected MPU...
70 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
71 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
72 // 0x00000001 [0] EN (0) Region enable
73 io_rw_32 rlar_a1;
74
75 _REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2
76 // Provides indirect read and write access to the base address of the MPU region selected by...
77 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
78 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
79 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
80 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region
81 io_rw_32 rbar_a2;
82
83 _REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2
84 // Provides indirect read and write access to the limit address of the currently selected MPU...
85 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
86 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
87 // 0x00000001 [0] EN (0) Region enable
88 io_rw_32 rlar_a2;
89
90 _REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3
91 // Provides indirect read and write access to the base address of the MPU region selected by...
92 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
93 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
94 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
95 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region
96 io_rw_32 rbar_a3;
97
98 _REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3
99 // Provides indirect read and write access to the limit address of the currently selected MPU...
100 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
101 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
102 // 0x00000001 [0] EN (0) Region enable
103 io_rw_32 rlar_a3;
104
105 uint32_t _pad0;
106
107 // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes)
108 _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0
109 // Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values
110 // 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3
111 // 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2
112 // 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1
113 // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0
114 io_rw_32 mair[2];
115
116} mpu_hw_t;
117
118#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M33_MPU_TYPE_OFFSET))
119#define mpu_ns_hw ((mpu_hw_t *)(PPB_NONSEC_BASE + M33_MPU_TYPE_OFFSET))
120static_assert(sizeof (mpu_hw_t) == 0x0038, "");
121
122#endif // _HARDWARE_STRUCTS_MPU_H
123
address_mapped.h
mpu_hw_t
Definition: mpu.h:26