v2.0.0
cyw43_spi.h
Go to the documentation of this file.
1/*
2 * This file is part of the cyw43-driver
3 *
4 * Copyright (C) 2019-2022 George Robotics Pty Ltd
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright notice,
10 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 * 3. Any redistribution, use, or modification in source or binary form is done
15 * solely for personal benefit and not for any commercial purpose or for
16 * monetary gain.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS" AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 * DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT OWNER BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * This software is also available for use with certain devices under different
30 * terms, as set out in the top level LICENSE file. For commercial licensing
31 * options please email contact@georgerobotics.com.au.
32 */
33
39#ifndef CYW43_INCLUDED_CYW43_SPI_H
40#define CYW43_INCLUDED_CYW43_SPI_H
41
42// Test register value
43#define TEST_PATTERN 0xFEEDBEADu
44
45// Register addresses
46#define SPI_BUS_CONTROL ((uint32_t)0x0000)
47#define SPI_RESPONSE_DELAY ((uint32_t)0x0001)
48#define SPI_STATUS_ENABLE ((uint32_t)0x0002)
49#define SPI_RESET_BP ((uint32_t)0x0003) // (corerev >= 1)
50#define SPI_INTERRUPT_REGISTER ((uint32_t)0x0004) // 16 bits - Interrupt status
51#define SPI_INTERRUPT_ENABLE_REGISTER ((uint32_t)0x0006) // 16 bits - Interrupt mask
52#define SPI_STATUS_REGISTER ((uint32_t)0x0008) // 32 bits
53#define SPI_FUNCTION1_INFO ((uint32_t)0x000C) // 16 bits
54#define SPI_FUNCTION2_INFO ((uint32_t)0x000E) // 16 bits
55#define SPI_FUNCTION3_INFO ((uint32_t)0x0010) // 16 bits
56#define SPI_READ_TEST_REGISTER ((uint32_t)0x0014) // 32 bits
57#define SPI_RESP_DELAY_F0 ((uint32_t)0x001c) // 8 bits (corerev >= 3)
58#define SPI_RESP_DELAY_F1 ((uint32_t)0x001d) // 8 bits (corerev >= 3)
59#define SPI_RESP_DELAY_F2 ((uint32_t)0x001e) // 8 bits (corerev >= 3)
60#define SPI_RESP_DELAY_F3 ((uint32_t)0x001f) // 8 bits (corerev >= 3)
61
62// SPI_FUNCTIONX_BITS
63#define SPI_FUNCTIONX_ENABLED (1 << 0)
64#define SPI_FUNCTIONX_READY (1 << 1)
65
66// SPI_BUS_CONTROL Bits
67#define WORD_LENGTH_32 ((uint32_t)0x01) // 0/1 16/32 bit word length
68#define ENDIAN_BIG ((uint32_t)0x02) // 0/1 Little/Big Endian
69#define CLOCK_PHASE ((uint32_t)0x04) // 0/1 clock phase delay
70#define CLOCK_POLARITY ((uint32_t)0x08) // 0/1 Idle state clock polarity is low/high
71#define HIGH_SPEED_MODE ((uint32_t)0x10) // 1/0 High Speed mode / Normal mode
72#define INTERRUPT_POLARITY_HIGH ((uint32_t)0x20) // 1/0 Interrupt active polarity is high/low
73#define WAKE_UP ((uint32_t)0x80) // 0/1 Wake-up command from Host to WLAN
74
75// SPI_STATUS_ENABLE bits
76#define STATUS_ENABLE ((uint32_t)0x01) // 1/0 Status sent/not sent to host after read/write
77#define INTR_WITH_STATUS ((uint32_t)0x02) // 0/1 Do-not / do-interrupt if status is sent
78#define RESP_DELAY_ALL ((uint32_t)0x04) // Applicability of resp delay to F1 or all func's read
79#define DWORD_PKT_LEN_EN ((uint32_t)0x08) // Packet len denoted in dwords instead of bytes
80#define CMD_ERR_CHK_EN ((uint32_t)0x20) // Command error check enable
81#define DATA_ERR_CHK_EN ((uint32_t)0x40) // Data error check enable
82
83// SPI_INTERRUPT_REGISTER and SPI_INTERRUPT_ENABLE_REGISTER bits
84#define DATA_UNAVAILABLE ((uint32_t)0x0001) // Requested data not available; Clear by writing a "1"
85#define F2_F3_FIFO_RD_UNDERFLOW ((uint32_t)0x0002)
86#define F2_F3_FIFO_WR_OVERFLOW ((uint32_t)0x0004)
87#define COMMAND_ERROR ((uint32_t)0x0008) // Cleared by writing 1
88#define DATA_ERROR ((uint32_t)0x0010) // Cleared by writing 1
89#define F2_PACKET_AVAILABLE ((uint32_t)0x0020)
90#define F3_PACKET_AVAILABLE ((uint32_t)0x0040)
91#define F1_OVERFLOW ((uint32_t)0x0080) // Due to last write. Bkplane has pending write requests
92#define GSPI_PACKET_AVAILABLE ((uint32_t)0x0100)
93#define MISC_INTR1 ((uint32_t)0x0200)
94#define MISC_INTR2 ((uint32_t)0x0400)
95#define MISC_INTR3 ((uint32_t)0x0800)
96#define MISC_INTR4 ((uint32_t)0x1000)
97#define F1_INTR ((uint32_t)0x2000)
98#define F2_INTR ((uint32_t)0x4000)
99#define F3_INTR ((uint32_t)0x8000)
100
101#define BUS_OVERFLOW_UNDERFLOW (F1_OVERFLOW | F2_F3_FIFO_RD_UNDERFLOW | F2_F3_FIFO_WR_OVERFLOW)
102
103// SPI_STATUS_REGISTER bits
104#define STATUS_DATA_NOT_AVAILABLE ((uint32_t)0x00000001)
105#define STATUS_UNDERFLOW ((uint32_t)0x00000002)
106#define STATUS_OVERFLOW ((uint32_t)0x00000004)
107#define STATUS_F2_INTR ((uint32_t)0x00000008)
108#define STATUS_F3_INTR ((uint32_t)0x00000010)
109#define STATUS_F2_RX_READY ((uint32_t)0x00000020)
110#define STATUS_F3_RX_READY ((uint32_t)0x00000040)
111#define STATUS_HOST_CMD_DATA_ERR ((uint32_t)0x00000080)
112#define STATUS_F2_PKT_AVAILABLE ((uint32_t)0x00000100)
113#define STATUS_F2_PKT_LEN_MASK ((uint32_t)0x000FFE00)
114#define STATUS_F2_PKT_LEN_SHIFT ((uint32_t)9)
115#define STATUS_F3_PKT_AVAILABLE ((uint32_t)0x00100000)
116#define STATUS_F3_PKT_LEN_MASK ((uint32_t)0xFFE00000)
117#define STATUS_F3_PKT_LEN_SHIFT ((uint32_t)21)
118
119#define SPI_FRAME_CONTROL ((uint32_t)0x1000D)
120
121// Read and write before switching to 32bit mode
122uint32_t read_reg_u32_swap(cyw43_int_t *self, uint32_t fn, uint32_t reg);
123int write_reg_u32_swap(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint32_t val);
124
125// spi setup functions
126int cyw43_spi_init(cyw43_int_t *self);
127void cyw43_spi_deinit(cyw43_int_t *self);
128void cyw43_spi_gpio_setup(void);
129void cyw43_spi_reset(void);
130
131// For f1 overflow
132int cyw43_spi_transfer(cyw43_int_t *self, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length);
133
134#endif
_cyw43_int_t
Definition: cyw43_internal.h:46