v2.0.0-develop
nvic.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_NVIC_H
9#define _HARDWARE_STRUCTS_NVIC_H
10
11#include "hardware/address_mapped.h"
12#include "hardware/regs/m33.h"
13
14// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
15//
16// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
17// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
18//
19// Bit-field descriptions are of the form:
20// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
21
22#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
23#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
24#endif
25
26 typedef struct {
27 // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes)
28 _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0
29 // Enables or reads the enabled state of each group of 32 interrupts
30 // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether...
31 io_rw_32 iser[2];
32
33 uint32_t _pad0[30];
34
35 // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes)
36 _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0
37 // Clears or reads the enabled state of each group of 32 interrupts
38 // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether...
39 io_rw_32 icer[2];
40
41 uint32_t _pad1[30];
42
43 // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes)
44 _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0
45 // Enables or reads the pending state of each group of 32 interrupts
46 // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether...
47 io_rw_32 ispr[2];
48
49 uint32_t _pad2[30];
50
51 // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes)
52 _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0
53 // Clears or reads the pending state of each group of 32 interrupts
54 // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether...
55 io_rw_32 icpr[2];
56
57 uint32_t _pad3[30];
58
59 // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes)
60 _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0
61 // For each group of 32 interrupts, shows the active state of each interrupt
62 // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state...
63 io_rw_32 iabr[2];
64
65 uint32_t _pad4[30];
66
67 // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes)
68 _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0
69 // For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state
70 // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security...
71 io_rw_32 itns[2];
72
73 uint32_t _pad5[30];
74
75 // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes)
76 _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0
77 // Sets or reads interrupt priorities
78 // 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number...
79 // 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number...
80 // 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number...
81 // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number...
82 io_rw_32 ipr[16];
83
84} nvic_hw_t;
85
86#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET))
87#define nvic_ns_hw ((nvic_hw_t *)(PPB_NONSEC_BASE + M33_NVIC_ISER0_OFFSET))
88static_assert(sizeof (nvic_hw_t) == 0x0340, "");
89
90#endif // _HARDWARE_STRUCTS_NVIC_H
91
address_mapped.h
nvic_hw_t
Definition: nvic.h:26