v2.0.0
Macros | Functions
cyw43_spi.h File Reference

CYW43 SPI API. More...

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## Macros
#define | TEST_PATTERN 0xFEEDBEADu
#define | SPI_BUS_CONTROL ((uint32_t)0x0000)
#define | SPI_RESPONSE_DELAY ((uint32_t)0x0001)
#define | SPI_STATUS_ENABLE ((uint32_t)0x0002)
#define | SPI_RESET_BP ((uint32_t)0x0003)
#define | SPI_INTERRUPT_REGISTER ((uint32_t)0x0004)
#define | SPI_INTERRUPT_ENABLE_REGISTER ((uint32_t)0x0006)
#define | SPI_STATUS_REGISTER ((uint32_t)0x0008)
#define | SPI_FUNCTION1_INFO ((uint32_t)0x000C)
#define | SPI_FUNCTION2_INFO ((uint32_t)0x000E)
#define | SPI_FUNCTION3_INFO ((uint32_t)0x0010)
#define | SPI_READ_TEST_REGISTER ((uint32_t)0x0014)
#define | SPI_RESP_DELAY_F0 ((uint32_t)0x001c)
#define | SPI_RESP_DELAY_F1 ((uint32_t)0x001d)
#define | SPI_RESP_DELAY_F2 ((uint32_t)0x001e)
#define | SPI_RESP_DELAY_F3 ((uint32_t)0x001f)
#define | SPI_FUNCTIONX_ENABLED (1 << 0)
#define | SPI_FUNCTIONX_READY (1 << 1)
#define | WORD_LENGTH_32 ((uint32_t)0x01)
#define | ENDIAN_BIG ((uint32_t)0x02)
#define | CLOCK_PHASE ((uint32_t)0x04)
#define | CLOCK_POLARITY ((uint32_t)0x08)
#define | HIGH_SPEED_MODE ((uint32_t)0x10)
#define | INTERRUPT_POLARITY_HIGH ((uint32_t)0x20)
#define | WAKE_UP ((uint32_t)0x80)
#define | STATUS_ENABLE ((uint32_t)0x01)
#define | INTR_WITH_STATUS ((uint32_t)0x02)
#define | RESP_DELAY_ALL ((uint32_t)0x04)
#define | DWORD_PKT_LEN_EN ((uint32_t)0x08)
#define | CMD_ERR_CHK_EN ((uint32_t)0x20)
#define | DATA_ERR_CHK_EN ((uint32_t)0x40)
#define | DATA_UNAVAILABLE ((uint32_t)0x0001)
#define | F2_F3_FIFO_RD_UNDERFLOW ((uint32_t)0x0002)
#define | F2_F3_FIFO_WR_OVERFLOW ((uint32_t)0x0004)
#define | COMMAND_ERROR ((uint32_t)0x0008)
#define | DATA_ERROR ((uint32_t)0x0010)
#define | F2_PACKET_AVAILABLE ((uint32_t)0x0020)
#define | F3_PACKET_AVAILABLE ((uint32_t)0x0040)
#define | F1_OVERFLOW ((uint32_t)0x0080)
#define | GSPI_PACKET_AVAILABLE ((uint32_t)0x0100)
#define | MISC_INTR1 ((uint32_t)0x0200)
#define | MISC_INTR2 ((uint32_t)0x0400)
#define | MISC_INTR3 ((uint32_t)0x0800)
#define | MISC_INTR4 ((uint32_t)0x1000)
#define | F1_INTR ((uint32_t)0x2000)
#define | F2_INTR ((uint32_t)0x4000)
#define | F3_INTR ((uint32_t)0x8000)
#define | BUS_OVERFLOW_UNDERFLOW (F1_OVERFLOW | F2_F3_FIFO_RD_UNDERFLOW | F2_F3_FIFO_WR_OVERFLOW)
#define | STATUS_DATA_NOT_AVAILABLE ((uint32_t)0x00000001)
#define | STATUS_UNDERFLOW ((uint32_t)0x00000002)
#define | STATUS_OVERFLOW ((uint32_t)0x00000004)
#define | STATUS_F2_INTR ((uint32_t)0x00000008)
#define | STATUS_F3_INTR ((uint32_t)0x00000010)
#define | STATUS_F2_RX_READY ((uint32_t)0x00000020)
#define | STATUS_F3_RX_READY ((uint32_t)0x00000040)
#define | STATUS_HOST_CMD_DATA_ERR ((uint32_t)0x00000080)
#define | STATUS_F2_PKT_AVAILABLE ((uint32_t)0x00000100)
#define | STATUS_F2_PKT_LEN_MASK ((uint32_t)0x000FFE00)
#define | STATUS_F2_PKT_LEN_SHIFT ((uint32_t)9)
#define | STATUS_F3_PKT_AVAILABLE ((uint32_t)0x00100000)
#define | STATUS_F3_PKT_LEN_MASK ((uint32_t)0xFFE00000)
#define | STATUS_F3_PKT_LEN_SHIFT ((uint32_t)21)
#define | SPI_FRAME_CONTROL ((uint32_t)0x1000D)

## Functions
uint32_t | read_reg_u32_swap (cyw43_int_t *self, uint32_t fn, uint32_t reg)
int | write_reg_u32_swap (cyw43_int_t *self, uint32_t fn, uint32_t reg, uint32_t val)
int | cyw43_spi_init (cyw43_int_t *self)
void | cyw43_spi_deinit (cyw43_int_t *self)
void | cyw43_spi_gpio_setup (void)
void | cyw43_spi_reset (void)
int | cyw43_spi_transfer (cyw43_int_t *self, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length)

## Detailed Description

CYW43 SPI API.