v2.0.0
io_bank0.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_IO_BANK0_H
9#define _HARDWARE_STRUCTS_IO_BANK0_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/io_bank0.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
30 typedef enum gpio_function_rp2040 {
31 GPIO_FUNC_XIP = 0,
32 GPIO_FUNC_SPI = 1,
33 GPIO_FUNC_UART = 2,
34 GPIO_FUNC_I2C = 3,
35 GPIO_FUNC_PWM = 4,
36 GPIO_FUNC_SIO = 5,
37 GPIO_FUNC_PIO0 = 6,
38 GPIO_FUNC_PIO1 = 7,
39 GPIO_FUNC_GPCK = 8,
40 GPIO_FUNC_USB = 9,
41 GPIO_FUNC_NULL = 0x1f,
42} gpio_function_t;
43
44 typedef struct {
45 _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS
46 // GPIO status
47 // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
48 // 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied
49 // 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied
50 // 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied
51 // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
52 // 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register...
53 // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
54 // 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register...
55 io_ro_32 status;
56
57 _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL
58 // GPIO control including function select and overrides
59 // 0x30000000 [29:28] IRQOVER (0x0)
60 // 0x00030000 [17:16] INOVER (0x0)
61 // 0x00003000 [13:12] OEOVER (0x0)
62 // 0x00000300 [9:8] OUTOVER (0x0)
63 // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
64 io_rw_32 ctrl;
65} io_bank0_status_ctrl_hw_t;
66
67 typedef struct {
68 // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
69 _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
70 // Interrupt Enable for proc0
71 // 0x80000000 [31] GPIO7_EDGE_HIGH (0)
72 // 0x40000000 [30] GPIO7_EDGE_LOW (0)
73 // 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
74 // 0x10000000 [28] GPIO7_LEVEL_LOW (0)
75 // 0x08000000 [27] GPIO6_EDGE_HIGH (0)
76 // 0x04000000 [26] GPIO6_EDGE_LOW (0)
77 // 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
78 // 0x01000000 [24] GPIO6_LEVEL_LOW (0)
79 // 0x00800000 [23] GPIO5_EDGE_HIGH (0)
80 // 0x00400000 [22] GPIO5_EDGE_LOW (0)
81 // 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
82 // 0x00100000 [20] GPIO5_LEVEL_LOW (0)
83 // 0x00080000 [19] GPIO4_EDGE_HIGH (0)
84 // 0x00040000 [18] GPIO4_EDGE_LOW (0)
85 // 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
86 // 0x00010000 [16] GPIO4_LEVEL_LOW (0)
87 // 0x00008000 [15] GPIO3_EDGE_HIGH (0)
88 // 0x00004000 [14] GPIO3_EDGE_LOW (0)
89 // 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
90 // 0x00001000 [12] GPIO3_LEVEL_LOW (0)
91 // 0x00000800 [11] GPIO2_EDGE_HIGH (0)
92 // 0x00000400 [10] GPIO2_EDGE_LOW (0)
93 // 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
94 // 0x00000100 [8] GPIO2_LEVEL_LOW (0)
95 // 0x00000080 [7] GPIO1_EDGE_HIGH (0)
96 // 0x00000040 [6] GPIO1_EDGE_LOW (0)
97 // 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
98 // 0x00000010 [4] GPIO1_LEVEL_LOW (0)
99 // 0x00000008 [3] GPIO0_EDGE_HIGH (0)
100 // 0x00000004 [2] GPIO0_EDGE_LOW (0)
101 // 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
102 // 0x00000001 [0] GPIO0_LEVEL_LOW (0)
103 io_rw_32 inte[4];
104
105 // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
106 _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
107 // Interrupt Force for proc0
108 // 0x80000000 [31] GPIO7_EDGE_HIGH (0)
109 // 0x40000000 [30] GPIO7_EDGE_LOW (0)
110 // 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
111 // 0x10000000 [28] GPIO7_LEVEL_LOW (0)
112 // 0x08000000 [27] GPIO6_EDGE_HIGH (0)
113 // 0x04000000 [26] GPIO6_EDGE_LOW (0)
114 // 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
115 // 0x01000000 [24] GPIO6_LEVEL_LOW (0)
116 // 0x00800000 [23] GPIO5_EDGE_HIGH (0)
117 // 0x00400000 [22] GPIO5_EDGE_LOW (0)
118 // 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
119 // 0x00100000 [20] GPIO5_LEVEL_LOW (0)
120 // 0x00080000 [19] GPIO4_EDGE_HIGH (0)
121 // 0x00040000 [18] GPIO4_EDGE_LOW (0)
122 // 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
123 // 0x00010000 [16] GPIO4_LEVEL_LOW (0)
124 // 0x00008000 [15] GPIO3_EDGE_HIGH (0)
125 // 0x00004000 [14] GPIO3_EDGE_LOW (0)
126 // 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
127 // 0x00001000 [12] GPIO3_LEVEL_LOW (0)
128 // 0x00000800 [11] GPIO2_EDGE_HIGH (0)
129 // 0x00000400 [10] GPIO2_EDGE_LOW (0)
130 // 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
131 // 0x00000100 [8] GPIO2_LEVEL_LOW (0)
132 // 0x00000080 [7] GPIO1_EDGE_HIGH (0)
133 // 0x00000040 [6] GPIO1_EDGE_LOW (0)
134 // 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
135 // 0x00000010 [4] GPIO1_LEVEL_LOW (0)
136 // 0x00000008 [3] GPIO0_EDGE_HIGH (0)
137 // 0x00000004 [2] GPIO0_EDGE_LOW (0)
138 // 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
139 // 0x00000001 [0] GPIO0_LEVEL_LOW (0)
140 io_rw_32 intf[4];
141
142 // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
143 _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
144 // Interrupt status after masking & forcing for proc0
145 // 0x80000000 [31] GPIO7_EDGE_HIGH (0)
146 // 0x40000000 [30] GPIO7_EDGE_LOW (0)
147 // 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
148 // 0x10000000 [28] GPIO7_LEVEL_LOW (0)
149 // 0x08000000 [27] GPIO6_EDGE_HIGH (0)
150 // 0x04000000 [26] GPIO6_EDGE_LOW (0)
151 // 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
152 // 0x01000000 [24] GPIO6_LEVEL_LOW (0)
153 // 0x00800000 [23] GPIO5_EDGE_HIGH (0)
154 // 0x00400000 [22] GPIO5_EDGE_LOW (0)
155 // 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
156 // 0x00100000 [20] GPIO5_LEVEL_LOW (0)
157 // 0x00080000 [19] GPIO4_EDGE_HIGH (0)
158 // 0x00040000 [18] GPIO4_EDGE_LOW (0)
159 // 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
160 // 0x00010000 [16] GPIO4_LEVEL_LOW (0)
161 // 0x00008000 [15] GPIO3_EDGE_HIGH (0)
162 // 0x00004000 [14] GPIO3_EDGE_LOW (0)
163 // 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
164 // 0x00001000 [12] GPIO3_LEVEL_LOW (0)
165 // 0x00000800 [11] GPIO2_EDGE_HIGH (0)
166 // 0x00000400 [10] GPIO2_EDGE_LOW (0)
167 // 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
168 // 0x00000100 [8] GPIO2_LEVEL_LOW (0)
169 // 0x00000080 [7] GPIO1_EDGE_HIGH (0)
170 // 0x00000040 [6] GPIO1_EDGE_LOW (0)
171 // 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
172 // 0x00000010 [4] GPIO1_LEVEL_LOW (0)
173 // 0x00000008 [3] GPIO0_EDGE_HIGH (0)
174 // 0x00000004 [2] GPIO0_EDGE_LOW (0)
175 // 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
176 // 0x00000001 [0] GPIO0_LEVEL_LOW (0)
177 io_ro_32 ints[4];
178} io_bank0_irq_ctrl_hw_t;
179
181 typedef struct {
182 io_bank0_status_ctrl_hw_t io[30];
183
184 // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
185 _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
186 // Raw Interrupts
187 // 0x80000000 [31] GPIO7_EDGE_HIGH (0)
188 // 0x40000000 [30] GPIO7_EDGE_LOW (0)
189 // 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
190 // 0x10000000 [28] GPIO7_LEVEL_LOW (0)
191 // 0x08000000 [27] GPIO6_EDGE_HIGH (0)
192 // 0x04000000 [26] GPIO6_EDGE_LOW (0)
193 // 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
194 // 0x01000000 [24] GPIO6_LEVEL_LOW (0)
195 // 0x00800000 [23] GPIO5_EDGE_HIGH (0)
196 // 0x00400000 [22] GPIO5_EDGE_LOW (0)
197 // 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
198 // 0x00100000 [20] GPIO5_LEVEL_LOW (0)
199 // 0x00080000 [19] GPIO4_EDGE_HIGH (0)
200 // 0x00040000 [18] GPIO4_EDGE_LOW (0)
201 // 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
202 // 0x00010000 [16] GPIO4_LEVEL_LOW (0)
203 // 0x00008000 [15] GPIO3_EDGE_HIGH (0)
204 // 0x00004000 [14] GPIO3_EDGE_LOW (0)
205 // 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
206 // 0x00001000 [12] GPIO3_LEVEL_LOW (0)
207 // 0x00000800 [11] GPIO2_EDGE_HIGH (0)
208 // 0x00000400 [10] GPIO2_EDGE_LOW (0)
209 // 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
210 // 0x00000100 [8] GPIO2_LEVEL_LOW (0)
211 // 0x00000080 [7] GPIO1_EDGE_HIGH (0)
212 // 0x00000040 [6] GPIO1_EDGE_LOW (0)
213 // 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
214 // 0x00000010 [4] GPIO1_LEVEL_LOW (0)
215 // 0x00000008 [3] GPIO0_EDGE_HIGH (0)
216 // 0x00000004 [2] GPIO0_EDGE_LOW (0)
217 // 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
218 // 0x00000001 [0] GPIO0_LEVEL_LOW (0)
219 io_rw_32 intr[4];
220
221 union {
222 struct {
223 io_bank0_irq_ctrl_hw_t proc0_irq_ctrl;
224 io_bank0_irq_ctrl_hw_t proc1_irq_ctrl;
225 io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl;
226 };
227 io_bank0_irq_ctrl_hw_t irq_ctrl[3];
228 };
229} io_bank0_hw_t;
231
232#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE)
233static_assert(sizeof (io_bank0_hw_t) == 0x0190, "");
234
235#endif // _HARDWARE_STRUCTS_IO_BANK0_H
236
address_mapped.h
gpio_function_t
enum gpio_function_rp2040 gpio_function_t
GPIO pin function selectors on RP2040 (used as typedef gpio_function_t)
gpio_function_rp2040
gpio_function_rp2040
GPIO pin function selectors on RP2040 (used as typedef gpio_function_t)
Definition: io_bank0.h:30
GPIO_FUNC_PWM
@ GPIO_FUNC_PWM
Select PWM as GPIO pin function.
Definition: io_bank0.h:35
GPIO_FUNC_PIO1
@ GPIO_FUNC_PIO1
Select PIO1 as GPIO pin function.
Definition: io_bank0.h:38
GPIO_FUNC_NULL
@ GPIO_FUNC_NULL
Select NULL as GPIO pin function.
Definition: io_bank0.h:41
GPIO_FUNC_GPCK
@ GPIO_FUNC_GPCK
Select GPCK as GPIO pin function.
Definition: io_bank0.h:39
GPIO_FUNC_USB
@ GPIO_FUNC_USB
Select USB as GPIO pin function.
Definition: io_bank0.h:40
GPIO_FUNC_XIP
@ GPIO_FUNC_XIP
Select XIP as GPIO pin function.
Definition: io_bank0.h:31
GPIO_FUNC_SIO
@ GPIO_FUNC_SIO
Select SIO as GPIO pin function.
Definition: io_bank0.h:36
GPIO_FUNC_SPI
@ GPIO_FUNC_SPI
Select SPI as GPIO pin function.
Definition: io_bank0.h:32
GPIO_FUNC_UART
@ GPIO_FUNC_UART
Select UART as GPIO pin function.
Definition: io_bank0.h:33
GPIO_FUNC_PIO0
@ GPIO_FUNC_PIO0
Select PIO0 as GPIO pin function.
Definition: io_bank0.h:37
GPIO_FUNC_I2C
@ GPIO_FUNC_I2C
Select I2C as GPIO pin function.
Definition: io_bank0.h:34
io_bank0_hw_t
Definition: io_bank0.h:181
io_bank0_irq_ctrl_hw_t
Definition: io_bank0.h:67
io_bank0_status_ctrl_hw_t
Definition: io_bank0.h:44