v2.0.0-develop
syscfg.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_SYSCFG_H
9#define _HARDWARE_STRUCTS_SYSCFG_H
10
11#include "hardware/address_mapped.h"
12#include "hardware/regs/syscfg.h"
13
14// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_syscfg
15//
16// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
17// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h.
18//
19// Bit-field descriptions are of the form:
20// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
21
22 typedef struct {
23 _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG
24 // Configuration for processors
25 // 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted
26 // 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted
27 io_ro_32 proc_config;
28
29 _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS
30 // For each bit, if 1, bypass the input synchronizer between that GPIO +
31 // 0xffffffff [31:0] GPIO (0x00000000)
32 io_rw_32 proc_in_sync_bypass;
33
34 _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI
35 // For each bit, if 1, bypass the input synchronizer between that GPIO +
36 // 0xf0000000 [31:28] QSPI_SD (0x0)
37 // 0x08000000 [27] QSPI_CSN (0)
38 // 0x04000000 [26] QSPI_SCK (0)
39 // 0x02000000 [25] USB_DM (0)
40 // 0x01000000 [24] USB_DP (0)
41 // 0x0000ffff [15:0] GPIO (0x0000)
42 io_rw_32 proc_in_sync_bypass_hi;
43
44 _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE
45 // Directly control the chip SWD debug port
46 // 0x00000008 [3] ATTACH (0) Attach chip debug port to syscfg controls, and...
47 // 0x00000004 [2] SWCLK (1) Directly drive SWCLK, if ATTACH is set
48 // 0x00000002 [1] SWDI (1) Directly drive SWDIO input, if ATTACH is set
49 // 0x00000001 [0] SWDO (-) Observe the value of SWDIO output
50 io_rw_32 dbgforce;
51
52 _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN
53 // Control PD pins to memories
54 // 0x00001000 [12] BOOTRAM (0)
55 // 0x00000800 [11] ROM (0)
56 // 0x00000400 [10] USB (0)
57 // 0x00000200 [9] SRAM9 (0)
58 // 0x00000100 [8] SRAM8 (0)
59 // 0x00000080 [7] SRAM7 (0)
60 // 0x00000040 [6] SRAM6 (0)
61 // 0x00000020 [5] SRAM5 (0)
62 // 0x00000010 [4] SRAM4 (0)
63 // 0x00000008 [3] SRAM3 (0)
64 // 0x00000004 [2] SRAM2 (0)
65 // 0x00000002 [1] SRAM1 (0)
66 // 0x00000001 [0] SRAM0 (0)
67 io_rw_32 mempowerdown;
68
69 _REG_(SYSCFG_AUXCTRL_OFFSET) // SYSCFG_AUXCTRL
70 // Auxiliary system control register
71 // 0x000000ff [7:0] AUXCTRL (0x00) * Bits 7:2: Reserved
72 io_rw_32 auxctrl;
73
74} syscfg_hw_t;
75
76#define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE)
77static_assert(sizeof (syscfg_hw_t) == 0x0018, "");
78
79#endif // _HARDWARE_STRUCTS_SYSCFG_H
80
address_mapped.h
syscfg_hw_t
Definition: syscfg.h:22