v2.0.0-develop
usb.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_USB_H
9#define _HARDWARE_STRUCTS_USB_H
10
11#include "hardware/address_mapped.h"
12#include "hardware/regs/usb.h"
13#include "hardware/structs/usb_dpram.h"
14
15// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb
16//
17// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18// _REG_(x) will link to the corresponding register in hardware/regs/usb.h.
19//
20// Bit-field descriptions are of the form:
21// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
22
23 typedef struct {
24 _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP
25 // Device address and endpoint control
26 // 0x000f0000 [19:16] ENDPOINT (0x0) Device endpoint to send data to
27 // 0x0000007f [6:0] ADDRESS (0x00) In device mode, the address that the device should respond to
28 io_rw_32 dev_addr_ctrl;
29
30 // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes)
31 _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1
32 // Interrupt endpoint 1
33 // 0x04000000 [26] INTEP_PREAMBLE (0) Interrupt EP requires preamble (is a low speed device on...
34 // 0x02000000 [25] INTEP_DIR (0) Direction of the interrupt endpoint
35 // 0x000f0000 [19:16] ENDPOINT (0x0) Endpoint number of the interrupt endpoint
36 // 0x0000007f [6:0] ADDRESS (0x00) Device address
37 io_rw_32 int_ep_addr_ctrl[15];
38
39 _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL
40 // Main control register
41 // 0x80000000 [31] SIM_TIMING (0) Reduced timings for simulation
42 // 0x00000004 [2] PHY_ISO (1) Isolates USB phy after controller power-up +
43 // 0x00000002 [1] HOST_NDEVICE (0) Device mode = 0, Host mode = 1
44 // 0x00000001 [0] CONTROLLER_EN (0) Enable controller
45 io_rw_32 main_ctrl;
46
47 _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR
48 // Set the SOF (Start of Frame) frame number in the host controller
49 // 0x000007ff [10:0] COUNT (0x000)
50 io_wo_32 sof_wr;
51
52 _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD
53 // Read the last SOF (Start of Frame) frame number seen
54 // 0x000007ff [10:0] COUNT (0x000)
55 io_ro_32 sof_rd;
56
57 _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL
58 // SIE control register
59 // 0x80000000 [31] EP0_INT_STALL (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
60 // 0x40000000 [30] EP0_DOUBLE_BUF (0) Device: EP0 single buffered = 0, double buffered = 1
61 // 0x20000000 [29] EP0_INT_1BUF (0) Device: Set bit in BUFF_STATUS for every buffer completed on EP0
62 // 0x10000000 [28] EP0_INT_2BUF (0) Device: Set bit in BUFF_STATUS for every 2 buffers...
63 // 0x08000000 [27] EP0_INT_NAK (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
64 // 0x04000000 [26] DIRECT_EN (0) Direct bus drive enable
65 // 0x02000000 [25] DIRECT_DP (0) Direct control of DP
66 // 0x01000000 [24] DIRECT_DM (0) Direct control of DM
67 // 0x00080000 [19] EP0_STOP_ON_SHORT_PACKET (0) Device: Stop EP0 on a short packet
68 // 0x00040000 [18] TRANSCEIVER_PD (0) Power down bus transceiver
69 // 0x00020000 [17] RPU_OPT (0) Device: Pull-up strength (0=1K2, 1=2k3)
70 // 0x00010000 [16] PULLUP_EN (0) Device: Enable pull up resistor
71 // 0x00008000 [15] PULLDOWN_EN (1) Host: Enable pull down resistors
72 // 0x00002000 [13] RESET_BUS (0) Host: Reset bus
73 // 0x00001000 [12] RESUME (0) Device: Remote wakeup
74 // 0x00000800 [11] VBUS_EN (0) Host: Enable VBUS
75 // 0x00000400 [10] KEEP_ALIVE_EN (0) Host: Enable keep alive packet (for low speed bus)
76 // 0x00000200 [9] SOF_EN (0) Host: Enable SOF generation (for full speed bus)
77 // 0x00000100 [8] SOF_SYNC (0) Host: Delay packet(s) until after SOF
78 // 0x00000040 [6] PREAMBLE_EN (0) Host: Preable enable for LS device on FS hub
79 // 0x00000010 [4] STOP_TRANS (0) Host: Stop transaction
80 // 0x00000008 [3] RECEIVE_DATA (0) Host: Receive transaction (IN to host)
81 // 0x00000004 [2] SEND_DATA (0) Host: Send transaction (OUT from host)
82 // 0x00000002 [1] SEND_SETUP (0) Host: Send Setup packet
83 // 0x00000001 [0] START_TRANS (0) Host: Start transaction
84 io_rw_32 sie_ctrl;
85
86 _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS
87 // SIE status register
88 // 0x80000000 [31] DATA_SEQ_ERROR (0) Data Sequence Error
89 // 0x40000000 [30] ACK_REC (0) ACK received
90 // 0x20000000 [29] STALL_REC (0) Host: STALL received
91 // 0x10000000 [28] NAK_REC (0) Host: NAK received
92 // 0x08000000 [27] RX_TIMEOUT (0) RX timeout is raised by both the host and device if an...
93 // 0x04000000 [26] RX_OVERFLOW (0) RX overflow is raised by the Serial RX engine if the...
94 // 0x02000000 [25] BIT_STUFF_ERROR (0) Bit Stuff Error
95 // 0x01000000 [24] CRC_ERROR (0) CRC Error
96 // 0x00800000 [23] ENDPOINT_ERROR (0) An endpoint has encounted an error
97 // 0x00080000 [19] BUS_RESET (0) Device: bus reset received
98 // 0x00040000 [18] TRANS_COMPLETE (0) Transaction complete
99 // 0x00020000 [17] SETUP_REC (0) Device: Setup packet received
100 // 0x00010000 [16] CONNECTED (0) Device: connected
101 // 0x00001000 [12] RX_SHORT_PACKET (0) Device or Host has received a short packet
102 // 0x00000800 [11] RESUME (0) Host: Device has initiated a remote resume
103 // 0x00000400 [10] VBUS_OVER_CURR (0) VBUS over current detected
104 // 0x00000300 [9:8] SPEED (0x0) Host: device speed
105 // 0x00000010 [4] SUSPENDED (0) Bus in suspended state
106 // 0x0000000c [3:2] LINE_STATE (0x0) USB bus line state
107 // 0x00000001 [0] VBUS_DETECTED (0) Device: VBUS Detected
108 io_rw_32 sie_status;
109
110 _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL
111 // interrupt endpoint control register
112 // 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 -> 15
113 io_rw_32 int_ep_ctrl;
114
115 _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS
116 // Buffer status register
117 // 0x80000000 [31] EP15_OUT (0)
118 // 0x40000000 [30] EP15_IN (0)
119 // 0x20000000 [29] EP14_OUT (0)
120 // 0x10000000 [28] EP14_IN (0)
121 // 0x08000000 [27] EP13_OUT (0)
122 // 0x04000000 [26] EP13_IN (0)
123 // 0x02000000 [25] EP12_OUT (0)
124 // 0x01000000 [24] EP12_IN (0)
125 // 0x00800000 [23] EP11_OUT (0)
126 // 0x00400000 [22] EP11_IN (0)
127 // 0x00200000 [21] EP10_OUT (0)
128 // 0x00100000 [20] EP10_IN (0)
129 // 0x00080000 [19] EP9_OUT (0)
130 // 0x00040000 [18] EP9_IN (0)
131 // 0x00020000 [17] EP8_OUT (0)
132 // 0x00010000 [16] EP8_IN (0)
133 // 0x00008000 [15] EP7_OUT (0)
134 // 0x00004000 [14] EP7_IN (0)
135 // 0x00002000 [13] EP6_OUT (0)
136 // 0x00001000 [12] EP6_IN (0)
137 // 0x00000800 [11] EP5_OUT (0)
138 // 0x00000400 [10] EP5_IN (0)
139 // 0x00000200 [9] EP4_OUT (0)
140 // 0x00000100 [8] EP4_IN (0)
141 // 0x00000080 [7] EP3_OUT (0)
142 // 0x00000040 [6] EP3_IN (0)
143 // 0x00000020 [5] EP2_OUT (0)
144 // 0x00000010 [4] EP2_IN (0)
145 // 0x00000008 [3] EP1_OUT (0)
146 // 0x00000004 [2] EP1_IN (0)
147 // 0x00000002 [1] EP0_OUT (0)
148 // 0x00000001 [0] EP0_IN (0)
149 io_rw_32 buf_status;
150
151 _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE
152 // Which of the double buffers should be handled
153 // 0x80000000 [31] EP15_OUT (0)
154 // 0x40000000 [30] EP15_IN (0)
155 // 0x20000000 [29] EP14_OUT (0)
156 // 0x10000000 [28] EP14_IN (0)
157 // 0x08000000 [27] EP13_OUT (0)
158 // 0x04000000 [26] EP13_IN (0)
159 // 0x02000000 [25] EP12_OUT (0)
160 // 0x01000000 [24] EP12_IN (0)
161 // 0x00800000 [23] EP11_OUT (0)
162 // 0x00400000 [22] EP11_IN (0)
163 // 0x00200000 [21] EP10_OUT (0)
164 // 0x00100000 [20] EP10_IN (0)
165 // 0x00080000 [19] EP9_OUT (0)
166 // 0x00040000 [18] EP9_IN (0)
167 // 0x00020000 [17] EP8_OUT (0)
168 // 0x00010000 [16] EP8_IN (0)
169 // 0x00008000 [15] EP7_OUT (0)
170 // 0x00004000 [14] EP7_IN (0)
171 // 0x00002000 [13] EP6_OUT (0)
172 // 0x00001000 [12] EP6_IN (0)
173 // 0x00000800 [11] EP5_OUT (0)
174 // 0x00000400 [10] EP5_IN (0)
175 // 0x00000200 [9] EP4_OUT (0)
176 // 0x00000100 [8] EP4_IN (0)
177 // 0x00000080 [7] EP3_OUT (0)
178 // 0x00000040 [6] EP3_IN (0)
179 // 0x00000020 [5] EP2_OUT (0)
180 // 0x00000010 [4] EP2_IN (0)
181 // 0x00000008 [3] EP1_OUT (0)
182 // 0x00000004 [2] EP1_IN (0)
183 // 0x00000002 [1] EP0_OUT (0)
184 // 0x00000001 [0] EP0_IN (0)
185 io_ro_32 buf_cpu_should_handle;
186
187 _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT
188 // Device only: Can be set to ignore the buffer control register for this endpoint in case you...
189 // 0x80000000 [31] EP15_OUT (0)
190 // 0x40000000 [30] EP15_IN (0)
191 // 0x20000000 [29] EP14_OUT (0)
192 // 0x10000000 [28] EP14_IN (0)
193 // 0x08000000 [27] EP13_OUT (0)
194 // 0x04000000 [26] EP13_IN (0)
195 // 0x02000000 [25] EP12_OUT (0)
196 // 0x01000000 [24] EP12_IN (0)
197 // 0x00800000 [23] EP11_OUT (0)
198 // 0x00400000 [22] EP11_IN (0)
199 // 0x00200000 [21] EP10_OUT (0)
200 // 0x00100000 [20] EP10_IN (0)
201 // 0x00080000 [19] EP9_OUT (0)
202 // 0x00040000 [18] EP9_IN (0)
203 // 0x00020000 [17] EP8_OUT (0)
204 // 0x00010000 [16] EP8_IN (0)
205 // 0x00008000 [15] EP7_OUT (0)
206 // 0x00004000 [14] EP7_IN (0)
207 // 0x00002000 [13] EP6_OUT (0)
208 // 0x00001000 [12] EP6_IN (0)
209 // 0x00000800 [11] EP5_OUT (0)
210 // 0x00000400 [10] EP5_IN (0)
211 // 0x00000200 [9] EP4_OUT (0)
212 // 0x00000100 [8] EP4_IN (0)
213 // 0x00000080 [7] EP3_OUT (0)
214 // 0x00000040 [6] EP3_IN (0)
215 // 0x00000020 [5] EP2_OUT (0)
216 // 0x00000010 [4] EP2_IN (0)
217 // 0x00000008 [3] EP1_OUT (0)
218 // 0x00000004 [2] EP1_IN (0)
219 // 0x00000002 [1] EP0_OUT (0)
220 // 0x00000001 [0] EP0_IN (0)
221 io_rw_32 abort;
222
223 _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE
224 // Device only: Used in conjunction with `EP_ABORT`
225 // 0x80000000 [31] EP15_OUT (0)
226 // 0x40000000 [30] EP15_IN (0)
227 // 0x20000000 [29] EP14_OUT (0)
228 // 0x10000000 [28] EP14_IN (0)
229 // 0x08000000 [27] EP13_OUT (0)
230 // 0x04000000 [26] EP13_IN (0)
231 // 0x02000000 [25] EP12_OUT (0)
232 // 0x01000000 [24] EP12_IN (0)
233 // 0x00800000 [23] EP11_OUT (0)
234 // 0x00400000 [22] EP11_IN (0)
235 // 0x00200000 [21] EP10_OUT (0)
236 // 0x00100000 [20] EP10_IN (0)
237 // 0x00080000 [19] EP9_OUT (0)
238 // 0x00040000 [18] EP9_IN (0)
239 // 0x00020000 [17] EP8_OUT (0)
240 // 0x00010000 [16] EP8_IN (0)
241 // 0x00008000 [15] EP7_OUT (0)
242 // 0x00004000 [14] EP7_IN (0)
243 // 0x00002000 [13] EP6_OUT (0)
244 // 0x00001000 [12] EP6_IN (0)
245 // 0x00000800 [11] EP5_OUT (0)
246 // 0x00000400 [10] EP5_IN (0)
247 // 0x00000200 [9] EP4_OUT (0)
248 // 0x00000100 [8] EP4_IN (0)
249 // 0x00000080 [7] EP3_OUT (0)
250 // 0x00000040 [6] EP3_IN (0)
251 // 0x00000020 [5] EP2_OUT (0)
252 // 0x00000010 [4] EP2_IN (0)
253 // 0x00000008 [3] EP1_OUT (0)
254 // 0x00000004 [2] EP1_IN (0)
255 // 0x00000002 [1] EP0_OUT (0)
256 // 0x00000001 [0] EP0_IN (0)
257 io_rw_32 abort_done;
258
259 _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM
260 // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register...
261 // 0x00000002 [1] EP0_OUT (0)
262 // 0x00000001 [0] EP0_IN (0)
263 io_rw_32 ep_stall_arm;
264
265 _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL
266 // Used by the host controller
267 // 0xf0000000 [31:28] RETRY_COUNT_HI (0x0) Bits 9:6 of nak_retry count
268 // 0x08000000 [27] EPX_STOPPED_ON_NAK (0) EPX polling has stopped because a nak was received
269 // 0x04000000 [26] STOP_EPX_ON_NAK (0) Stop polling epx when a nak is received
270 // 0x03ff0000 [25:16] DELAY_FS (0x010) NAK polling interval for a full speed device
271 // 0x0000fc00 [15:10] RETRY_COUNT_LO (0x00) Bits 5:0 of nak_retry_count
272 // 0x000003ff [9:0] DELAY_LS (0x010) NAK polling interval for a low speed device
273 io_rw_32 nak_poll;
274
275 _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK
276 // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set
277 // 0x80000000 [31] EP15_OUT (0)
278 // 0x40000000 [30] EP15_IN (0)
279 // 0x20000000 [29] EP14_OUT (0)
280 // 0x10000000 [28] EP14_IN (0)
281 // 0x08000000 [27] EP13_OUT (0)
282 // 0x04000000 [26] EP13_IN (0)
283 // 0x02000000 [25] EP12_OUT (0)
284 // 0x01000000 [24] EP12_IN (0)
285 // 0x00800000 [23] EP11_OUT (0)
286 // 0x00400000 [22] EP11_IN (0)
287 // 0x00200000 [21] EP10_OUT (0)
288 // 0x00100000 [20] EP10_IN (0)
289 // 0x00080000 [19] EP9_OUT (0)
290 // 0x00040000 [18] EP9_IN (0)
291 // 0x00020000 [17] EP8_OUT (0)
292 // 0x00010000 [16] EP8_IN (0)
293 // 0x00008000 [15] EP7_OUT (0)
294 // 0x00004000 [14] EP7_IN (0)
295 // 0x00002000 [13] EP6_OUT (0)
296 // 0x00001000 [12] EP6_IN (0)
297 // 0x00000800 [11] EP5_OUT (0)
298 // 0x00000400 [10] EP5_IN (0)
299 // 0x00000200 [9] EP4_OUT (0)
300 // 0x00000100 [8] EP4_IN (0)
301 // 0x00000080 [7] EP3_OUT (0)
302 // 0x00000040 [6] EP3_IN (0)
303 // 0x00000020 [5] EP2_OUT (0)
304 // 0x00000010 [4] EP2_IN (0)
305 // 0x00000008 [3] EP1_OUT (0)
306 // 0x00000004 [2] EP1_IN (0)
307 // 0x00000002 [1] EP0_OUT (0)
308 // 0x00000001 [0] EP0_IN (0)
309 io_rw_32 ep_nak_stall_status;
310
311 _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING
312 // Where to connect the USB controller
313 // 0x80000000 [31] SWAP_DPDM (0) Swap the USB PHY DP and DM pins and all related controls...
314 // 0x00000010 [4] USBPHY_AS_GPIO (0) Use the usb DP and DM pins as GPIO pins instead of...
315 // 0x00000008 [3] SOFTCON (0)
316 // 0x00000004 [2] TO_DIGITAL_PAD (0)
317 // 0x00000002 [1] TO_EXTPHY (0)
318 // 0x00000001 [0] TO_PHY (1)
319 io_rw_32 muxing;
320
321 _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR
322 // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO
323 // 0x00000020 [5] OVERCURR_DETECT_EN (0)
324 // 0x00000010 [4] OVERCURR_DETECT (0)
325 // 0x00000008 [3] VBUS_DETECT_OVERRIDE_EN (0)
326 // 0x00000004 [2] VBUS_DETECT (0)
327 // 0x00000002 [1] VBUS_EN_OVERRIDE_EN (0)
328 // 0x00000001 [0] VBUS_EN (0)
329 io_rw_32 pwr;
330
331 _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT
332 // This register allows for direct control of the USB phy
333 // 0x02000000 [25] RX_DM_OVERRIDE (0) Override rx_dm value into controller
334 // 0x01000000 [24] RX_DP_OVERRIDE (0) Override rx_dp value into controller
335 // 0x00800000 [23] RX_DD_OVERRIDE (0) Override rx_dd value into controller
336 // 0x00400000 [22] DM_OVV (0) DM over voltage
337 // 0x00200000 [21] DP_OVV (0) DP over voltage
338 // 0x00100000 [20] DM_OVCN (0) DM overcurrent
339 // 0x00080000 [19] DP_OVCN (0) DP overcurrent
340 // 0x00040000 [18] RX_DM (0) DPM pin state
341 // 0x00020000 [17] RX_DP (0) DPP pin state
342 // 0x00010000 [16] RX_DD (0) Differential RX
343 // 0x00008000 [15] TX_DIFFMODE (0) TX_DIFFMODE=0: Single ended mode +
344 // 0x00004000 [14] TX_FSSLEW (0) TX_FSSLEW=0: Low speed slew rate +
345 // 0x00002000 [13] TX_PD (0) TX power down override (if override enable is set)
346 // 0x00001000 [12] RX_PD (0) RX power down override (if override enable is set)
347 // 0x00000800 [11] TX_DM (0) Output data
348 // 0x00000400 [10] TX_DP (0) Output data
349 // 0x00000200 [9] TX_DM_OE (0) Output enable
350 // 0x00000100 [8] TX_DP_OE (0) Output enable
351 // 0x00000040 [6] DM_PULLDN_EN (0) DM pull down enable
352 // 0x00000020 [5] DM_PULLUP_EN (0) DM pull up enable
353 // 0x00000010 [4] DM_PULLUP_HISEL (0) Enable the second DM pull up resistor
354 // 0x00000004 [2] DP_PULLDN_EN (0) DP pull down enable
355 // 0x00000002 [1] DP_PULLUP_EN (0) DP pull up enable
356 // 0x00000001 [0] DP_PULLUP_HISEL (0) Enable the second DP pull up resistor
357 io_rw_32 phy_direct;
358
359 _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE
360 // Override enable for each control in usbphy_direct
361 // 0x00040000 [18] RX_DM_OVERRIDE_EN (0)
362 // 0x00020000 [17] RX_DP_OVERRIDE_EN (0)
363 // 0x00010000 [16] RX_DD_OVERRIDE_EN (0)
364 // 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0)
365 // 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0)
366 // 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0)
367 // 0x00000400 [10] TX_PD_OVERRIDE_EN (0)
368 // 0x00000200 [9] RX_PD_OVERRIDE_EN (0)
369 // 0x00000100 [8] TX_DM_OVERRIDE_EN (0)
370 // 0x00000080 [7] TX_DP_OVERRIDE_EN (0)
371 // 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0)
372 // 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0)
373 // 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0)
374 // 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0)
375 // 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0)
376 // 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0)
377 // 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0)
378 io_rw_32 phy_direct_override;
379
380 _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM
381 // Used to adjust trim values of USB phy pull down resistors
382 // 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY +
383 // 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY +
384 io_rw_32 phy_trim;
385
386 _REG_(USB_LINESTATE_TUNING_OFFSET) // USB_LINESTATE_TUNING
387 // Used for debug only
388 // 0x00000f00 [11:8] SPARE_FIX (0x0)
389 // 0x00000080 [7] DEV_LS_WAKE_FIX (1) Device - exit suspend on any non-idle signalling, not...
390 // 0x00000040 [6] DEV_RX_ERR_QUIESCE (1) Device - suppress repeated errors until the device FSM...
391 // 0x00000020 [5] SIE_RX_CHATTER_SE0_FIX (1) RX - when recovering from line chatter or bitstuff...
392 // 0x00000010 [4] SIE_RX_BITSTUFF_FIX (1) RX - when a bitstuff error is signalled by rx_dasm,...
393 // 0x00000008 [3] DEV_BUFF_CONTROL_DOUBLE_READ_FIX (1) Device - the controller FSM performs two reads of the...
394 // 0x00000004 [2] MULTI_HUB_FIX (0) Host - increase inter-packet and turnaround timeouts to...
395 // 0x00000002 [1] LINESTATE_DELAY (0) Device/Host - add an extra 1-bit debounce of linestate sampling
396 // 0x00000001 [0] RCV_DELAY (0) Device - register the received data to account for hub...
397 io_rw_32 linestate_tuning;
398
399 _REG_(USB_INTR_OFFSET) // USB_INTR
400 // Raw Interrupts
401 // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL
402 // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG
403 // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS
404 // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS
405 // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
406 // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
407 // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
408 // 0x00010000 [16] SETUP_REQ (0) Device
409 // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
410 // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
411 // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
412 // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
413 // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
414 // 0x00000400 [10] STALL (0) Source: SIE_STATUS
415 // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
416 // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
417 // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
418 // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
419 // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
420 // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
421 // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
422 // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
423 // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
424 // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
425 io_ro_32 intr;
426
427 _REG_(USB_INTE_OFFSET) // USB_INTE
428 // Interrupt Enable
429 // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL
430 // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG
431 // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS
432 // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS
433 // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
434 // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
435 // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
436 // 0x00010000 [16] SETUP_REQ (0) Device
437 // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
438 // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
439 // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
440 // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
441 // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
442 // 0x00000400 [10] STALL (0) Source: SIE_STATUS
443 // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
444 // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
445 // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
446 // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
447 // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
448 // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
449 // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
450 // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
451 // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
452 // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
453 io_rw_32 inte;
454
455 _REG_(USB_INTF_OFFSET) // USB_INTF
456 // Interrupt Force
457 // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL
458 // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG
459 // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS
460 // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS
461 // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
462 // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
463 // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
464 // 0x00010000 [16] SETUP_REQ (0) Device
465 // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
466 // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
467 // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
468 // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
469 // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
470 // 0x00000400 [10] STALL (0) Source: SIE_STATUS
471 // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
472 // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
473 // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
474 // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
475 // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
476 // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
477 // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
478 // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
479 // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
480 // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
481 io_rw_32 intf;
482
483 _REG_(USB_INTS_OFFSET) // USB_INTS
484 // Interrupt status after masking & forcing
485 // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL
486 // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG
487 // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS
488 // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS
489 // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
490 // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
491 // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
492 // 0x00010000 [16] SETUP_REQ (0) Device
493 // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
494 // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
495 // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
496 // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
497 // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
498 // 0x00000400 [10] STALL (0) Source: SIE_STATUS
499 // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
500 // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
501 // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
502 // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
503 // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
504 // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
505 // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
506 // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
507 // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
508 // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
509 io_ro_32 ints;
510
511 uint32_t _pad0[25];
512
513 _REG_(USB_SOF_TIMESTAMP_RAW_OFFSET) // USB_SOF_TIMESTAMP_RAW
514 // Device only
515 // 0x001fffff [20:0] SOF_TIMESTAMP_RAW (0x000000)
516 io_ro_32 sof_timestamp_raw;
517
518 _REG_(USB_SOF_TIMESTAMP_LAST_OFFSET) // USB_SOF_TIMESTAMP_LAST
519 // Device only
520 // 0x001fffff [20:0] SOF_TIMESTAMP_LAST (0x000000)
521 io_ro_32 sof_timestamp_last;
522
523 _REG_(USB_SM_STATE_OFFSET) // USB_SM_STATE
524 // 0x00000f00 [11:8] RX_DASM (0x0)
525 // 0x000000e0 [7:5] BC_STATE (0x0)
526 // 0x0000001f [4:0] STATE (0x00)
527 io_ro_32 sm_state;
528
529 _REG_(USB_EP_TX_ERROR_OFFSET) // USB_EP_TX_ERROR
530 // TX error count for each endpoint
531 // 0xc0000000 [31:30] EP15 (0x0)
532 // 0x30000000 [29:28] EP14 (0x0)
533 // 0x0c000000 [27:26] EP13 (0x0)
534 // 0x03000000 [25:24] EP12 (0x0)
535 // 0x00c00000 [23:22] EP11 (0x0)
536 // 0x00300000 [21:20] EP10 (0x0)
537 // 0x000c0000 [19:18] EP9 (0x0)
538 // 0x00030000 [17:16] EP8 (0x0)
539 // 0x0000c000 [15:14] EP7 (0x0)
540 // 0x00003000 [13:12] EP6 (0x0)
541 // 0x00000c00 [11:10] EP5 (0x0)
542 // 0x00000300 [9:8] EP4 (0x0)
543 // 0x000000c0 [7:6] EP3 (0x0)
544 // 0x00000030 [5:4] EP2 (0x0)
545 // 0x0000000c [3:2] EP1 (0x0)
546 // 0x00000003 [1:0] EP0 (0x0)
547 io_rw_32 ep_tx_error;
548
549 _REG_(USB_EP_RX_ERROR_OFFSET) // USB_EP_RX_ERROR
550 // RX error count for each endpoint
551 // 0x80000000 [31] EP15_SEQ (0)
552 // 0x40000000 [30] EP15_TRANSACTION (0)
553 // 0x20000000 [29] EP14_SEQ (0)
554 // 0x10000000 [28] EP14_TRANSACTION (0)
555 // 0x08000000 [27] EP13_SEQ (0)
556 // 0x04000000 [26] EP13_TRANSACTION (0)
557 // 0x02000000 [25] EP12_SEQ (0)
558 // 0x01000000 [24] EP12_TRANSACTION (0)
559 // 0x00800000 [23] EP11_SEQ (0)
560 // 0x00400000 [22] EP11_TRANSACTION (0)
561 // 0x00200000 [21] EP10_SEQ (0)
562 // 0x00100000 [20] EP10_TRANSACTION (0)
563 // 0x00080000 [19] EP9_SEQ (0)
564 // 0x00040000 [18] EP9_TRANSACTION (0)
565 // 0x00020000 [17] EP8_SEQ (0)
566 // 0x00010000 [16] EP8_TRANSACTION (0)
567 // 0x00008000 [15] EP7_SEQ (0)
568 // 0x00004000 [14] EP7_TRANSACTION (0)
569 // 0x00002000 [13] EP6_SEQ (0)
570 // 0x00001000 [12] EP6_TRANSACTION (0)
571 // 0x00000800 [11] EP5_SEQ (0)
572 // 0x00000400 [10] EP5_TRANSACTION (0)
573 // 0x00000200 [9] EP4_SEQ (0)
574 // 0x00000100 [8] EP4_TRANSACTION (0)
575 // 0x00000080 [7] EP3_SEQ (0)
576 // 0x00000040 [6] EP3_TRANSACTION (0)
577 // 0x00000020 [5] EP2_SEQ (0)
578 // 0x00000010 [4] EP2_TRANSACTION (0)
579 // 0x00000008 [3] EP1_SEQ (0)
580 // 0x00000004 [2] EP1_TRANSACTION (0)
581 // 0x00000002 [1] EP0_SEQ (0)
582 // 0x00000001 [0] EP0_TRANSACTION (0)
583 io_rw_32 ep_rx_error;
584
585 _REG_(USB_DEV_SM_WATCHDOG_OFFSET) // USB_DEV_SM_WATCHDOG
586 // Watchdog that forces the device state machine to idle and raises an interrupt if the device...
587 // 0x00100000 [20] FIRED (0)
588 // 0x00080000 [19] RESET (0) Set to 1 to forcibly reset the device state machine on...
589 // 0x00040000 [18] ENABLE (0)
590 // 0x0003ffff [17:0] LIMIT (0x00000)
591 io_rw_32 dev_sm_watchdog;
592
593} usb_hw_t;
594
595#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE)
596static_assert(sizeof (usb_hw_t) == 0x0118, "");
597
598#endif // _HARDWARE_STRUCTS_USB_H
599
address_mapped.h
usb_hw_t
Definition: usb.h:23