v2.0.0
cyw43_internal.h
1/*
2 * This file is part of the cyw43-driver
3 *
4 * Copyright (C) 2019-2022 George Robotics Pty Ltd
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright notice,
10 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 * 3. Any redistribution, use, or modification in source or binary form is done
15 * solely for personal benefit and not for any commercial purpose or for
16 * monetary gain.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS" AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 * DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT OWNER BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * This software is also available for use with certain devices under different
30 * terms, as set out in the top level LICENSE file. For commercial licensing
31 * options please email contact@georgerobotics.com.au.
32 */
33
39#ifndef CYW43_INCLUDED_CYW43_INTERNAL_H
40#define CYW43_INCLUDED_CYW43_INTERNAL_H
41
42#define BUS_FUNCTION (0)
43#define BACKPLANE_FUNCTION (1)
44#define WLAN_FUNCTION (2)
45
46 typedef struct _cyw43_int_t {
47 void *cb_data;
48
49 uint32_t startup_t0;
50 uint32_t cur_backplane_window;
51 uint8_t wwd_sdpcm_packet_transmit_sequence_number;
52 uint8_t wwd_sdpcm_last_bus_data_credit;
53 uint8_t wlan_flow_control;
54 uint16_t wwd_sdpcm_requested_ioctl_id;
55 bool bus_is_up;
56 bool had_successful_packet;
57 #if CYW43_BACKPLANE_READ_PAD_LEN_BYTES > 0
58 uint32_t spi_header[(CYW43_BACKPLANE_READ_PAD_LEN_BYTES / 4) + 1] __attribute__((aligned(4))); // Must be before spid_buf
59 #endif
60 uint8_t spid_buf[2048];
61
62 uint8_t last_ssid_joined[36];
63 // private info for the bus implementation
64 void *bus_data;
65
66 // Infineon "workaround" for f1 overflow problem
67 uint32_t last_header[2];
68 size_t last_size;
69 uint32_t last_backplane_window;
70} cyw43_int_t;
71
72static_assert(sizeof(cyw43_int_t) == sizeof(cyw43_ll_t), "");
73
74// Read/write a number of bytes.
75// These return 0 on success, <0 errno code on error.
76int cyw43_read_bytes(cyw43_int_t *self, uint32_t fn, uint32_t addr, size_t len, uint8_t *buf);
77int cyw43_write_bytes(cyw43_int_t *self, uint32_t fn, uint32_t addr, size_t len, const uint8_t *buf);
78
79// Read a single register.
80// These return 0 on success, <0 errno code on error.
81// TODO: cyw43_read_reg_u32 cannot return <0 on error with 32-bit return type.
82int cyw43_read_reg_u8(cyw43_int_t *self, uint32_t fn, uint32_t reg);
83int cyw43_read_reg_u16(cyw43_int_t *self, uint32_t fn, uint32_t reg);
84uint32_t cyw43_read_reg_u32(cyw43_int_t *self, uint32_t fn, uint32_t reg);
85
86// Write a single register.
87// These return 0 on success, <0 errno code on error.
88int cyw43_write_reg_u8(cyw43_int_t *self, uint32_t function, uint32_t reg, uint32_t val);
89int cyw43_write_reg_u16(cyw43_int_t *self, uint32_t fn, uint32_t reg, uint16_t val);
90int cyw43_write_reg_u32(cyw43_int_t *self, uint32_t function, uint32_t reg, uint32_t val);
91
92#endif // CYW43_INCLUDED_CYW43_INTERNAL_H
_cyw43_int_t
Definition: cyw43_internal.h:46
_cyw43_ll_t
Definition: cyw43_ll.h:265