v2.0.0
scb.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_SCB_H
9#define _HARDWARE_STRUCTS_SCB_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/m0plus.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
26 typedef struct {
27 _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
28 // CPUID Base Register
29 // 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM
30 // 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: +
31 // 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: +
32 // 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+
33 // 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: +
34 io_ro_32 cpuid;
35
36 _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
37 // Interrupt Control and State Register
38 // 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI
39 // 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit
40 // 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit
41 // 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit
42 // 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit
43 // 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted
44 // 0x00400000 [22] ISRPENDING (0) External interrupt pending flag
45 // 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority...
46 // 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field
47 io_rw_32 icsr;
48
49 _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
50 // Vector Table Offset Register
51 // 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address
52 io_rw_32 vtor;
53
54 _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
55 // Application Interrupt and Reset Control Register
56 // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: +
57 // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: +
58 // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to...
59 // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and...
60 io_rw_32 aircr;
61
62 _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
63 // System Control Register
64 // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: +
65 // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep...
66 // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode...
67 io_rw_32 scr;
68} armv6m_scb_hw_t;
69
70#define scb_hw ((armv6m_scb_hw_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET))
71static_assert(sizeof (armv6m_scb_hw_t) == 0x0014, "");
72
73#endif // _HARDWARE_STRUCTS_SCB_H
74
address_mapped.h
armv6m_scb_hw_t
Definition: scb.h:26