v2.0.0
uart.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_UART_H
9#define _HARDWARE_STRUCTS_UART_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/uart.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/uart.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
26 typedef struct {
27 _REG_(UART_UARTDR_OFFSET) // UART_UARTDR
28 // Data Register, UARTDR
29 // 0x00000800 [11] OE (-) Overrun error
30 // 0x00000400 [10] BE (-) Break error
31 // 0x00000200 [9] PE (-) Parity error
32 // 0x00000100 [8] FE (-) Framing error
33 // 0x000000ff [7:0] DATA (-) Receive (read) data character
34 io_rw_32 dr;
35
36 _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR
37 // Receive Status Register/Error Clear Register, UARTRSR/UARTECR
38 // 0x00000008 [3] OE (0) Overrun error
39 // 0x00000004 [2] BE (0) Break error
40 // 0x00000002 [1] PE (0) Parity error
41 // 0x00000001 [0] FE (0) Framing error
42 io_rw_32 rsr;
43
44 uint32_t _pad0[4];
45
46 _REG_(UART_UARTFR_OFFSET) // UART_UARTFR
47 // Flag Register, UARTFR
48 // 0x00000100 [8] RI (-) Ring indicator
49 // 0x00000080 [7] TXFE (1) Transmit FIFO empty
50 // 0x00000040 [6] RXFF (0) Receive FIFO full
51 // 0x00000020 [5] TXFF (0) Transmit FIFO full
52 // 0x00000010 [4] RXFE (1) Receive FIFO empty
53 // 0x00000008 [3] BUSY (0) UART busy
54 // 0x00000004 [2] DCD (-) Data carrier detect
55 // 0x00000002 [1] DSR (-) Data set ready
56 // 0x00000001 [0] CTS (-) Clear to send
57 io_ro_32 fr;
58
59 uint32_t _pad1;
60
61 _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR
62 // IrDA Low-Power Counter Register, UARTILPR
63 // 0x000000ff [7:0] ILPDVSR (0x00) 8-bit low-power divisor value
64 io_rw_32 ilpr;
65
66 _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD
67 // Integer Baud Rate Register, UARTIBRD
68 // 0x0000ffff [15:0] BAUD_DIVINT (0x0000) The integer baud rate divisor
69 io_rw_32 ibrd;
70
71 _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD
72 // Fractional Baud Rate Register, UARTFBRD
73 // 0x0000003f [5:0] BAUD_DIVFRAC (0x00) The fractional baud rate divisor
74 io_rw_32 fbrd;
75
76 _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H
77 // Line Control Register, UARTLCR_H
78 // 0x00000080 [7] SPS (0) Stick parity select
79 // 0x00000060 [6:5] WLEN (0x0) Word length
80 // 0x00000010 [4] FEN (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)...
81 // 0x00000008 [3] STP2 (0) Two stop bits select
82 // 0x00000004 [2] EPS (0) Even parity select
83 // 0x00000002 [1] PEN (0) Parity enable: 0 = parity is disabled and no parity bit...
84 // 0x00000001 [0] BRK (0) Send break
85 io_rw_32 lcr_h;
86
87 _REG_(UART_UARTCR_OFFSET) // UART_UARTCR
88 // Control Register, UARTCR
89 // 0x00008000 [15] CTSEN (0) CTS hardware flow control enable
90 // 0x00004000 [14] RTSEN (0) RTS hardware flow control enable
91 // 0x00002000 [13] OUT2 (0) This bit is the complement of the UART Out2 (nUARTOut2)...
92 // 0x00001000 [12] OUT1 (0) This bit is the complement of the UART Out1 (nUARTOut1)...
93 // 0x00000800 [11] RTS (0) Request to send
94 // 0x00000400 [10] DTR (0) Data transmit ready
95 // 0x00000200 [9] RXE (1) Receive enable
96 // 0x00000100 [8] TXE (1) Transmit enable
97 // 0x00000080 [7] LBE (0) Loopback enable
98 // 0x00000004 [2] SIRLP (0) SIR low-power IrDA mode
99 // 0x00000002 [1] SIREN (0) SIR enable: 0 = IrDA SIR ENDEC is disabled
100 // 0x00000001 [0] UARTEN (0) UART enable: 0 = UART is disabled
101 io_rw_32 cr;
102
103 _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS
104 // Interrupt FIFO Level Select Register, UARTIFLS
105 // 0x00000038 [5:3] RXIFLSEL (0x2) Receive interrupt FIFO level select
106 // 0x00000007 [2:0] TXIFLSEL (0x2) Transmit interrupt FIFO level select
107 io_rw_32 ifls;
108
109 _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC
110 // Interrupt Mask Set/Clear Register, UARTIMSC
111 // 0x00000400 [10] OEIM (0) Overrun error interrupt mask
112 // 0x00000200 [9] BEIM (0) Break error interrupt mask
113 // 0x00000100 [8] PEIM (0) Parity error interrupt mask
114 // 0x00000080 [7] FEIM (0) Framing error interrupt mask
115 // 0x00000040 [6] RTIM (0) Receive timeout interrupt mask
116 // 0x00000020 [5] TXIM (0) Transmit interrupt mask
117 // 0x00000010 [4] RXIM (0) Receive interrupt mask
118 // 0x00000008 [3] DSRMIM (0) nUARTDSR modem interrupt mask
119 // 0x00000004 [2] DCDMIM (0) nUARTDCD modem interrupt mask
120 // 0x00000002 [1] CTSMIM (0) nUARTCTS modem interrupt mask
121 // 0x00000001 [0] RIMIM (0) nUARTRI modem interrupt mask
122 io_rw_32 imsc;
123
124 _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS
125 // Raw Interrupt Status Register, UARTRIS
126 // 0x00000400 [10] OERIS (0) Overrun error interrupt status
127 // 0x00000200 [9] BERIS (0) Break error interrupt status
128 // 0x00000100 [8] PERIS (0) Parity error interrupt status
129 // 0x00000080 [7] FERIS (0) Framing error interrupt status
130 // 0x00000040 [6] RTRIS (0) Receive timeout interrupt status
131 // 0x00000020 [5] TXRIS (0) Transmit interrupt status
132 // 0x00000010 [4] RXRIS (0) Receive interrupt status
133 // 0x00000008 [3] DSRRMIS (-) nUARTDSR modem interrupt status
134 // 0x00000004 [2] DCDRMIS (-) nUARTDCD modem interrupt status
135 // 0x00000002 [1] CTSRMIS (-) nUARTCTS modem interrupt status
136 // 0x00000001 [0] RIRMIS (-) nUARTRI modem interrupt status
137 io_ro_32 ris;
138
139 _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS
140 // Masked Interrupt Status Register, UARTMIS
141 // 0x00000400 [10] OEMIS (0) Overrun error masked interrupt status
142 // 0x00000200 [9] BEMIS (0) Break error masked interrupt status
143 // 0x00000100 [8] PEMIS (0) Parity error masked interrupt status
144 // 0x00000080 [7] FEMIS (0) Framing error masked interrupt status
145 // 0x00000040 [6] RTMIS (0) Receive timeout masked interrupt status
146 // 0x00000020 [5] TXMIS (0) Transmit masked interrupt status
147 // 0x00000010 [4] RXMIS (0) Receive masked interrupt status
148 // 0x00000008 [3] DSRMMIS (-) nUARTDSR modem masked interrupt status
149 // 0x00000004 [2] DCDMMIS (-) nUARTDCD modem masked interrupt status
150 // 0x00000002 [1] CTSMMIS (-) nUARTCTS modem masked interrupt status
151 // 0x00000001 [0] RIMMIS (-) nUARTRI modem masked interrupt status
152 io_ro_32 mis;
153
154 _REG_(UART_UARTICR_OFFSET) // UART_UARTICR
155 // Interrupt Clear Register, UARTICR
156 // 0x00000400 [10] OEIC (-) Overrun error interrupt clear
157 // 0x00000200 [9] BEIC (-) Break error interrupt clear
158 // 0x00000100 [8] PEIC (-) Parity error interrupt clear
159 // 0x00000080 [7] FEIC (-) Framing error interrupt clear
160 // 0x00000040 [6] RTIC (-) Receive timeout interrupt clear
161 // 0x00000020 [5] TXIC (-) Transmit interrupt clear
162 // 0x00000010 [4] RXIC (-) Receive interrupt clear
163 // 0x00000008 [3] DSRMIC (-) nUARTDSR modem interrupt clear
164 // 0x00000004 [2] DCDMIC (-) nUARTDCD modem interrupt clear
165 // 0x00000002 [1] CTSMIC (-) nUARTCTS modem interrupt clear
166 // 0x00000001 [0] RIMIC (-) nUARTRI modem interrupt clear
167 io_rw_32 icr;
168
169 _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR
170 // DMA Control Register, UARTDMACR
171 // 0x00000004 [2] DMAONERR (0) DMA on error
172 // 0x00000002 [1] TXDMAE (0) Transmit DMA enable
173 // 0x00000001 [0] RXDMAE (0) Receive DMA enable
174 io_rw_32 dmacr;
175} uart_hw_t;
176
177#define uart0_hw ((uart_hw_t *)UART0_BASE)
178#define uart1_hw ((uart_hw_t *)UART1_BASE)
179static_assert(sizeof (uart_hw_t) == 0x004c, "");
180
181#endif // _HARDWARE_STRUCTS_UART_H
182
address_mapped.h
uart_hw_t
Definition: uart.h:26