v2.0.0-develop
io_qspi.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_IO_QSPI_H
9#define _HARDWARE_STRUCTS_IO_QSPI_H
10
11#include "hardware/address_mapped.h"
12#include "hardware/regs/io_qspi.h"
13
14// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_qspi
15//
16// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
17// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
18//
19// Bit-field descriptions are of the form:
20// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
21
22enum gpio_function1 {
23 GPIO_FUNC1_XIP = 0,
24 GPIO_FUNC1_UART = 2,
25 GPIO_FUNC1_I2C = 3,
26 GPIO_FUNC1_SIO = 5,
27 GPIO_FUNC1_UART_AUX = 11,
28 GPIO_FUNC1_NULL = 0x1f,
29};
30
31 typedef struct {
32 _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
33 // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
34 // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied
35 // 0x00002000 [13] OETOPAD (0) output enable to pad after register overide is applied
36 // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register overide is applied
37 io_ro_32 status;
38
39 _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
40 // 0x30000000 [29:28] IRQOVER (0x0)
41 // 0x00030000 [17:16] INOVER (0x0)
42 // 0x0000c000 [15:14] OEOVER (0x0)
43 // 0x00003000 [13:12] OUTOVER (0x0)
44 // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
45 io_rw_32 ctrl;
46
47} io_qspi_status_ctrl_hw_t;
48
49 typedef struct {
50 _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
51 // Interrupt Enable for proc0
52 // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
53 // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
54 // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
55 // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
56 // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
57 // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
58 // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
59 // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
60 // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
61 // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
62 // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
63 // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
64 // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
65 // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
66 // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
67 // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
68 // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
69 // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
70 // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
71 // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
72 // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
73 // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
74 // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
75 // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
76 // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
77 // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
78 // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
79 // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
80 // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
81 // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
82 // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
83 // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
84 io_rw_32 inte;
85
86 _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
87 // Interrupt Force for proc0
88 // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
89 // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
90 // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
91 // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
92 // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
93 // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
94 // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
95 // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
96 // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
97 // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
98 // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
99 // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
100 // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
101 // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
102 // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
103 // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
104 // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
105 // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
106 // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
107 // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
108 // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
109 // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
110 // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
111 // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
112 // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
113 // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
114 // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
115 // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
116 // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
117 // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
118 // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
119 // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
120 io_rw_32 intf;
121
122 _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
123 // Interrupt status after masking & forcing for proc0
124 // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
125 // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
126 // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
127 // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
128 // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
129 // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
130 // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
131 // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
132 // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
133 // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
134 // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
135 // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
136 // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
137 // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
138 // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
139 // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
140 // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
141 // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
142 // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
143 // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
144 // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
145 // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
146 // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
147 // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
148 // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
149 // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
150 // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
151 // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
152 // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
153 // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
154 // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
155 // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
156 io_ro_32 ints;
157
158} io_qspi_irq_ctrl_hw_t;
159
160 typedef struct {
161 _REG_(IO_QSPI_USBPHY_DP_STATUS_OFFSET) // IO_QSPI_USBPHY_DP_STATUS
162 // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
163 // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied
164 // 0x00002000 [13] OETOPAD (0) output enable to pad after register overide is applied
165 // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register overide is applied
166 io_ro_32 usbphy_dp_status;
167
168 _REG_(IO_QSPI_USBPHY_DP_CTRL_OFFSET) // IO_QSPI_USBPHY_DP_CTRL
169 // 0x30000000 [29:28] IRQOVER (0x0)
170 // 0x00030000 [17:16] INOVER (0x0)
171 // 0x0000c000 [15:14] OEOVER (0x0)
172 // 0x00003000 [13:12] OUTOVER (0x0)
173 // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
174 io_rw_32 usbphy_dp_ctrl;
175
176 _REG_(IO_QSPI_USBPHY_DM_STATUS_OFFSET) // IO_QSPI_USBPHY_DM_STATUS
177 // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
178 // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied
179 // 0x00002000 [13] OETOPAD (0) output enable to pad after register overide is applied
180 // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register overide is applied
181 io_ro_32 usbphy_dm_status;
182
183 _REG_(IO_QSPI_USBPHY_DM_CTRL_OFFSET) // IO_QSPI_USBPHY_DM_CTRL
184 // 0x30000000 [29:28] IRQOVER (0x0)
185 // 0x00030000 [17:16] INOVER (0x0)
186 // 0x0000c000 [15:14] OEOVER (0x0)
187 // 0x00003000 [13:12] OUTOVER (0x0)
188 // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
189 io_rw_32 usbphy_dm_ctrl;
190
191 io_qspi_status_ctrl_hw_t io[6];
192
193 uint32_t _pad0[112];
194
195 _REG_(IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_SECURE
196 // 0x00000080 [7] GPIO_QSPI_SD3 (0)
197 // 0x00000040 [6] GPIO_QSPI_SD2 (0)
198 // 0x00000020 [5] GPIO_QSPI_SD1 (0)
199 // 0x00000010 [4] GPIO_QSPI_SD0 (0)
200 // 0x00000008 [3] GPIO_QSPI_SS (0)
201 // 0x00000004 [2] GPIO_QSPI_SCLK (0)
202 // 0x00000002 [1] USBPHY_DM (0)
203 // 0x00000001 [0] USBPHY_DP (0)
204 io_ro_32 irqsummary_proc0_secure;
205
206 _REG_(IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_NONSECURE
207 // 0x00000080 [7] GPIO_QSPI_SD3 (0)
208 // 0x00000040 [6] GPIO_QSPI_SD2 (0)
209 // 0x00000020 [5] GPIO_QSPI_SD1 (0)
210 // 0x00000010 [4] GPIO_QSPI_SD0 (0)
211 // 0x00000008 [3] GPIO_QSPI_SS (0)
212 // 0x00000004 [2] GPIO_QSPI_SCLK (0)
213 // 0x00000002 [1] USBPHY_DM (0)
214 // 0x00000001 [0] USBPHY_DP (0)
215 io_ro_32 irqsummary_proc0_nonsecure;
216
217 _REG_(IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_SECURE
218 // 0x00000080 [7] GPIO_QSPI_SD3 (0)
219 // 0x00000040 [6] GPIO_QSPI_SD2 (0)
220 // 0x00000020 [5] GPIO_QSPI_SD1 (0)
221 // 0x00000010 [4] GPIO_QSPI_SD0 (0)
222 // 0x00000008 [3] GPIO_QSPI_SS (0)
223 // 0x00000004 [2] GPIO_QSPI_SCLK (0)
224 // 0x00000002 [1] USBPHY_DM (0)
225 // 0x00000001 [0] USBPHY_DP (0)
226 io_ro_32 irqsummary_proc1_secure;
227
228 _REG_(IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_NONSECURE
229 // 0x00000080 [7] GPIO_QSPI_SD3 (0)
230 // 0x00000040 [6] GPIO_QSPI_SD2 (0)
231 // 0x00000020 [5] GPIO_QSPI_SD1 (0)
232 // 0x00000010 [4] GPIO_QSPI_SD0 (0)
233 // 0x00000008 [3] GPIO_QSPI_SS (0)
234 // 0x00000004 [2] GPIO_QSPI_SCLK (0)
235 // 0x00000002 [1] USBPHY_DM (0)
236 // 0x00000001 [0] USBPHY_DP (0)
237 io_ro_32 irqsummary_proc1_nonsecure;
238
239 _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE
240 // 0x00000080 [7] GPIO_QSPI_SD3 (0)
241 // 0x00000040 [6] GPIO_QSPI_SD2 (0)
242 // 0x00000020 [5] GPIO_QSPI_SD1 (0)
243 // 0x00000010 [4] GPIO_QSPI_SD0 (0)
244 // 0x00000008 [3] GPIO_QSPI_SS (0)
245 // 0x00000004 [2] GPIO_QSPI_SCLK (0)
246 // 0x00000002 [1] USBPHY_DM (0)
247 // 0x00000001 [0] USBPHY_DP (0)
248 io_ro_32 irqsummary_dormant_wake_secure;
249
250 _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE
251 // 0x00000080 [7] GPIO_QSPI_SD3 (0)
252 // 0x00000040 [6] GPIO_QSPI_SD2 (0)
253 // 0x00000020 [5] GPIO_QSPI_SD1 (0)
254 // 0x00000010 [4] GPIO_QSPI_SD0 (0)
255 // 0x00000008 [3] GPIO_QSPI_SS (0)
256 // 0x00000004 [2] GPIO_QSPI_SCLK (0)
257 // 0x00000002 [1] USBPHY_DM (0)
258 // 0x00000001 [0] USBPHY_DP (0)
259 io_ro_32 irqsummary_dormant_wake_nonsecure;
260
261 _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
262 // Raw Interrupts
263 // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
264 // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
265 // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
266 // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
267 // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
268 // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
269 // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
270 // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
271 // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
272 // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
273 // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
274 // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
275 // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
276 // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
277 // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
278 // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
279 // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
280 // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
281 // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
282 // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
283 // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
284 // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
285 // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
286 // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
287 // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
288 // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
289 // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
290 // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
291 // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
292 // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
293 // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
294 // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
295 io_rw_32 intr;
296
297 union {
298 struct {
299 io_qspi_irq_ctrl_hw_t proc0_irq_ctrl;
300 io_qspi_irq_ctrl_hw_t proc1_irq_ctrl;
301 io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl;
302 };
303 io_qspi_irq_ctrl_hw_t irq_ctrl[3];
304};
305
306} io_qspi_hw_t;
307
308#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE)
309static_assert(sizeof (io_qspi_hw_t) == 0x0240, "");
310
311#endif // _HARDWARE_STRUCTS_IO_QSPI_H
312
address_mapped.h
io_qspi_hw_t
Definition: io_qspi.h:160
io_qspi_irq_ctrl_hw_t
Definition: io_qspi.h:49
io_qspi_status_ctrl_hw_t
Definition: io_qspi.h:31