v2.0.0-develop
sio.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_SIO_H
9#define _HARDWARE_STRUCTS_SIO_H
10
11#include "hardware/address_mapped.h"
12#include "hardware/regs/sio.h"
13#include "hardware/structs/interp.h"
14
15// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio
16//
17// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
19//
20// Bit-field descriptions are of the form:
21// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
22
23
24 typedef struct {
25 _REG_(SIO_CPUID_OFFSET) // SIO_CPUID
26 // Processor core identifier
27 // 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when...
28 io_ro_32 cpuid;
29
30 _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN
31 // Input value for GPIO0
32 // 0xffffffff [31:0] GPIO_IN (0x00000000)
33 io_ro_32 gpio_in;
34
35 _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN
36 // Input value on GPIO32
37 // 0xf0000000 [31:28] QSPI_SD (0x0) Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins
38 // 0x08000000 [27] QSPI_CSN (0) Input value on QSPI CSn pin
39 // 0x04000000 [26] QSPI_SCK (0) Input value on QSPI SCK pin
40 // 0x02000000 [25] USB_DM (0) Input value on USB D- pin
41 // 0x01000000 [24] USB_DP (0) Input value on USB D+ pin
42 // 0x0000ffff [15:0] GPIO (0x0000) Input value on GPIO32
43 io_ro_32 gpio_hi_in;
44
45 uint32_t _pad0;
46
47 _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT
48 // GPIO0
49 // 0xffffffff [31:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0
50 io_rw_32 gpio_out;
51
52 _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT
53 // Output value for GPIO32
54 // 0xf0000000 [31:28] QSPI_SD (0x0) Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins
55 // 0x08000000 [27] QSPI_CSN (0) Output value for QSPI CSn pin
56 // 0x04000000 [26] QSPI_SCK (0) Output value for QSPI SCK pin
57 // 0x02000000 [25] USB_DM (0) Output value for USB D- pin
58 // 0x01000000 [24] USB_DP (0) Output value for USB D+ pin
59 // 0x0000ffff [15:0] GPIO (0x0000) Output value for GPIO32
60 io_rw_32 gpio_hi_out;
61
62 _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET
63 // GPIO0
64 // 0xffffffff [31:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i
65 io_wo_32 gpio_set;
66
67 _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET
68 // Output value set for GPIO32
69 // 0xf0000000 [31:28] QSPI_SD (0x0)
70 // 0x08000000 [27] QSPI_CSN (0)
71 // 0x04000000 [26] QSPI_SCK (0)
72 // 0x02000000 [25] USB_DM (0)
73 // 0x01000000 [24] USB_DP (0)
74 // 0x0000ffff [15:0] GPIO (0x0000)
75 io_wo_32 gpio_hi_set;
76
77 _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR
78 // GPIO0
79 // 0xffffffff [31:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i
80 io_wo_32 gpio_clr;
81
82 _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR
83 // Output value clear for GPIO32
84 // 0xf0000000 [31:28] QSPI_SD (0x0)
85 // 0x08000000 [27] QSPI_CSN (0)
86 // 0x04000000 [26] QSPI_SCK (0)
87 // 0x02000000 [25] USB_DM (0)
88 // 0x01000000 [24] USB_DP (0)
89 // 0x0000ffff [15:0] GPIO (0x0000)
90 io_wo_32 gpio_hi_clr;
91
92 _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR
93 // GPIO0
94 // 0xffffffff [31:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i
95 io_wo_32 gpio_togl;
96
97 _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR
98 // Output value XOR for GPIO32
99 // 0xf0000000 [31:28] QSPI_SD (0x0)
100 // 0x08000000 [27] QSPI_CSN (0)
101 // 0x04000000 [26] QSPI_SCK (0)
102 // 0x02000000 [25] USB_DM (0)
103 // 0x01000000 [24] USB_DP (0)
104 // 0x0000ffff [15:0] GPIO (0x0000)
105 io_wo_32 gpio_hi_togl;
106
107 _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE
108 // GPIO0
109 // 0xffffffff [31:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0
110 io_rw_32 gpio_oe;
111
112 _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE
113 // Output enable value for GPIO32
114 // 0xf0000000 [31:28] QSPI_SD (0x0) Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2...
115 // 0x08000000 [27] QSPI_CSN (0) Output enable value for QSPI CSn pin
116 // 0x04000000 [26] QSPI_SCK (0) Output enable value for QSPI SCK pin
117 // 0x02000000 [25] USB_DM (0) Output enable value for USB D- pin
118 // 0x01000000 [24] USB_DP (0) Output enable value for USB D+ pin
119 // 0x0000ffff [15:0] GPIO (0x0000) Output enable value for GPIO32
120 io_rw_32 gpio_hi_oe;
121
122 _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET
123 // GPIO0
124 // 0xffffffff [31:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i
125 io_wo_32 gpio_oe_set;
126
127 _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET
128 // Output enable set for GPIO32
129 // 0xf0000000 [31:28] QSPI_SD (0x0)
130 // 0x08000000 [27] QSPI_CSN (0)
131 // 0x04000000 [26] QSPI_SCK (0)
132 // 0x02000000 [25] USB_DM (0)
133 // 0x01000000 [24] USB_DP (0)
134 // 0x0000ffff [15:0] GPIO (0x0000)
135 io_wo_32 gpio_hi_oe_set;
136
137 _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR
138 // GPIO0
139 // 0xffffffff [31:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i
140 io_wo_32 gpio_oe_clr;
141
142 _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR
143 // Output enable clear for GPIO32
144 // 0xf0000000 [31:28] QSPI_SD (0x0)
145 // 0x08000000 [27] QSPI_CSN (0)
146 // 0x04000000 [26] QSPI_SCK (0)
147 // 0x02000000 [25] USB_DM (0)
148 // 0x01000000 [24] USB_DP (0)
149 // 0x0000ffff [15:0] GPIO (0x0000)
150 io_wo_32 gpio_hi_oe_clr;
151
152 _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR
153 // GPIO0
154 // 0xffffffff [31:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i
155 io_wo_32 gpio_oe_togl;
156
157 _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR
158 // Output enable XOR for GPIO32
159 // 0xf0000000 [31:28] QSPI_SD (0x0)
160 // 0x08000000 [27] QSPI_CSN (0)
161 // 0x04000000 [26] QSPI_SCK (0)
162 // 0x02000000 [25] USB_DM (0)
163 // 0x01000000 [24] USB_DP (0)
164 // 0x0000ffff [15:0] GPIO (0x0000)
165 io_wo_32 gpio_hi_oe_togl;
166
167 _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST
168 // Status register for inter-core FIFOs (mailboxes).
169 // 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty
170 // 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full
171 // 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i
172 // 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i
173 io_rw_32 fifo_st;
174
175 _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR
176 // Write access to this core's TX FIFO
177 // 0xffffffff [31:0] FIFO_WR (0x00000000)
178 io_wo_32 fifo_wr;
179
180 _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD
181 // Read access to this core's RX FIFO
182 // 0xffffffff [31:0] FIFO_RD (-)
183 io_ro_32 fifo_rd;
184
185 _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST
186 // Spinlock state
187 // 0xffffffff [31:0] SPINLOCK_ST (0x00000000)
188 io_ro_32 spinlock_st;
189
190 uint32_t _pad1[8];
191
192 interp_hw_t interp[2];
193
194 // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes)
195 _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0
196 // Spinlock register 0
197 // 0xffffffff [31:0] SPINLOCK0 (0x00000000)
198 io_rw_32 spinlock[32];
199
200 _REG_(SIO_DOORBELL_OUT_SET_OFFSET) // SIO_DOORBELL_OUT_SET
201 // Trigger a doorbell interrupt on the opposite core
202 // 0x000000ff [7:0] DOORBELL_OUT_SET (0x00)
203 io_rw_32 doorbell_out_set;
204
205 _REG_(SIO_DOORBELL_OUT_CLR_OFFSET) // SIO_DOORBELL_OUT_CLR
206 // Clear doorbells which have been posted to the opposite core
207 // 0x000000ff [7:0] DOORBELL_OUT_CLR (0x00)
208 io_rw_32 doorbell_out_clr;
209
210 _REG_(SIO_DOORBELL_IN_SET_OFFSET) // SIO_DOORBELL_IN_SET
211 // Write 1s to trigger doorbell interrupts on this core
212 // 0x000000ff [7:0] DOORBELL_IN_SET (0x00)
213 io_rw_32 doorbell_in_set;
214
215 _REG_(SIO_DOORBELL_IN_CLR_OFFSET) // SIO_DOORBELL_IN_CLR
216 // Check and acknowledge doorbells posted to this core
217 // 0x000000ff [7:0] DOORBELL_IN_CLR (0x00)
218 io_rw_32 doorbell_in_clr;
219
220 _REG_(SIO_PERI_NONSEC_OFFSET) // SIO_PERI_NONSEC
221 // Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so...
222 // 0x00000020 [5] TMDS (0) IF 1, detach TMDS encoder (of this core) from the Secure...
223 // 0x00000002 [1] INTERP1 (0) If 1, detach interpolator 1 (of this core) from the...
224 // 0x00000001 [0] INTERP0 (0) If 1, detach interpolator 0 (of this core) from the...
225 io_rw_32 peri_nonsec;
226
227 uint32_t _pad2[3];
228
229 _REG_(SIO_RISCV_SOFTIRQ_OFFSET) // SIO_RISCV_SOFTIRQ
230 // Control the assertion of the standard software interrupt (MIP
231 // 0x00000200 [9] CORE1_CLR (0) Write 1 to atomically clear the core 1 software interrupt flag
232 // 0x00000100 [8] CORE0_CLR (0) Write 1 to atomically clear the core 0 software interrupt flag
233 // 0x00000002 [1] CORE1_SET (0) Write 1 to atomically set the core 1 software interrupt flag
234 // 0x00000001 [0] CORE0_SET (0) Write 1 to atomically set the core 0 software interrupt flag
235 io_rw_32 riscv_softirq;
236
237 _REG_(SIO_MTIME_CTRL_OFFSET) // SIO_MTIME_CTRL
238 // Control register for the RISC-V 64-bit Machine-mode timer
239 // 0x00000008 [3] DBGPAUSE_CORE1 (1) If 1, the timer pauses when core 1 is in the debug halt state
240 // 0x00000004 [2] DBGPAUSE_CORE0 (1) If 1, the timer pauses when core 0 is in the debug halt state
241 // 0x00000002 [1] FULLSPEED (0) If 1, increment the timer every cycle (i
242 // 0x00000001 [0] EN (1) Timer enable bit
243 io_rw_32 mtime_ctrl;
244
245 uint32_t _pad3[2];
246
247 _REG_(SIO_MTIME_OFFSET) // SIO_MTIME
248 // Read/write access to the high half of RISC-V Machine-mode timer
249 // 0xffffffff [31:0] MTIME (0x00000000)
250 io_rw_32 mtime;
251
252 _REG_(SIO_MTIMEH_OFFSET) // SIO_MTIMEH
253 // Read/write access to the high half of RISC-V Machine-mode timer
254 // 0xffffffff [31:0] MTIMEH (0x00000000)
255 io_rw_32 mtimeh;
256
257 _REG_(SIO_MTIMECMP_OFFSET) // SIO_MTIMECMP
258 // Low half of RISC-V Machine-mode timer comparator
259 // 0xffffffff [31:0] MTIMECMP (0xffffffff)
260 io_rw_32 mtimecmp;
261
262 _REG_(SIO_MTIMECMPH_OFFSET) // SIO_MTIMECMPH
263 // High half of RISC-V Machine-mode timer comparator
264 // 0xffffffff [31:0] MTIMECMPH (0xffffffff)
265 io_rw_32 mtimecmph;
266
267 _REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL
268 // Control register for TMDS encoder
269 // 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders
270 // 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle...
271 // 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read...
272 // 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE
273 // 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,...
274 // 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,...
275 // 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,...
276 // 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
277 // 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
278 // 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
279 io_rw_32 tmds_ctrl;
280
281 _REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA
282 // Write-only access to the TMDS colour data register
283 // 0xffffffff [31:0] TMDS_WDATA (0x00000000)
284 io_wo_32 tmds_wdata;
285
286 _REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE
287 // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols)
288 // 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000)
289 io_ro_32 tmds_peek_single;
290
291 _REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE
292 // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value
293 // 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000)
294 io_ro_32 tmds_pop_single;
295
296 _REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0
297 // Get lane 0 of the encoding of two pixels' worth of colour data
298 // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000)
299 io_ro_32 tmds_peek_double_l0;
300
301 _REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0
302 // Get lane 0 of the encoding of two pixels' worth of colour data
303 // 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000)
304 io_ro_32 tmds_pop_double_l0;
305
306 _REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1
307 // Get lane 1 of the encoding of two pixels' worth of colour data
308 // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000)
309 io_ro_32 tmds_peek_double_l1;
310
311 _REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1
312 // Get lane 1 of the encoding of two pixels' worth of colour data
313 // 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000)
314 io_ro_32 tmds_pop_double_l1;
315
316 _REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2
317 // Get lane 2 of the encoding of two pixels' worth of colour data
318 // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000)
319 io_ro_32 tmds_peek_double_l2;
320
321 _REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2
322 // Get lane 2 of the encoding of two pixels' worth of colour data
323 // 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000)
324 io_ro_32 tmds_pop_double_l2;
325
326} sio_hw_t;
327
328#define sio_hw ((sio_hw_t *)SIO_BASE)
329#define sio_ns_hw ((sio_hw_t *)SIO_NONSEC_BASE)
330static_assert(sizeof (sio_hw_t) == 0x01e8, "");
331
332#endif // _HARDWARE_STRUCTS_SIO_H
333
address_mapped.h
interp_hw_t
Definition: interp.h:22
sio_hw_t
Definition: sio.h:24