v2.0.0
sha256.h
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1/*
2 * Copyright (c) 2024 Raspberry Pi (Trading) Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef _HARDWARE_SHA256_H
8#define _HARDWARE_SHA256_H
9
10#include "pico.h"
11#include "hardware/structs/sha256.h"
12
28#ifdef __cplusplus
29extern "C" {
30#endif
31
32// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256, Enable/disable hardware_sha256 assertions, type=bool, default=0, group=hardware_sha256
33#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256
34#ifdef PARAM_ASSERTIONS_ENABLED_SHA256 // backwards compatibility with SDK < 2.0.0
35#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256 PARAM_ASSERTIONS_ENABLED_SHA256
36#else
37#define PARAM_ASSERTIONS_ENABLED_HARDWARE_SHA256 0
38#endif
39#endif
40
44#define SHA256_RESULT_BYTES 32
45
49 enum sha256_endianness {
50 SHA256_LITTLE_ENDIAN,
51 SHA256_BIG_ENDIAN,
52};
53
57 typedef union {
58 uint32_t words[SHA256_RESULT_BYTES/4];
59 uint8_t bytes[SHA256_RESULT_BYTES];
60} sha256_result_t;
61
69 static inline void sha256_set_dma_size(uint size_in_bytes) {
70 uint32_t val;
71 invalid_params_if(HARDWARE_SHA256, size_in_bytes != 1 && size_in_bytes != 2 && size_in_bytes != 4);
72 if (size_in_bytes == 1) {
73 val = SHA256_CSR_DMA_SIZE_VALUE_8BIT;
74 } else if (size_in_bytes == 2) {
75 val = SHA256_CSR_DMA_SIZE_VALUE_16BIT;
76 } else {
77 val = SHA256_CSR_DMA_SIZE_VALUE_32BIT;
78 }
79 hw_write_masked(&sha256_hw->csr, val << SHA256_CSR_DMA_SIZE_LSB, SHA256_CSR_DMA_SIZE_BITS);
80}
81
82
91 static inline void sha256_set_bswap(bool swap) {
92 if (swap) {
93 hw_set_bits(&sha256_hw->csr, SHA256_CSR_BSWAP_BITS);
94 } else {
95 hw_clear_bits(&sha256_hw->csr, SHA256_CSR_BSWAP_BITS);
96 }
97}
98
104 static inline void sha256_start(void) {
105 hw_set_bits(&sha256_hw->csr, SHA256_CSR_START_BITS);
106}
107
117 static inline bool sha256_is_sum_valid(void) {
118 return sha256_hw->csr & SHA256_CSR_SUM_VLD_BITS;
119}
120
129 static inline bool sha256_is_ready(void) {
130 return sha256_hw->csr & SHA256_CSR_WDATA_RDY_BITS;
131}
132
140 static inline void sha256_wait_valid_blocking(void) {
141 while (!sha256_is_sum_valid()) {
142 tight_loop_contents();
143 }
144}
145
152 static inline void sha256_wait_ready_blocking(void) {
153 while (!sha256_is_ready()) {
154 tight_loop_contents();
155 }
156}
157
165void sha256_get_result(sha256_result_t *out, enum sha256_endianness endianness);
166
174 static inline bool sha256_err_not_ready(void) {
175 return sha256_hw->csr & SHA256_CSR_ERR_WDATA_NOT_RDY_BITS;
176}
177
183 static inline void sha256_err_not_ready_clear(void) {
184 hw_clear_bits(&sha256_hw->csr, SHA256_CSR_ERR_WDATA_NOT_RDY_BITS);
185}
186
194 static inline volatile void *sha256_get_write_addr(void) {
195 return &sha256_hw->wdata;
196}
197
203 static inline void sha256_put_word(uint32_t word) {
204 sha256_hw->wdata = word;
205}
206
212 static inline void sha256_put_byte(uint8_t b) {
213 *((io_rw_8*)&sha256_hw->wdata) = b;
214}
215
216#ifdef __cplusplus
217}
218#endif
219
220#endif
hw_set_bits
static __force_inline void hw_set_bits(io_rw_32 *addr, uint32_t mask)
Atomically set the specified bits to 1 in a HW register.
Definition: address_mapped.h:135
hw_write_masked
static __force_inline void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask)
Set new values for a sub-set of the bits in a HW register.
Definition: address_mapped.h:171
hw_clear_bits
static __force_inline void hw_clear_bits(io_rw_32 *addr, uint32_t mask)
Atomically clear the specified bits to 0 in a HW register.
Definition: address_mapped.h:145
sha256_get_result
void sha256_get_result(sha256_result_t *out, enum sha256_endianness endianness)
Get the checksum result.
Definition: sha256.c:9
SHA256_RESULT_BYTES
#define SHA256_RESULT_BYTES
Size of a sha256 result in bytes.
Definition: sha256.h:44
sha256_set_bswap
static void sha256_set_bswap(bool swap)
Enable or disable byte swapping of 32-bit values.
Definition: sha256.h:91
sha256_start
static void sha256_start(void)
Prepare the hardware for a new checksum.
Definition: sha256.h:104
sha256_set_dma_size
static void sha256_set_dma_size(uint size_in_bytes)
Configure the correct DMA data size.
Definition: sha256.h:69
sha256_is_ready
static bool sha256_is_ready(void)
Check if a the hardware is ready to accept more data.
Definition: sha256.h:129
sha256_put_word
static void sha256_put_word(uint32_t word)
Write one 32bit word of data to the SHA-256 hardware.
Definition: sha256.h:203
sha256_is_sum_valid
static bool sha256_is_sum_valid(void)
Check if a valid checksum has been calculated.
Definition: sha256.h:117
sha256_wait_valid_blocking
static void sha256_wait_valid_blocking(void)
Wait until the checksum is valid.
Definition: sha256.h:140
sha256_put_byte
static void sha256_put_byte(uint8_t b)
Write one byte of data to the SHA-256 hardware.
Definition: sha256.h:212
sha256_wait_ready_blocking
static void sha256_wait_ready_blocking(void)
Wait until the hardware is ready to accept more data.
Definition: sha256.h:152
sha256_endianness
sha256_endianness
SHA-256 endianness definition used in the API.
Definition: sha256.h:49
sha256_err_not_ready
static bool sha256_err_not_ready(void)
Check if data was written before the hardware was ready.
Definition: sha256.h:174
sha256_get_write_addr
static volatile void * sha256_get_write_addr(void)
Address to write the data to be hashed.
Definition: sha256.h:194
sha256_err_not_ready_clear
static void sha256_err_not_ready_clear(void)
Clear the "not ready" error condition.
Definition: sha256.h:183
SHA256_BIG_ENDIAN
@ SHA256_BIG_ENDIAN
Big Endian.
Definition: sha256.h:51
SHA256_LITTLE_ENDIAN
@ SHA256_LITTLE_ENDIAN
Little Endian.
Definition: sha256.h:50
tight_loop_contents
static __force_inline void tight_loop_contents(void)
No-op function for the body of tight loops.
Definition: platform.h:67
pico.h
sha256_result_t
SHA-256 result generated by the API.
Definition: sha256.h:57