v2.0.0
sio.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_SIO_H
9#define _HARDWARE_STRUCTS_SIO_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/sio.h"
17#include "hardware/structs/interp.h"
18
19// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
20//
21// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
22// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
23//
24// Bit-field descriptions are of the form:
25// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
26
27
28 typedef struct {
29 _REG_(SIO_CPUID_OFFSET) // SIO_CPUID
30 // Processor core identifier
31 // 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when...
32 io_ro_32 cpuid;
33
34 _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN
35 // Input value for GPIO pins
36 // 0x3fffffff [29:0] GPIO_IN (0x00000000) Input value for GPIO0
37 io_ro_32 gpio_in;
38
39 _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN
40 // Input value for QSPI pins
41 // 0x0000003f [5:0] GPIO_HI_IN (0x00) Input value on QSPI IO in order 0
42 io_ro_32 gpio_hi_in;
43
44 uint32_t _pad0;
45
46 _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT
47 // GPIO output value
48 // 0x3fffffff [29:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0
49 io_rw_32 gpio_out;
50
51 _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET
52 // GPIO output value set
53 // 0x3fffffff [29:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i
54 io_wo_32 gpio_set;
55
56 _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR
57 // GPIO output value clear
58 // 0x3fffffff [29:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i
59 io_wo_32 gpio_clr;
60
61 _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR
62 // GPIO output value XOR
63 // 0x3fffffff [29:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i
64 io_wo_32 gpio_togl;
65
66 _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE
67 // GPIO output enable
68 // 0x3fffffff [29:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0
69 io_rw_32 gpio_oe;
70
71 _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET
72 // GPIO output enable set
73 // 0x3fffffff [29:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i
74 io_wo_32 gpio_oe_set;
75
76 _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR
77 // GPIO output enable clear
78 // 0x3fffffff [29:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i
79 io_wo_32 gpio_oe_clr;
80
81 _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR
82 // GPIO output enable XOR
83 // 0x3fffffff [29:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i
84 io_wo_32 gpio_oe_togl;
85
86 _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT
87 // QSPI output value
88 // 0x0000003f [5:0] GPIO_HI_OUT (0x00) Set output level (1/0 -> high/low) for QSPI IO0
89 io_rw_32 gpio_hi_out;
90
91 _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET
92 // QSPI output value set
93 // 0x0000003f [5:0] GPIO_HI_OUT_SET (0x00) Perform an atomic bit-set on GPIO_HI_OUT, i
94 io_wo_32 gpio_hi_set;
95
96 _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR
97 // QSPI output value clear
98 // 0x0000003f [5:0] GPIO_HI_OUT_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OUT, i
99 io_wo_32 gpio_hi_clr;
100
101 _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR
102 // QSPI output value XOR
103 // 0x0000003f [5:0] GPIO_HI_OUT_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OUT, i
104 io_wo_32 gpio_hi_togl;
105
106 _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE
107 // QSPI output enable
108 // 0x0000003f [5:0] GPIO_HI_OE (0x00) Set output enable (1/0 -> output/input) for QSPI IO0
109 io_rw_32 gpio_hi_oe;
110
111 _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET
112 // QSPI output enable set
113 // 0x0000003f [5:0] GPIO_HI_OE_SET (0x00) Perform an atomic bit-set on GPIO_HI_OE, i
114 io_wo_32 gpio_hi_oe_set;
115
116 _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR
117 // QSPI output enable clear
118 // 0x0000003f [5:0] GPIO_HI_OE_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OE, i
119 io_wo_32 gpio_hi_oe_clr;
120
121 _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR
122 // QSPI output enable XOR
123 // 0x0000003f [5:0] GPIO_HI_OE_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OE, i
124 io_wo_32 gpio_hi_oe_togl;
125
126 _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST
127 // Status register for inter-core FIFOs (mailboxes).
128 // 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty
129 // 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full
130 // 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i
131 // 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i
132 io_rw_32 fifo_st;
133
134 _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR
135 // Write access to this core's TX FIFO
136 // 0xffffffff [31:0] FIFO_WR (0x00000000)
137 io_wo_32 fifo_wr;
138
139 _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD
140 // Read access to this core's RX FIFO
141 // 0xffffffff [31:0] FIFO_RD (-)
142 io_ro_32 fifo_rd;
143
144 _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST
145 // Spinlock state
146 // 0xffffffff [31:0] SPINLOCK_ST (0x00000000)
147 io_ro_32 spinlock_st;
148
149 _REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND
150 // Divider unsigned dividend
151 // 0xffffffff [31:0] DIV_UDIVIDEND (0x00000000)
152 io_rw_32 div_udividend;
153
154 _REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR
155 // Divider unsigned divisor
156 // 0xffffffff [31:0] DIV_UDIVISOR (0x00000000)
157 io_rw_32 div_udivisor;
158
159 _REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND
160 // Divider signed dividend
161 // 0xffffffff [31:0] DIV_SDIVIDEND (0x00000000)
162 io_rw_32 div_sdividend;
163
164 _REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR
165 // Divider signed divisor
166 // 0xffffffff [31:0] DIV_SDIVISOR (0x00000000)
167 io_rw_32 div_sdivisor;
168
169 _REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT
170 // Divider result quotient
171 // 0xffffffff [31:0] DIV_QUOTIENT (0x00000000)
172 io_rw_32 div_quotient;
173
174 _REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER
175 // Divider result remainder
176 // 0xffffffff [31:0] DIV_REMAINDER (0x00000000)
177 io_rw_32 div_remainder;
178
179 _REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR
180 // Control and status register for divider
181 // 0x00000002 [1] DIRTY (0) Changes to 1 when any register is written, and back to 0...
182 // 0x00000001 [0] READY (1) Reads as 0 when a calculation is in progress, 1 otherwise
183 io_ro_32 div_csr;
184
185 uint32_t _pad1;
186
187 interp_hw_t interp[2];
188
189 // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes)
190 _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0
191 // Spinlock register 0
192 // 0xffffffff [31:0] SPINLOCK0 (0x00000000)
193 io_rw_32 spinlock[32];
194} sio_hw_t;
195
196#define sio_hw ((sio_hw_t *)SIO_BASE)
197static_assert(sizeof (sio_hw_t) == 0x0180, "");
198
199#endif // _HARDWARE_STRUCTS_SIO_H
200
address_mapped.h
interp_hw_t
Definition: interp.h:26
sio_hw_t
Definition: sio.h:28