v2.0.0
mpu.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_MPU_H
9#define _HARDWARE_STRUCTS_MPU_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/m33.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
26#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
27#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
28#endif
29
30typedef struct {
31 _REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE
32 // The MPU Type Register indicates how many regions the MPU `FTSSS supports
33 // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
34 // 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data...
35 io_ro_32 type;
36
37 _REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL
38 // Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled...
39 // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for...
40 // 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less...
41 // 0x00000001 [0] ENABLE (0) Enables the MPU
42 io_rw_32 ctrl;
43
44 _REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR
45 // Selects the region currently accessed by MPU_RBAR and MPU_RLAR
46 // 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR
47 io_rw_32 rnr;
48
49 _REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR
50 // Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS
51 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
52 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
53 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
54 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region
55 io_rw_32 rbar;
56
57 _REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR
58 // Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS
59 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
60 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
61 // 0x00000001 [0] EN (0) Region enable
62 io_rw_32 rlar;
63
64 _REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1
65 // Provides indirect read and write access to the base address of the MPU region selected by...
66 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
67 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
68 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
69 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region
70 io_rw_32 rbar_a1;
71
72 _REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1
73 // Provides indirect read and write access to the limit address of the currently selected MPU...
74 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
75 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
76 // 0x00000001 [0] EN (0) Region enable
77 io_rw_32 rlar_a1;
78
79 _REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2
80 // Provides indirect read and write access to the base address of the MPU region selected by...
81 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
82 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
83 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
84 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region
85 io_rw_32 rbar_a2;
86
87 _REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2
88 // Provides indirect read and write access to the limit address of the currently selected MPU...
89 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
90 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
91 // 0x00000001 [0] EN (0) Region enable
92 io_rw_32 rlar_a2;
93
94 _REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3
95 // Provides indirect read and write access to the base address of the MPU region selected by...
96 // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
97 // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
98 // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
99 // 0x00000001 [0] XN (0) Defines whether code can be executed from this region
100 io_rw_32 rbar_a3;
101
102 _REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3
103 // Provides indirect read and write access to the limit address of the currently selected MPU...
104 // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
105 // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
106 // 0x00000001 [0] EN (0) Region enable
107 io_rw_32 rlar_a3;
108
109 uint32_t _pad0;
110
111 // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes)
112 _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0
113 // Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values
114 // 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3
115 // 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2
116 // 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1
117 // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0
118 io_rw_32 mair[2];
119} mpu_hw_t;
120
121#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M33_MPU_TYPE_OFFSET))
122#define mpu_ns_hw ((mpu_hw_t *)(PPB_NONSEC_BASE + M33_MPU_TYPE_OFFSET))
123static_assert(sizeof (mpu_hw_t) == 0x0038, "");
124
125#endif // _HARDWARE_STRUCTS_MPU_H
126
address_mapped.h
mpu_hw_t
Definition: mpu.h:26