v2.0.0
sau.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_SAU_H
9#define _HARDWARE_STRUCTS_SAU_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/m33.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
26#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
27#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
28#endif
29
30 typedef struct {
31 _REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL
32 // Allows enabling of the Security Attribution Unit
33 // 0x00000002 [1] ALLNS (0) When SAU_CTRL
34 // 0x00000001 [0] ENABLE (0) Enables the SAU
35 io_rw_32 ctrl;
36
37 _REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE
38 // Indicates the number of regions implemented by the Security Attribution Unit
39 // 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions
40 io_ro_32 type;
41
42 _REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR
43 // Selects the region currently accessed by SAU_RBAR and SAU_RLAR
44 // 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR
45 io_rw_32 rnr;
46
47 _REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR
48 // Provides indirect read and write access to the base address of the currently selected SAU region
49 // 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region
50 io_rw_32 rbar;
51
52 _REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR
53 // Provides indirect read and write access to the limit address of the currently selected SAU region
54 // 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected...
55 // 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to...
56 // 0x00000001 [0] ENABLE (0) SAU region enable
57 io_rw_32 rlar;
58} armv8m_sau_hw_t;
59
60#define sau_hw ((armv8m_sau_hw_t *)(PPB_BASE + M33_SAU_CTRL_OFFSET))
61#define sau_ns_hw ((armv8m_sau_hw_t *)(PPB_NONSEC_BASE + M33_SAU_CTRL_OFFSET))
62static_assert(sizeof (armv8m_sau_hw_t) == 0x0014, "");
63
64#endif // _HARDWARE_STRUCTS_SAU_H
65
address_mapped.h
armv8m_sau_hw_t
Definition: sau.h:30