v2.0.0-develop
xip.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_XIP_H
9#define _HARDWARE_STRUCTS_XIP_H
10
11#include "hardware/address_mapped.h"
12#include "hardware/regs/xip.h"
13
14// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xip
15//
16// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
17// _REG_(x) will link to the corresponding register in hardware/regs/xip.h.
18//
19// Bit-field descriptions are of the form:
20// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
21
22 typedef struct {
23 _REG_(XIP_CTRL_OFFSET) // XIP_CTRL
24 // Cache control register
25 // 0x00000800 [11] WRITABLE_M1 (0) If 1, enable writes to XIP memory window 1 (addresses...
26 // 0x00000400 [10] WRITABLE_M0 (0) If 1, enable writes to XIP memory window 0 (addresses...
27 // 0x00000200 [9] SPLIT_WAYS (0) When 1, route all cached+Secure accesses to way 0 of the...
28 // 0x00000100 [8] MAINT_NONSEC (0) When 0, Non-secure accesses to the cache maintenance...
29 // 0x00000080 [7] NO_UNTRANSLATED_NONSEC (1) When 1, Non-secure accesses to the uncached,...
30 // 0x00000040 [6] NO_UNTRANSLATED_SEC (0) When 1, Secure accesses to the uncached, untranslated...
31 // 0x00000020 [5] NO_UNCACHED_NONSEC (0) When 1, Non-secure accesses to the uncached window...
32 // 0x00000010 [4] NO_UNCACHED_SEC (0) When 1, Secure accesses to the uncached window...
33 // 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down
34 // 0x00000002 [1] EN_NONSECURE (1) When 1, enable the cache for Non-secure accesses
35 // 0x00000001 [0] EN_SECURE (1) When 1, enable the cache for Secure accesses
36 io_rw_32 ctrl;
37
38 uint32_t _pad0;
39
40 _REG_(XIP_STAT_OFFSET) // XIP_STAT
41 // 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full
42 // 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty
43 io_ro_32 stat;
44
45 _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT
46 // Cache Hit counter
47 // 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each...
48 io_rw_32 ctr_hit;
49
50 _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC
51 // Cache Access counter
52 // 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each...
53 io_rw_32 ctr_acc;
54
55 _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR
56 // FIFO stream address
57 // 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash...
58 io_rw_32 stream_addr;
59
60 _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR
61 // FIFO stream control
62 // 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read
63 io_rw_32 stream_ctr;
64
65 _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO
66 // FIFO stream data
67 // 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA
68 io_ro_32 stream_fifo;
69
70} xip_hw_t;
71
72#define xip_hw ((xip_hw_t *)XIP_BASE)
73static_assert(sizeof (xip_hw_t) == 0x0020, "");
74
75#endif // _HARDWARE_STRUCTS_XIP_H
76
address_mapped.h
stat
Definition: stat.h:12
xip_hw_t
Definition: xip.h:22