v2.0.0
rosc.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_ROSC_H
9#define _HARDWARE_STRUCTS_ROSC_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/rosc.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_rosc
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
26typedef struct {
27 _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
28 // Ring Oscillator control
29 // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE +
30 // 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring +
31 io_rw_32 ctrl;
32
33 _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
34 // Ring Oscillator frequency control A
35 // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
36 // 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength
37 // 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength
38 // 0x00000080 [7] DS1_RANDOM (0) Randomises the stage 1 drive strength
39 // 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength
40 // 0x00000008 [3] DS0_RANDOM (0) Randomises the stage 0 drive strength
41 // 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength
42 io_rw_32 freqa;
43
44 _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
45 // Ring Oscillator frequency control B
46 // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
47 // 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength
48 // 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength
49 // 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength
50 // 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength
51 io_rw_32 freqb;
52
53 _REG_(ROSC_RANDOM_OFFSET) // ROSC_RANDOM
54 // Loads a value to the LFSR randomiser
55 // 0xffffffff [31:0] SEED (0x3f04b16d)
56 io_rw_32 random;
57
58 _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
59 // Ring Oscillator pause control
60 // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC +
61 io_rw_32 dormant;
62
63 _REG_(ROSC_DIV_OFFSET) // ROSC_DIV
64 // Controls the output divider
65 // 0x0000ffff [15:0] DIV (-) set to 0xaa00 + div where +
66 io_rw_32 div;
67
68 _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
69 // Controls the phase shifted output
70 // 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa +
71 // 0x00000008 [3] ENABLE (1) enable the phase-shifted output +
72 // 0x00000004 [2] FLIP (0) invert the phase-shifted output +
73 // 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks +
74 io_rw_32 phase;
75
76 _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
77 // Ring Oscillator Status
78 // 0x80000000 [31] STABLE (0) Oscillator is running and stable
79 // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or...
80 // 0x00010000 [16] DIV_RUNNING (-) post-divider is running +
81 // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable +
82 io_rw_32 status;
83
84 _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
85 // Returns a 1 bit random value
86 // 0x00000001 [0] RANDOMBIT (1)
87 io_ro_32 randombit;
88
89 _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
90 // A down counter running at the ROSC frequency which counts to zero and stops.
91 // 0x0000ffff [15:0] COUNT (0x0000)
92 io_rw_32 count;
93} rosc_hw_t;
94
95#define rosc_hw ((rosc_hw_t *)ROSC_BASE)
96static_assert(sizeof (rosc_hw_t) == 0x0028, "");
97
98#endif // _HARDWARE_STRUCTS_ROSC_H
99
address_mapped.h
rosc_hw_t
Definition: rosc.h:26