v2.0.0
pll.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_PLL_H
9#define _HARDWARE_STRUCTS_PLL_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/pll.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/pll.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
27 typedef struct {
28 _REG_(PLL_CS_OFFSET) // PLL_CS
29 // Control and Status
30 // 0x80000000 [31] LOCK (0) PLL is locked
31 // 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the...
32 // 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock
33 io_rw_32 cs;
34
35 _REG_(PLL_PWR_OFFSET) // PLL_PWR
36 // Controls the PLL power modes
37 // 0x00000020 [5] VCOPD (1) PLL VCO powerdown +
38 // 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown +
39 // 0x00000004 [2] DSMPD (1) PLL DSM powerdown +
40 // 0x00000001 [0] PD (1) PLL powerdown +
41 io_rw_32 pwr;
42
43 _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT
44 // Feedback divisor
45 // 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints
46 io_rw_32 fbdiv_int;
47
48 _REG_(PLL_PRIM_OFFSET) // PLL_PRIM
49 // Controls the PLL post dividers for the primary output
50 // 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7
51 // 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7
52 io_rw_32 prim;
53} pll_hw_t;
55
56#define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE)
57#define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE)
58static_assert(sizeof (pll_hw_t) == 0x0010, "");
59
60#endif // _HARDWARE_STRUCTS_PLL_H
61
address_mapped.h
pll_hw_t
Definition: pll.h:27