v2.0.0
pio.h
Go to the documentation of this file.
1/*
2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef _HARDWARE_PIO_H
8#define _HARDWARE_PIO_H
9
10#include "pico.h"
11#include "hardware/address_mapped.h"
12#include "hardware/structs/pio.h"
13#include "hardware/gpio.h"
14#include "hardware/regs/dreq.h"
15#include "hardware/pio_instructions.h"
16
17// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO, Enable/disable assertions in the hardware_pio module, type=bool, default=0, group=hardware_pio
18#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO
19#ifdef PARAM_ASSERTIONS_ENABLED_PIO // backwards compatibility with SDK < 2.0.0
20#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO PARAM_ASSERTIONS_ENABLED_PIO
21#else
22#define PARAM_ASSERTIONS_ENABLED_HARDWARE_PIO 0
23#endif
24#endif
25
26// PICO_CONFIG: PICO_PIO_VERSION, The PIO hardware version, type=int, default=0 on RP2040 and 1 on RP2350, group=hardware_pio
27#ifndef PICO_PIO_VERSION
28#if PIO_GPIOBASE_BITS
29#define PICO_PIO_VERSION 1
30#else
31#define PICO_PIO_VERSION 0
32#endif
33#endif
68#ifdef __cplusplus
69extern "C" {
70#endif
71
72static_assert(PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB == PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB + 1, "");
73
77 enum pio_fifo_join {
78 PIO_FIFO_JOIN_NONE = 0,
79 PIO_FIFO_JOIN_TX = 1,
80 PIO_FIFO_JOIN_RX = 2,
81#if PICO_PIO_VERSION > 0
82 PIO_FIFO_JOIN_TXGET = 4,
83 PIO_FIFO_JOIN_TXPUT = 8,
84 PIO_FIFO_JOIN_PUTGET = 12,
85#endif
86};
87
91 enum pio_mov_status_type {
92 STATUS_TX_LESSTHAN = 0,
93 STATUS_RX_LESSTHAN = 1,
94#if PICO_PIO_VERSION > 0
95 STATUS_IRQ_SET = 2
96#endif
97};
98
99typedef pio_hw_t *PIO;
100
107#define pio0 pio0_hw
108
115#define pio1 pio1_hw
116
117#if NUM_PIOS > 2
124#define pio2 pio2_hw
125#endif
126
127#if PICO_PIO_VERSION > 0
128#ifndef PICO_PIO_USE_GPIO_BASE
129// PICO_CONFIG: PICO_PIO_USE_GPIO_BASE, Enable code for handling more than 32 PIO pins, type=bool, default=true when supported and when the device has more than 32 pins, group=hardware_pio
130#define PICO_PIO_USE_GPIO_BASE ((NUM_BANK0_GPIOS) > 32)
131#endif
132#endif
133
142#ifndef PIO_NUM
143static_assert(PIO1_BASE - PIO0_BASE == (1u << 20), "hardware layout mismatch");
144#define PIO_NUM(pio) (((uintptr_t)(pio) - PIO0_BASE) >> 20)
145#endif
146
155#ifndef PIO_INSTANCE
156static_assert(PIO1_BASE - PIO0_BASE == (1u << 20), "hardware layout mismatch");
157#define PIO_INSTANCE(instance) ((pio_hw_t *)(PIO0_BASE + (instance) * (1u << 20)))
158#endif
159
168#ifndef PIO_FUNCSEL_NUM
169#define PIO_FUNCSEL_NUM(pio, gpio) ((gpio_function_t) (GPIO_FUNC_PIO0 + PIO_NUM(pio)))
170#endif
171
181#ifndef PIO_DREQ_NUM
182static_assert(DREQ_PIO0_TX1 == DREQ_PIO0_TX0 + 1, "");
183static_assert(DREQ_PIO0_TX2 == DREQ_PIO0_TX0 + 2, "");
184static_assert(DREQ_PIO0_TX3 == DREQ_PIO0_TX0 + 3, "");
185static_assert(DREQ_PIO0_RX0 == DREQ_PIO0_TX0 + NUM_PIO_STATE_MACHINES, "");
186static_assert(DREQ_PIO1_RX0 == DREQ_PIO1_TX0 + NUM_PIO_STATE_MACHINES, "");
187#define PIO_DREQ_NUM(pio, sm, is_tx) ((sm) + (((is_tx) ? 0 : NUM_PIO_STATE_MACHINES) + PIO_NUM(pio) * (DREQ_PIO1_TX0 - DREQ_PIO0_TX0)))
188#endif
189
198#ifndef PIO_IRQ_NUM
199#define PIO_IRQ_NUM(pio, irqn) (PIO0_IRQ_0 + NUM_PIO_IRQS * PIO_NUM(pio) + (irqn))
200#endif
201
217 typedef struct {
218 uint32_t clkdiv;
219 uint32_t execctrl;
220 uint32_t shiftctrl;
221 uint32_t pinctrl;
222#if PICO_PIO_USE_GPIO_BASE
223#define PINHI_ALL_PINCTRL_LSBS ((1u << PIO_SM0_PINCTRL_IN_BASE_LSB) | (1u << PIO_SM0_PINCTRL_OUT_BASE_LSB) | \
224 (1u << PIO_SM0_PINCTRL_SET_BASE_LSB) | (1u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB))
225static_assert( 0 == (0xff000000u & (PINHI_ALL_PINCTRL_LSBS * 0x1f)), "");
226// note we put the jmp_ctrl pin starting at bit 24
227#define PINHI_ALL_PIN_LSBS ((1u << 24) | (1u << PIO_SM0_PINCTRL_IN_BASE_LSB) | (1u << PIO_SM0_PINCTRL_OUT_BASE_LSB) | \
228 (1u << PIO_SM0_PINCTRL_SET_BASE_LSB) | (1u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB))
229 // each 5-bit field which would usually be used for the pin_base in pin_ctrl, is used for:
230 // 0b11111 - corresponding field not specified
231 // 0b00000 - pin is in range 0-15
232 // 0b00001 - pin is in range 16-31
233 // 0b00010 - pin is in range 32-47
234 uint32_t pinhi;
235#endif
236} pio_sm_config;
237
238static inline void check_sm_param(__unused uint sm) {
239 valid_params_if(HARDWARE_PIO, sm < NUM_PIO_STATE_MACHINES);
240}
241
242static inline void check_sm_mask(__unused uint mask) {
243 valid_params_if(HARDWARE_PIO, mask < (1u << NUM_PIO_STATE_MACHINES));
244}
245
246static inline void check_pio_param(__unused PIO pio) {
247#if NUM_PIOS == 2
248 valid_params_if(HARDWARE_PIO, pio == pio0 || pio == pio1);
249#elif NUM_PIOS == 3
250 valid_params_if(HARDWARE_PIO, pio == pio0 || pio == pio1 || pio == pio2);
251#endif
252}
253
254static inline void check_pio_pin_param(__unused uint pin) {
255#if !PICO_PIO_USE_GPIO_BASE
256 invalid_params_if(HARDWARE_PIO, pin >= 32);
257#else
258 // pin base allows us to move up 16 pins at a time
259 invalid_params_if(HARDWARE_PIO, pin >= ((NUM_BANK0_GPIOS + 15u)&~15u));
260#endif
261}
262
271 static inline void sm_config_set_out_pin_base(pio_sm_config *c, uint out_base) {
272 check_pio_pin_param(out_base);
273 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_OUT_BASE_BITS) |
274 ((out_base & 31) << PIO_SM0_PINCTRL_OUT_BASE_LSB);
275#if PICO_PIO_USE_GPIO_BASE
276 c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_OUT_BASE_LSB)) |
277 ((out_base >> 4) << PIO_SM0_PINCTRL_OUT_BASE_LSB);
278#endif
279}
280
289 static inline void sm_config_set_out_pin_count(pio_sm_config *c, uint out_count) {
290 valid_params_if(HARDWARE_PIO, out_count <= 32);
291 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_OUT_COUNT_BITS) |
292 (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB);
293}
294
304 static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count) {
305 sm_config_set_out_pin_base(c, out_base);
306 sm_config_set_out_pin_count(c, out_count);
307}
308
317 static inline void sm_config_set_set_pin_base(pio_sm_config *c, uint set_base) {
318 check_pio_pin_param(set_base);
319 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SET_BASE_BITS) |
320 ((set_base & 31) << PIO_SM0_PINCTRL_SET_BASE_LSB);
321#if PICO_PIO_USE_GPIO_BASE
322 c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_SET_BASE_LSB)) |
323 ((set_base >> 4) << PIO_SM0_PINCTRL_SET_BASE_LSB);
324#endif
325}
326
335 static inline void sm_config_set_set_pin_count(pio_sm_config *c, uint set_count) {
336 valid_params_if(HARDWARE_PIO, set_count <= 5);
337 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SET_COUNT_BITS) |
338 (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB);
339}
340
350 static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count) {
351 sm_config_set_set_pin_base(c, set_base);
352 sm_config_set_set_pin_count(c, set_count);
353}
354
363 static inline void sm_config_set_in_pin_base(pio_sm_config *c, uint in_base) {
364 check_pio_pin_param(in_base);
365 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) |
366 ((in_base & 31) << PIO_SM0_PINCTRL_IN_BASE_LSB);
367#if PICO_PIO_USE_GPIO_BASE
368 c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_IN_BASE_LSB)) |
369 ((in_base >> 4) << PIO_SM0_PINCTRL_IN_BASE_LSB);
370#endif
371}
372
381 static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) {
382 sm_config_set_in_pin_base(c, in_base);
383}
384
385static inline void sm_config_set_in_pin_count(pio_sm_config *c, uint in_count) {
386#if PICO_PIO_VERSION == 0
387 // can't be changed from 32 on PIO v0
388 ((void)c);
389 valid_params_if(HARDWARE_PIO, in_count == 32);
390#else
391 valid_params_if(HARDWARE_PIO, in_count && in_count <= 32);
392 c->shiftctrl = (c->shiftctrl & ~PIO_SM0_SHIFTCTRL_IN_COUNT_BITS) |
393 ((in_count - 1) << PIO_SM0_SHIFTCTRL_IN_COUNT_LSB);
394#endif
395}
396
405 static inline void sm_config_set_sideset_pin_base(pio_sm_config *c, uint sideset_base) {
406 check_pio_pin_param(sideset_base);
407 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) |
408 ((sideset_base & 31) << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
409#if PICO_PIO_USE_GPIO_BASE
410 c->pinhi = (c->pinhi & ~(31u << PIO_SM0_PINCTRL_SIDESET_BASE_LSB)) |
411 ((sideset_base >> 4) << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
412#endif
413}
414
426 static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base) {
427 sm_config_set_sideset_pin_base(c, sideset_base);
428}
429
438 static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs) {
439 valid_params_if(HARDWARE_PIO, bit_count <= 5);
440 valid_params_if(HARDWARE_PIO, !optional || bit_count >= 1);
441 c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_COUNT_BITS) |
442 (bit_count << PIO_SM0_PINCTRL_SIDESET_COUNT_LSB);
443 c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_SIDE_EN_BITS | PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) |
444 (bool_to_bit(optional) << PIO_SM0_EXECCTRL_SIDE_EN_LSB) |
445 (bool_to_bit(pindirs) << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB);
446}
447
461 static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) {
462 invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac != 0);
463 c->clkdiv =
464 (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) |
465 (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
466}
467
468static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac) {
469 valid_params_if(HARDWARE_PIO, div >= 1 && div <= 65536);
470 *div_int = (uint16_t)div;
471 if (*div_int == 0) {
472 *div_frac = 0;
473 } else {
474 *div_frac = (uint8_t)((div - (float)*div_int) * (1u << 8u));
475 }
476}
477
493 static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) {
494 uint16_t div_int;
495 uint8_t div_frac;
496 pio_calculate_clkdiv_from_float(div, &div_int, &div_frac);
497 sm_config_set_clkdiv_int_frac(c, div_int, div_frac);
498}
499
508 static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap) {
509 valid_params_if(HARDWARE_PIO, wrap < PIO_INSTRUCTION_COUNT);
510 valid_params_if(HARDWARE_PIO, wrap_target < PIO_INSTRUCTION_COUNT);
511 c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) |
512 (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) |
513 (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB);
514}
515
522 static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) {
523 check_pio_pin_param(pin);
524 c->execctrl = (c->execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) |
525 ((pin & 31) << PIO_SM0_EXECCTRL_JMP_PIN_LSB);
526#if PICO_PIO_USE_GPIO_BASE
527 c->pinhi = (c->pinhi & ~(31u << 24)) |
528 ((pin >> 4) << 24);
529#endif
530}
531
540 static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) {
541 valid_params_if(HARDWARE_PIO, push_threshold <= 32);
542 c->shiftctrl = (c->shiftctrl &
543 ~(PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS |
544 PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS |
545 PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS)) |
546 (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) |
547 (bool_to_bit(autopush) << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) |
548 ((push_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB);
549}
550
559 static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) {
560 valid_params_if(HARDWARE_PIO, pull_threshold <= 32);
561 c->shiftctrl = (c->shiftctrl &
562 ~(PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS |
563 PIO_SM0_SHIFTCTRL_AUTOPULL_BITS |
564 PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS)) |
565 (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) |
566 (bool_to_bit(autopull) << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) |
567 ((pull_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB);
568}
569
576 static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join) {
577 valid_params_if(HARDWARE_PIO, join == PIO_FIFO_JOIN_NONE || join == PIO_FIFO_JOIN_TX || join == PIO_FIFO_JOIN_RX
578#if PICO_PIO_VERSION > 0
579 || join == PIO_FIFO_JOIN_TXPUT || join == PIO_FIFO_JOIN_TXGET || join == PIO_FIFO_JOIN_PUTGET
580#endif
581 );
582#if PICO_PIO_VERSION == 0
583 c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) |
584 (((uint)join) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB);
585#else
586 c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS |
587 PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_BITS)) |
588 (((uint)(join & 3)) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB) |
589 (((uint)(join >> 2)) << PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_LSB);
590#endif
591}
592
601 static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_pin_index) {
602 c->execctrl = (c->execctrl &
603 (uint)~(PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS |
604 PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS)) |
605 (bool_to_bit(sticky) << PIO_SM0_EXECCTRL_OUT_STICKY_LSB) |
606 (bool_to_bit(has_enable_pin) << PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) |
607 ((enable_pin_index << PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB) & PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS);
608}
609
617 static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) {
618 valid_params_if(HARDWARE_PIO,
619 status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN
620#if PICO_PIO_VERSION > 0
621 || status_sel == STATUS_IRQ_SET
622#endif
623 );
624 c->execctrl = (c->execctrl
625 & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS))
626 | ((((uint)status_sel) << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS)
627 | ((status_n << PIO_SM0_EXECCTRL_STATUS_N_LSB) & PIO_SM0_EXECCTRL_STATUS_N_BITS);
628}
629
649 static inline pio_sm_config pio_get_default_sm_config(void) {
650 pio_sm_config c = {0};
651#if PICO_PIO_USE_GPIO_BASE
652 c.pinhi = -1;
653#endif
654 sm_config_set_clkdiv_int_frac(&c, 1, 0);
655 sm_config_set_wrap(&c, 0, 31);
656 sm_config_set_in_shift(&c, true, false, 32);
657 sm_config_set_out_shift(&c, true, false, 32);
658 return c;
659}
660
671 static inline uint pio_get_gpio_base(PIO pio) {
672#if PICO_PIO_VERSION > 0
673 return pio->gpiobase;
674#else
675 ((void)pio);
676 return 0;
677#endif
678}
679
688 static inline int pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) {
689 check_pio_param(pio);
690 check_sm_param(sm);
691 pio->sm[sm].clkdiv = config->clkdiv;
692 pio->sm[sm].execctrl = config->execctrl;
693 pio->sm[sm].shiftctrl = config->shiftctrl;
694#if PICO_PIO_USE_GPIO_BASE
695 uint used = (~config->pinhi >> 4) & PINHI_ALL_PIN_LSBS;
696 // configs that use pins 0-15
697 uint gpio_under_16 = (~config->pinhi) & (~config->pinhi >> 1) & used;
698 // configs that use pins 32-47
699 uint gpio_over_32 = (config->pinhi >> 1) & used;
700 uint gpio_base = pio_get_gpio_base(pio);
701 invalid_params_if_and_return(PIO, gpio_under_16 && gpio_base, PICO_ERROR_BAD_ALIGNMENT);
702 invalid_params_if_and_return(PIO, gpio_over_32 && !gpio_base, PICO_ERROR_BAD_ALIGNMENT);
703 // flip the top bit of any used (pinctrl) values to turn:
704 // bit6(32) + 0-15 -> base(16) + 16-31
705 // bit6(0) + 16-31 -> base(16) + 0-15
706 pio->sm[sm].pinctrl = config->pinctrl ^ (gpio_base ? ((used << 12) >> 8) : 0);
707#else
708 pio->sm[sm].pinctrl = config->pinctrl;
709#endif
710 return PICO_OK;
711}
712
719 static inline uint pio_get_index(PIO pio) {
720 check_pio_param(pio);
721 return PIO_NUM(pio);
722}
723
731 static inline uint pio_get_funcsel(PIO pio) {
732 check_pio_param(pio);
733 return PIO_FUNCSEL_NUM(pio, 0); // note GPIO currently unused, so won't bother updating API
734}
735
742 static inline PIO pio_get_instance(uint instance) {
743 invalid_params_if(HARDWARE_PIO, instance >= NUM_PIOS);
744 return PIO_INSTANCE(instance);
745}
746
759 static inline void pio_gpio_init(PIO pio, uint pin) {
760 check_pio_param(pio);
761 valid_params_if(HARDWARE_PIO, pin < NUM_BANK0_GPIOS);
762 gpio_set_function(pin, PIO_FUNCSEL_NUM(pio, pin));
763}
764
772 static inline uint pio_get_dreq(PIO pio, uint sm, bool is_tx) {
773 check_pio_param(pio);
774 check_sm_param(sm);
775 return PIO_DREQ_NUM(pio, sm, is_tx);
776}
777
778 typedef struct pio_program {
779 const uint16_t *instructions;
780 uint8_t length;
781 int8_t origin; // required instruction memory origin or -1
782 uint8_t pio_version;
783#if PICO_PIO_VERSION > 0
784 uint8_t used_gpio_ranges; // bitmap with one bit per 16 pins
785#endif
786} pio_program_t;
787
799int pio_set_gpio_base(PIO pio, uint gpio_base);
800
808bool pio_can_add_program(PIO pio, const pio_program_t *program);
809
818bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset);
819
830int pio_add_program(PIO pio, const pio_program_t *program);
831
843int pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset);
844
852void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset);
853
859void pio_clear_instruction_memory(PIO pio);
860
879int pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config);
880
888 static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) {
889 check_pio_param(pio);
890 check_sm_param(sm);
891 pio->ctrl = (pio->ctrl & ~(1u << sm)) | (bool_to_bit(enabled) << sm);
892}
893
907 static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) {
908 check_pio_param(pio);
909 check_sm_mask(mask);
910 pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u);
911}
912
913#if PICO_PIO_VERSION > 0
929static inline void pio_set_sm_multi_mask_enabled(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next, bool enabled) {
930 check_pio_param(pio);
931 check_sm_mask(mask);
932 pio->ctrl = (pio->ctrl & ~(mask << PIO_CTRL_SM_ENABLE_LSB)) |
933 (enabled ? ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS) : 0) |
934 (enabled ? PIO_CTRL_NEXTPREV_SM_ENABLE_BITS : PIO_CTRL_NEXTPREV_SM_DISABLE_BITS) |
935 ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) |
936 ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS);
937
938}
939#endif
940
950 static inline void pio_sm_restart(PIO pio, uint sm) {
951 check_pio_param(pio);
952 check_sm_param(sm);
953 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_SM_RESTART_LSB + sm));
954}
955
965 static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) {
966 check_pio_param(pio);
967 check_sm_mask(mask);
968 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS);
969}
970
992 static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) {
993 check_pio_param(pio);
994 check_sm_param(sm);
995 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm));
996}
997
1027 static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) {
1028 check_pio_param(pio);
1029 check_sm_mask(mask);
1030 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS);
1031}
1032
1033#if PICO_PIO_VERSION > 0
1065static inline void pio_clkdiv_restart_sm_multi_mask(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next) {
1066 check_pio_param(pio);
1067 check_sm_mask(mask);
1068 hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
1069 PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS |
1070 ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) |
1071 ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS));
1072}
1073#endif
1074
1086 static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) {
1087 check_pio_param(pio);
1088 check_sm_mask(mask);
1089 hw_set_bits(&pio->ctrl,
1090 ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
1091 ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS));
1092}
1093
1094#if PICO_PIO_VERSION > 0
1108static inline void pio_enable_sm_multi_mask_in_sync(PIO pio, uint32_t mask_prev, uint32_t mask, uint32_t mask_next) {
1109 check_pio_param(pio);
1110 check_sm_mask(mask);
1111 check_pio_param(pio);
1112 check_sm_mask(mask);
1113 hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
1114 ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS) |
1115 PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS | PIO_CTRL_NEXTPREV_SM_ENABLE_BITS |
1116 ((mask_prev << PIO_CTRL_PREV_PIO_MASK_LSB) & PIO_CTRL_PREV_PIO_MASK_BITS) |
1117 ((mask_next << PIO_CTRL_NEXT_PIO_MASK_LSB) & PIO_CTRL_NEXT_PIO_MASK_BITS));
1118}
1119#endif
1120
1124 typedef enum pio_interrupt_source {
1125 pis_interrupt0 = PIO_INTR_SM0_LSB,
1126 pis_interrupt1 = PIO_INTR_SM1_LSB,
1127 pis_interrupt2 = PIO_INTR_SM2_LSB,
1128 pis_interrupt3 = PIO_INTR_SM3_LSB,
1129#if PICO_PIO_VERSION > 0
1130 pis_interrupt4 = PIO_INTR_SM4_LSB,
1131 pis_interrupt5 = PIO_INTR_SM5_LSB,
1132 pis_interrupt6 = PIO_INTR_SM6_LSB,
1133 pis_interrupt7 = PIO_INTR_SM7_LSB,
1134#endif
1135 pis_sm0_tx_fifo_not_full = PIO_INTR_SM0_TXNFULL_LSB,
1136 pis_sm1_tx_fifo_not_full = PIO_INTR_SM1_TXNFULL_LSB,
1137 pis_sm2_tx_fifo_not_full = PIO_INTR_SM2_TXNFULL_LSB,
1138 pis_sm3_tx_fifo_not_full = PIO_INTR_SM3_TXNFULL_LSB,
1139 pis_sm0_rx_fifo_not_empty = PIO_INTR_SM0_RXNEMPTY_LSB,
1140 pis_sm1_rx_fifo_not_empty = PIO_INTR_SM1_RXNEMPTY_LSB,
1141 pis_sm2_rx_fifo_not_empty = PIO_INTR_SM2_RXNEMPTY_LSB,
1142 pis_sm3_rx_fifo_not_empty = PIO_INTR_SM3_RXNEMPTY_LSB,
1143} pio_interrupt_source_t;
1144
1152 static inline void pio_set_irq0_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled) {
1153 check_pio_param(pio);
1154 invalid_params_if(HARDWARE_PIO, source >= 32u || (1u << source) > PIO_INTR_BITS);
1155 if (enabled)
1156 hw_set_bits(&pio->inte0, 1u << source);
1157 else
1158 hw_clear_bits(&pio->inte0, 1u << source);
1159}
1160
1168 static inline void pio_set_irq1_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled) {
1169 check_pio_param(pio);
1170 invalid_params_if(HARDWARE_PIO, source >= 32 || (1u << source) > PIO_INTR_BITS);
1171 if (enabled)
1172 hw_set_bits(&pio->inte1, 1u << source);
1173 else
1174 hw_clear_bits(&pio->inte1, 1u << source);
1175}
1176
1184 static inline void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
1185 check_pio_param(pio);
1186 invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS);
1187 if (enabled) {
1188 hw_set_bits(&pio->inte0, source_mask);
1189 } else {
1190 hw_clear_bits(&pio->inte0, source_mask);
1191 }
1192}
1193
1201 static inline void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
1202 check_pio_param(pio);
1203 invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS);
1204 if (enabled) {
1205 hw_set_bits(&pio->inte1, source_mask);
1206 } else {
1207 hw_clear_bits(&pio->inte1, source_mask);
1208 }
1209}
1210
1219 static inline void pio_set_irqn_source_enabled(PIO pio, uint irq_index, pio_interrupt_source_t source, bool enabled) {
1220 invalid_params_if(HARDWARE_PIO, irq_index > NUM_PIO_IRQS);
1221 invalid_params_if(HARDWARE_PIO, source >= 32 || (1u << source) > PIO_INTR_BITS);
1222 if (enabled)
1223 hw_set_bits(&pio->irq_ctrl[irq_index].inte, 1u << source);
1224 else
1225 hw_clear_bits(&pio->irq_ctrl[irq_index].inte, 1u << source);
1226}
1227
1236 static inline void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled) {
1237 invalid_params_if(HARDWARE_PIO, irq_index > NUM_PIO_IRQS);
1238 static_assert(NUM_PIO_IRQS == 2, "");
1239 invalid_params_if(HARDWARE_PIO, source_mask > PIO_INTR_BITS);
1240 if (enabled) {
1241 hw_set_bits(&pio->irq_ctrl[irq_index].inte, source_mask);
1242 } else {
1243 hw_clear_bits(&pio->irq_ctrl[irq_index].inte, source_mask);
1244 }
1245}
1246
1254 static inline bool pio_interrupt_get(PIO pio, uint pio_interrupt_num) {
1255 check_pio_param(pio);
1256 invalid_params_if(HARDWARE_PIO, pio_interrupt_num >= 8);
1257 return pio->irq & (1u << pio_interrupt_num);
1258}
1259
1266 static inline void pio_interrupt_clear(PIO pio, uint pio_interrupt_num) {
1267 check_pio_param(pio);
1268 invalid_params_if(HARDWARE_PIO, pio_interrupt_num >= 8);
1269 pio->irq = (1u << pio_interrupt_num);
1270}
1271
1279 static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) {
1280 check_pio_param(pio);
1281 check_sm_param(sm);
1282 return (uint8_t) pio->sm[sm].addr;
1283}
1284
1297 inline static void pio_sm_exec(PIO pio, uint sm, uint instr) {
1298 check_pio_param(pio);
1299 check_sm_param(sm);
1300 pio->sm[sm].instr = instr;
1301}
1302
1310 static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) {
1311 check_pio_param(pio);
1312 check_sm_param(sm);
1313 return pio->sm[sm].execctrl & PIO_SM0_EXECCTRL_EXEC_STALLED_BITS;
1314}
1315
1328 static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) {
1329 check_pio_param(pio);
1330 check_sm_param(sm);
1331 pio_sm_exec(pio, sm, instr);
1332 while (pio_sm_is_exec_stalled(pio, sm)) tight_loop_contents();
1333}
1334
1344 static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap) {
1345 check_pio_param(pio);
1346 check_sm_param(sm);
1347 valid_params_if(HARDWARE_PIO, wrap < PIO_INSTRUCTION_COUNT);
1348 valid_params_if(HARDWARE_PIO, wrap_target < PIO_INSTRUCTION_COUNT);
1349 pio->sm[sm].execctrl =
1350 (pio->sm[sm].execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) |
1351 (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) |
1352 (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB);
1353}
1354
1365 static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count) {
1366 check_pio_param(pio);
1367 check_sm_param(sm);
1368#if PICO_PIO_USE_GPIO_BASE
1369 out_base -= pio_get_gpio_base(pio);
1370#endif
1371 valid_params_if(HARDWARE_PIO, out_base < 32);
1372 valid_params_if(HARDWARE_PIO, out_count <= 32);
1373 pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) |
1374 (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) |
1375 (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB);
1376}
1377
1378
1389 static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count) {
1390 check_pio_param(pio);
1391 check_sm_param(sm);
1392#if PICO_PIO_USE_GPIO_BASE
1393 set_base -= pio_get_gpio_base(pio);
1394#endif
1395 valid_params_if(HARDWARE_PIO, set_base < 32);
1396 valid_params_if(HARDWARE_PIO, set_count <= 5);
1397 pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) |
1398 (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) |
1399 (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB);
1400}
1401
1411 static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) {
1412 check_pio_param(pio);
1413 check_sm_param(sm);
1414#if PICO_PIO_USE_GPIO_BASE
1415 in_base -= pio_get_gpio_base(pio);
1416#endif
1417 valid_params_if(HARDWARE_PIO, in_base < 32);
1418 pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) |
1419 (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB);
1420}
1421
1431 static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) {
1432 check_pio_param(pio);
1433 check_sm_param(sm);
1434#if PICO_PIO_USE_GPIO_BASE
1435 sideset_base -= pio_get_gpio_base(pio);
1436#endif
1437 valid_params_if(HARDWARE_PIO, sideset_base < 32);
1438 pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) |
1439 (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
1440}
1441
1450 static inline void pio_sm_set_jmp_pin(PIO pio, uint sm, uint pin) {
1451 check_pio_param(pio);
1452 check_sm_param(sm);
1453#if PICO_PIO_USE_GPIO_BASE
1454 pin -= pio_get_gpio_base(pio);
1455#endif
1456 valid_params_if(HARDWARE_PIO, pin < 32);
1457 pio->sm[sm].execctrl =
1458 (pio->sm[sm].execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS)
1459 | (pin << PIO_SM0_EXECCTRL_JMP_PIN_LSB);
1460}
1461
1476 static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) {
1477 check_pio_param(pio);
1478 check_sm_param(sm);
1479 pio->txf[sm] = data;
1480}
1481
1497 static inline uint32_t pio_sm_get(PIO pio, uint sm) {
1498 check_pio_param(pio);
1499 check_sm_param(sm);
1500 return pio->rxf[sm];
1501}
1502
1510 static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) {
1511 check_pio_param(pio);
1512 check_sm_param(sm);
1513 return (pio->fstat & (1u << (PIO_FSTAT_RXFULL_LSB + sm))) != 0;
1514}
1515
1523 static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) {
1524 check_pio_param(pio);
1525 check_sm_param(sm);
1526 return (pio->fstat & (1u << (PIO_FSTAT_RXEMPTY_LSB + sm))) != 0;
1527}
1528
1536 static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) {
1537 check_pio_param(pio);
1538 check_sm_param(sm);
1539 uint bitoffs = PIO_FLEVEL_RX0_LSB + sm * (PIO_FLEVEL_RX1_LSB - PIO_FLEVEL_RX0_LSB);
1540 const uint32_t mask = PIO_FLEVEL_RX0_BITS >> PIO_FLEVEL_RX0_LSB;
1541 return (pio->flevel >> bitoffs) & mask;
1542}
1543
1551 static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) {
1552 check_pio_param(pio);
1553 check_sm_param(sm);
1554 return (pio->fstat & (1u << (PIO_FSTAT_TXFULL_LSB + sm))) != 0;
1555}
1556
1564 static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) {
1565 check_pio_param(pio);
1566 check_sm_param(sm);
1567 return (pio->fstat & (1u << (PIO_FSTAT_TXEMPTY_LSB + sm))) != 0;
1568}
1569
1577 static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) {
1578 check_pio_param(pio);
1579 check_sm_param(sm);
1580 unsigned int bitoffs = PIO_FLEVEL_TX0_LSB + sm * (PIO_FLEVEL_TX1_LSB - PIO_FLEVEL_TX0_LSB);
1581 const uint32_t mask = PIO_FLEVEL_TX0_BITS >> PIO_FLEVEL_TX0_LSB;
1582 return (pio->flevel >> bitoffs) & mask;
1583}
1584
1592 static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) {
1593 check_pio_param(pio);
1594 check_sm_param(sm);
1595 while (pio_sm_is_tx_fifo_full(pio, sm)) tight_loop_contents();
1596 pio_sm_put(pio, sm, data);
1597}
1598
1605 static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) {
1606 check_pio_param(pio);
1607 check_sm_param(sm);
1608 while (pio_sm_is_rx_fifo_empty(pio, sm)) tight_loop_contents();
1609 return pio_sm_get(pio, sm);
1610}
1611
1625void pio_sm_drain_tx_fifo(PIO pio, uint sm);
1626
1635 static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) {
1636 check_pio_param(pio);
1637 check_sm_param(sm);
1638 invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac != 0);
1639 pio->sm[sm].clkdiv =
1640 (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) |
1641 (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
1642}
1643
1651 static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) {
1652 check_pio_param(pio);
1653 check_sm_param(sm);
1654 uint16_t div_int;
1655 uint8_t div_frac;
1656 pio_calculate_clkdiv_from_float(div, &div_int, &div_frac);
1657 pio_sm_set_clkdiv_int_frac(pio, sm, div_int, div_frac);
1658}
1659
1666 static inline void pio_sm_clear_fifos(PIO pio, uint sm) {
1667 // changing the FIFO join state clears the fifo
1668 check_pio_param(pio);
1669 check_sm_param(sm);
1670 hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS);
1671 hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS);
1672}
1673
1686void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values);
1687
1701void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask);
1702
1716void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask);
1717
1733int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pins_base, uint pin_count, bool is_out);
1734
1745void pio_sm_claim(PIO pio, uint sm);
1746
1757void pio_claim_sm_mask(PIO pio, uint sm_mask);
1758
1767void pio_sm_unclaim(PIO pio, uint sm);
1768
1777int pio_claim_unused_sm(PIO pio, bool required);
1778
1788bool pio_sm_is_claimed(PIO pio, uint sm);
1789
1800bool pio_claim_free_sm_and_add_program(const pio_program_t *program, PIO *pio, uint *sm, uint *offset);
1801
1824bool pio_claim_free_sm_and_add_program_for_gpio_range(const pio_program_t *program, PIO *pio, uint *sm, uint *offset, uint gpio_base, uint gpio_count, bool set_gpio_base);
1825
1835void pio_remove_program_and_unclaim_sm(const pio_program_t *program, PIO pio, uint sm, uint offset);
1836
1844 static inline int pio_get_irq_num(PIO pio, uint irqn) {
1845 check_pio_param(pio);
1846 valid_params_if(HARDWARE_PIO, irqn < NUM_PIO_IRQS);
1847 return PIO_IRQ_NUM(pio, irqn);
1848}
1849
1856 static inline pio_interrupt_source_t pio_get_tx_fifo_not_full_interrupt_source(uint sm) {
1857 check_sm_param(sm);
1858 return ((pio_interrupt_source_t)(pis_sm0_tx_fifo_not_full + sm));
1859}
1860
1867 static inline pio_interrupt_source_t pio_get_rx_fifo_not_empty_interrupt_source(uint sm) {
1868 check_sm_param(sm);
1869 return ((pio_interrupt_source_t)(pis_sm0_rx_fifo_not_empty + sm));
1870}
1871
1872#ifdef __cplusplus
1873}
1874#endif
1875
1876#endif // _PIO_H_
address_mapped.h
gpio.h
hw_set_bits
static __force_inline void hw_set_bits(io_rw_32 *addr, uint32_t mask)
Atomically set the specified bits to 1 in a HW register.
Definition: address_mapped.h:135
hw_xor_bits
static __force_inline void hw_xor_bits(io_rw_32 *addr, uint32_t mask)
Atomically flip the specified bits in a HW register.
Definition: address_mapped.h:155
hw_clear_bits
static __force_inline void hw_clear_bits(io_rw_32 *addr, uint32_t mask)
Atomically clear the specified bits to 0 in a HW register.
Definition: address_mapped.h:145
DREQ_PIO0_TX3
@ DREQ_PIO0_TX3
Select PIO0's TX FIFO 3 as DREQ.
Definition: dreq.h:85
DREQ_PIO1_TX0
@ DREQ_PIO1_TX0
Select PIO1's TX FIFO 0 as DREQ.
Definition: dreq.h:90
DREQ_PIO1_RX0
@ DREQ_PIO1_RX0
Select PIO1's RX FIFO 0 as DREQ.
Definition: dreq.h:94
DREQ_PIO0_TX2
@ DREQ_PIO0_TX2
Select PIO0's TX FIFO 2 as DREQ.
Definition: dreq.h:84
DREQ_PIO0_RX0
@ DREQ_PIO0_RX0
Select PIO0's RX FIFO 0 as DREQ.
Definition: dreq.h:86
DREQ_PIO0_TX1
@ DREQ_PIO0_TX1
Select PIO0's TX FIFO 1 as DREQ.
Definition: dreq.h:83
DREQ_PIO0_TX0
@ DREQ_PIO0_TX0
Select PIO0's TX FIFO 0 as DREQ.
Definition: dreq.h:82
gpio_set_function
void gpio_set_function(uint gpio, gpio_function_t fn)
Select GPIO function.
Definition: gpio.c:38
pio_sm_get_tx_fifo_level
static uint pio_sm_get_tx_fifo_level(PIO pio, uint sm)
Return the number of elements currently in a state machine's TX FIFO.
Definition: pio.h:1577
pio_claim_free_sm_and_add_program
bool pio_claim_free_sm_and_add_program(const pio_program_t *program, PIO *pio, uint *sm, uint *offset)
Finds a PIO and statemachine and adds a program into PIO memory.
Definition: pio.c:331
PIO_INSTANCE
#define PIO_INSTANCE(instance)
Returns the PIO instance with the given PIO number.
Definition: pio.h:157
pio_set_irqn_source_enabled
static void pio_set_irqn_source_enabled(PIO pio, uint irq_index, pio_interrupt_source_t source, bool enabled)
Enable/Disable a single source on a PIO's specified (0/1) IRQ index.
Definition: pio.h:1219
pio_interrupt_source
pio_interrupt_source
PIO interrupt source numbers for pio related IRQs.
Definition: pio.h:1124
pio_sm_get_blocking
static uint32_t pio_sm_get_blocking(PIO pio, uint sm)
Read a word of data from a state machine's RX FIFO, blocking if the FIFO is empty.
Definition: pio.h:1605
pio_sm_set_pins
void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values)
Use a state machine to set a value on all pins for the PIO instance.
Definition: pio.c:212
pio_add_program_at_offset
int pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset)
Attempt to load the program at the specified instruction memory offset.
Definition: pio.c:183
pio_get_instance
static PIO pio_get_instance(uint instance)
Convert PIO instance to hardware instance.
Definition: pio.h:742
pio_sm_exec_wait_blocking
static void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr)
Immediately execute an instruction on a state machine and wait for it to complete.
Definition: pio.h:1328
pio_sm_set_config
static int pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config)
Apply a state machine configuration to a state machine.
Definition: pio.h:688
pio_get_irq_num
static int pio_get_irq_num(PIO pio, uint irqn)
Return an IRQ for a PIO hardware instance.
Definition: pio.h:1844
pio_set_gpio_base
int pio_set_gpio_base(PIO pio, uint gpio_base)
Set the base GPIO base for the PIO instance.
Definition: pio.c:97
pio_mov_status_type
pio_mov_status_type
MOV status types.
Definition: pio.h:91
pio_sm_is_tx_fifo_full
static bool pio_sm_is_tx_fifo_full(PIO pio, uint sm)
Determine if a state machine's TX FIFO is full.
Definition: pio.h:1551
pio_get_dreq
static uint pio_get_dreq(PIO pio, uint sm, bool is_tx)
Return the DREQ to use for pacing transfers to/from a particular state machine FIFO.
Definition: pio.h:772
pio_set_irq1_source_enabled
static void pio_set_irq1_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled)
Enable/Disable a single source on a PIO's IRQ 1.
Definition: pio.h:1168
pio_sm_drain_tx_fifo
void pio_sm_drain_tx_fifo(PIO pio, uint sm)
Empty out a state machine's TX FIFO.
Definition: pio.c:323
pio_claim_sm_mask
void pio_claim_sm_mask(PIO pio, uint sm_mask)
Mark multiple state machines as used.
Definition: pio.c:36
pio_claim_free_sm_and_add_program_for_gpio_range
bool pio_claim_free_sm_and_add_program_for_gpio_range(const pio_program_t *program, PIO *pio, uint *sm, uint *offset, uint gpio_base, uint gpio_count, bool set_gpio_base)
Finds a PIO and statemachine and adds a program into PIO memory.
Definition: pio.c:335
pio_claim_unused_sm
int pio_claim_unused_sm(PIO pio, bool required)
Claim a free state machine on a PIO instance.
Definition: pio.c:48
pio_sm_unclaim
void pio_sm_unclaim(PIO pio, uint sm)
Mark a state machine as no longer used.
Definition: pio.c:42
pio_clkdiv_restart_sm_mask
static void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask)
Restart multiple state machines' clock dividers from a phase of 0.
Definition: pio.h:1027
pio_sm_is_claimed
bool pio_sm_is_claimed(PIO pio, uint sm)
Determine if a PIO state machine is claimed.
Definition: pio.c:57
pio_interrupt_clear
static void pio_interrupt_clear(PIO pio, uint pio_interrupt_num)
Clear a particular PIO interrupt.
Definition: pio.h:1266
pio_sm_get
static uint32_t pio_sm_get(PIO pio, uint sm)
Read a word of data from a state machine's RX FIFO.
Definition: pio.h:1497
pio_sm_is_rx_fifo_full
static bool pio_sm_is_rx_fifo_full(PIO pio, uint sm)
Determine if a state machine's RX FIFO is full.
Definition: pio.h:1510
pio_sm_set_wrap
static void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap)
Set the current wrap configuration for a state machine.
Definition: pio.h:1344
PIO_NUM
#define PIO_NUM(pio)
Returns the PIO number for a PIO instance.
Definition: pio.h:144
pio_sm_restart
static void pio_sm_restart(PIO pio, uint sm)
Restart a state machine with a known state.
Definition: pio.h:950
pio_fifo_join
pio_fifo_join
FIFO join states.
Definition: pio.h:77
pio_sm_set_out_pins
static void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count)
Set the current 'out' pins for a state machine.
Definition: pio.h:1365
pio_sm_exec
static void pio_sm_exec(PIO pio, uint sm, uint instr)
Immediately execute an instruction on a state machine.
Definition: pio.h:1297
pio_set_irq0_source_mask_enabled
static void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled)
Enable/Disable multiple sources on a PIO's IRQ 0.
Definition: pio.h:1184
pio_remove_program
void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset)
Remove a program from a PIO instance's instruction memory.
Definition: pio.c:190
pio_sm_set_pindirs_with_mask
void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask)
Use a state machine to set the pin directions for multiple pins for the PIO instance.
Definition: pio.c:252
pio_clear_instruction_memory
void pio_clear_instruction_memory(PIO pio)
Clears all of a PIO instance's instruction memory.
Definition: pio.c:199
pio_sm_set_sideset_pins
static void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base)
Set the current 'sideset' pins for a state machine.
Definition: pio.h:1431
pio_sm_set_clkdiv
static void pio_sm_set_clkdiv(PIO pio, uint sm, float div)
set the current clock divider for a state machine
Definition: pio.h:1651
pio_get_gpio_base
static uint pio_get_gpio_base(PIO pio)
Return the base GPIO base for the PIO instance.
Definition: pio.h:671
pio_get_tx_fifo_not_full_interrupt_source
static pio_interrupt_source_t pio_get_tx_fifo_not_full_interrupt_source(uint sm)
Return the interrupt source for a state machines TX FIFO not full interrupt.
Definition: pio.h:1856
pio_sm_get_rx_fifo_level
static uint pio_sm_get_rx_fifo_level(PIO pio, uint sm)
Return the number of elements currently in a state machine's RX FIFO.
Definition: pio.h:1536
pio0
#define pio0
Definition: pio.h:107
pio1
#define pio1
Definition: pio.h:115
pio_sm_set_pins_with_mask
void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask)
Use a state machine to set a value on multiple pins for the PIO instance.
Definition: pio.c:234
pio_sm_set_jmp_pin
static void pio_sm_set_jmp_pin(PIO pio, uint sm, uint pin)
Set the 'jmp' pin for a state machine.
Definition: pio.h:1450
pio_sm_get_pc
static uint8_t pio_sm_get_pc(PIO pio, uint sm)
Return the current program counter for a state machine.
Definition: pio.h:1279
pio_get_funcsel
static uint pio_get_funcsel(PIO pio)
Return the funcsel number of a PIO instance.
Definition: pio.h:731
PIO_FUNCSEL_NUM
#define PIO_FUNCSEL_NUM(pio, gpio)
Returns gpio_function_t needed to select the PIO function for the given PIO instance on the given GPI...
Definition: pio.h:169
pio_sm_set_enabled
static void pio_sm_set_enabled(PIO pio, uint sm, bool enabled)
Enable or disable a PIO state machine.
Definition: pio.h:888
pio_sm_claim
void pio_sm_claim(PIO pio, uint sm)
Mark a state machine as used.
Definition: pio.c:24
pio_remove_program_and_unclaim_sm
void pio_remove_program_and_unclaim_sm(const pio_program_t *program, PIO pio, uint sm, uint offset)
Removes a program from PIO memory and unclaims the state machine.
Definition: pio.c:391
pio_can_add_program
bool pio_can_add_program(PIO pio, const pio_program_t *program)
Determine whether the given program can (at the time of the call) be loaded onto the PIO instance.
Definition: pio.c:145
pio_interrupt_get
static bool pio_interrupt_get(PIO pio, uint pio_interrupt_num)
Determine if a particular PIO interrupt is set.
Definition: pio.h:1254
pio_sm_set_clkdiv_int_frac
static void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac)
set the current clock divider for a state machine using a 16:8 fraction
Definition: pio.h:1635
pio_sm_is_exec_stalled
static bool pio_sm_is_exec_stalled(PIO pio, uint sm)
Determine if an instruction set by pio_sm_exec() is stalled executing.
Definition: pio.h:1310
pio_can_add_program_at_offset
bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset)
Determine whether the given program can (at the time of the call) be loaded onto the PIO instance sta...
Definition: pio.c:153
pio_sm_put
static void pio_sm_put(PIO pio, uint sm, uint32_t data)
Write a word of data to a state machine's TX FIFO.
Definition: pio.h:1476
pio_sm_clear_fifos
static void pio_sm_clear_fifos(PIO pio, uint sm)
Clear a state machine's TX and RX FIFOs.
Definition: pio.h:1666
pio_interrupt_source_t
enum pio_interrupt_source pio_interrupt_source_t
PIO interrupt source numbers for pio related IRQs.
PIO_DREQ_NUM
#define PIO_DREQ_NUM(pio, sm, is_tx)
Returns the dreq_num_t used for pacing DMA transfers to or from a given state machine's FIFOs on this...
Definition: pio.h:187
pio_enable_sm_mask_in_sync
static void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask)
Enable multiple PIO state machines synchronizing their clock dividers.
Definition: pio.h:1086
pio_sm_set_set_pins
static void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count)
Set the current 'set' pins for a state machine.
Definition: pio.h:1389
pio_sm_clkdiv_restart
static void pio_sm_clkdiv_restart(PIO pio, uint sm)
Restart a state machine's clock divider from a phase of 0.
Definition: pio.h:992
pio_get_rx_fifo_not_empty_interrupt_source
static pio_interrupt_source_t pio_get_rx_fifo_not_empty_interrupt_source(uint sm)
Return the interrupt source for a state machines RX FIFO not empty interrupt.
Definition: pio.h:1867
pio_sm_is_rx_fifo_empty
static bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm)
Determine if a state machine's RX FIFO is empty.
Definition: pio.h:1523
pio_sm_is_tx_fifo_empty
static bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm)
Determine if a state machine's TX FIFO is empty.
Definition: pio.h:1564
pio_set_irq1_source_mask_enabled
static void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled)
Enable/Disable multiple sources on a PIO's IRQ 1.
Definition: pio.h:1201
pio_restart_sm_mask
static void pio_restart_sm_mask(PIO pio, uint32_t mask)
Restart multiple state machine with a known state.
Definition: pio.h:965
pio_get_index
static uint pio_get_index(PIO pio)
Return the instance number of a PIO instance.
Definition: pio.h:719
PIO_IRQ_NUM
#define PIO_IRQ_NUM(pio, irqn)
Returns the irq_num_t for processor interrupts from the given PIO instance.
Definition: pio.h:199
pio_sm_put_blocking
static void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data)
Write a word of data to a state machine's TX FIFO, blocking if the FIFO is full.
Definition: pio.h:1592
pio_sm_set_in_pins
static void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base)
Set the current 'in' pins for a state machine.
Definition: pio.h:1411
pio_add_program
int pio_add_program(PIO pio, const pio_program_t *program)
Attempt to load the program.
Definition: pio.c:173
pio_sm_set_consecutive_pindirs
int pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pins_base, uint pin_count, bool is_out)
Use a state machine to set the same pin direction for multiple consecutive pins for the PIO instance.
Definition: pio.c:270
pio_set_sm_mask_enabled
static void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled)
Enable or disable multiple PIO state machines.
Definition: pio.h:907
pio_gpio_init
static void pio_gpio_init(PIO pio, uint pin)
Setup the function select for a GPIO to use output from the given PIO instance.
Definition: pio.h:759
pio_set_irqn_source_mask_enabled
static void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled)
Enable/Disable multiple sources on a PIO's specified (0/1) IRQ index.
Definition: pio.h:1236
pio_set_irq0_source_enabled
static void pio_set_irq0_source_enabled(PIO pio, pio_interrupt_source_t source, bool enabled)
Enable/Disable a single source on a PIO's IRQ 0.
Definition: pio.h:1152
pis_interrupt2
@ pis_interrupt2
PIO interrupt 2 is raised.
Definition: pio.h:1127
pis_sm2_tx_fifo_not_full
@ pis_sm2_tx_fifo_not_full
State machine 2 TX FIFO is not full.
Definition: pio.h:1137
pis_interrupt0
@ pis_interrupt0
PIO interrupt 0 is raised.
Definition: pio.h:1125
pis_sm1_tx_fifo_not_full
@ pis_sm1_tx_fifo_not_full
State machine 1 TX FIFO is not full.
Definition: pio.h:1136
pis_sm3_tx_fifo_not_full
@ pis_sm3_tx_fifo_not_full
State machine 3 TX FIFO is not full.
Definition: pio.h:1138
pis_interrupt1
@ pis_interrupt1
PIO interrupt 1 is raised.
Definition: pio.h:1126
pis_sm2_rx_fifo_not_empty
@ pis_sm2_rx_fifo_not_empty
State machine 2 RX FIFO is not empty.
Definition: pio.h:1141
pis_sm1_rx_fifo_not_empty
@ pis_sm1_rx_fifo_not_empty
State machine 1 RX FIFO is not empty.
Definition: pio.h:1140
pis_sm0_tx_fifo_not_full
@ pis_sm0_tx_fifo_not_full
State machine 0 TX FIFO is not full.
Definition: pio.h:1135
pis_interrupt3
@ pis_interrupt3
PIO interrupt 3 is raised.
Definition: pio.h:1128
pis_sm0_rx_fifo_not_empty
@ pis_sm0_rx_fifo_not_empty
State machine 0 RX FIFO is not empty.
Definition: pio.h:1139
pis_sm3_rx_fifo_not_empty
@ pis_sm3_rx_fifo_not_empty
State machine 3 RX FIFO is not empty.
Definition: pio.h:1142
PIO_FIFO_JOIN_NONE
@ PIO_FIFO_JOIN_NONE
TX FIFO length=4 is used for transmit, RX FIFO length=4 is used for receive.
Definition: pio.h:78
PIO_FIFO_JOIN_TX
@ PIO_FIFO_JOIN_TX
TX FIFO length=8 is used for transmit, RX FIFO is disabled.
Definition: pio.h:79
PIO_FIFO_JOIN_RX
@ PIO_FIFO_JOIN_RX
RX FIFO length=8 is used for receive, TX FIFO is disabled.
Definition: pio.h:80
PICO_OK
@ PICO_OK
No error; the operation succeeded.
Definition: error.h:23
PICO_ERROR_BAD_ALIGNMENT
@ PICO_ERROR_BAD_ALIGNMENT
Address was mis-aligned (usually not on word boundary)
Definition: error.h:35
tight_loop_contents
static __force_inline void tight_loop_contents(void)
No-op function for the body of tight loops.
Definition: platform.h:67
sm_config_set_out_pin_base
static void sm_config_set_out_pin_base(pio_sm_config *c, uint out_base)
Set the base of the 'out' pins in a state machine configuration.
Definition: pio.h:271
sm_config_set_clkdiv_int_frac
static void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac)
Set the state machine clock divider (from integer and fractional parts - 16:8) in a state machine con...
Definition: pio.h:461
sm_config_set_set_pin_base
static void sm_config_set_set_pin_base(pio_sm_config *c, uint set_base)
Set the base of the 'set' pins in a state machine configuration.
Definition: pio.h:317
sm_config_set_out_shift
static void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold)
Setup 'out' shifting parameters in a state machine configuration.
Definition: pio.h:559
sm_config_set_set_pin_count
static void sm_config_set_set_pin_count(pio_sm_config *c, uint set_count)
Set the count of 'set' pins in a state machine configuration.
Definition: pio.h:335
sm_config_set_sideset_pin_base
static void sm_config_set_sideset_pin_base(pio_sm_config *c, uint sideset_base)
Set the base of the 'sideset' pins in a state machine configuration.
Definition: pio.h:405
sm_config_set_out_special
static void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_pin_index)
Set special 'out' operations in a state machine configuration.
Definition: pio.h:601
sm_config_set_in_pin_base
static void sm_config_set_in_pin_base(pio_sm_config *c, uint in_base)
Set the base of the 'in' pins in a state machine configuration.
Definition: pio.h:363
sm_config_set_in_pins
static void sm_config_set_in_pins(pio_sm_config *c, uint in_base)
Set the base fpr the 'in' pins in a state machine configuration.
Definition: pio.h:381
sm_config_set_mov_status
static void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n)
Set source for 'mov status' in a state machine configuration.
Definition: pio.h:617
sm_config_set_sideset_pins
static void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base)
Set the 'sideset' pins in a state machine configuration.
Definition: pio.h:426
sm_config_set_set_pins
static void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count)
Set the 'set' pins in a state machine configuration.
Definition: pio.h:350
sm_config_set_out_pin_count
static void sm_config_set_out_pin_count(pio_sm_config *c, uint out_count)
Set the number of 'out' pins in a state machine configuration.
Definition: pio.h:289
sm_config_set_clkdiv
static void sm_config_set_clkdiv(pio_sm_config *c, float div)
Set the state machine clock divider (from a floating point value) in a state machine configuration.
Definition: pio.h:493
sm_config_set_in_shift
static void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold)
Setup 'in' shifting parameters in a state machine configuration.
Definition: pio.h:540
sm_config_set_jmp_pin
static void sm_config_set_jmp_pin(pio_sm_config *c, uint pin)
Set the 'jmp' pin in a state machine configuration.
Definition: pio.h:522
pio_get_default_sm_config
static pio_sm_config pio_get_default_sm_config(void)
Get the default state machine configuration.
Definition: pio.h:649
sm_config_set_out_pins
static void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count)
Set the 'out' pins in a state machine configuration.
Definition: pio.h:304
sm_config_set_sideset
static void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs)
Set the 'sideset' options in a state machine configuration.
Definition: pio.h:438
sm_config_set_wrap
static void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap)
Set the wrap addresses in a state machine configuration.
Definition: pio.h:508
sm_config_set_fifo_join
static void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join)
Setup the FIFO joining in a state machine configuration.
Definition: pio.h:576
pico.h
pio_hw_t
Definition: pio.h:132
pio_program
Definition: pio.h:778
pio_sm_config
PIO Configuration structure.
Definition: pio.h:217