v2.0.0
gpio.h
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1/*
2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef _HARDWARE_GPIO_H
8#define _HARDWARE_GPIO_H
9
10#include "pico.h"
11#include "hardware/structs/sio.h"
12#include "hardware/structs/pads_bank0.h"
13#include "hardware/structs/io_bank0.h"
14#include "hardware/irq.h"
15
16// PICO_CONFIG: PICO_USE_GPIO_COPROCESSOR, Enable/disable use of the GPIO coprocessor for GPIO access, type=bool, default=1, group=hardware_gpio
17#if !defined(PICO_USE_GPIO_COPROCESSOR) && HAS_GPIO_COPROCESSOR
18#define PICO_USE_GPIO_COPROCESSOR 1
19#endif
20
21#if PICO_USE_GPIO_COPROCESSOR
22#include "hardware/gpio_coproc.h"
23#endif
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO, Enable/disable assertions in the hardware_gpio module, type=bool, default=0, group=hardware_gpio
30#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO
31#ifdef PARAM_ASSERTIONS_ENABLED_GPIO // backwards compatibility with SDK < 2.0.0
32#define PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO PARAM_ASSERTIONS_ENABLED_GPIO
33#else
34#define PARAM_ASSERTIONS_ENABLED_HARDWARE_GPIO 0
35#endif
36#endif
37
170 enum gpio_dir {
171 GPIO_OUT = 1u,
172 GPIO_IN = 0u,
173};
174
190 enum gpio_irq_level {
191 GPIO_IRQ_LEVEL_LOW = 0x1u,
192 GPIO_IRQ_LEVEL_HIGH = 0x2u,
193 GPIO_IRQ_EDGE_FALL = 0x4u,
194 GPIO_IRQ_EDGE_RISE = 0x8u,
195};
196
205 typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t event_mask);
206
207 enum gpio_override {
208 GPIO_OVERRIDE_NORMAL = 0,
209 GPIO_OVERRIDE_INVERT = 1,
210 GPIO_OVERRIDE_LOW = 2,
211 GPIO_OVERRIDE_HIGH = 3,
212};
213
221 enum gpio_slew_rate {
222 GPIO_SLEW_RATE_SLOW = 0,
223 GPIO_SLEW_RATE_FAST = 1
224};
225
232 enum gpio_drive_strength {
233 GPIO_DRIVE_STRENGTH_2MA = 0,
234 GPIO_DRIVE_STRENGTH_4MA = 1,
235 GPIO_DRIVE_STRENGTH_8MA = 2,
236 GPIO_DRIVE_STRENGTH_12MA = 3
237};
238
239static inline void check_gpio_param(__unused uint gpio) {
240 invalid_params_if(HARDWARE_GPIO, gpio >= NUM_BANK0_GPIOS);
241}
242
243// ----------------------------------------------------------------------------
244// Pad Controls + IO Muxing
245// ----------------------------------------------------------------------------
246// Declarations for gpio.c
247
254void gpio_set_function(uint gpio, gpio_function_t fn);
255
263void gpio_set_function_masked(uint32_t gpio_mask, gpio_function_t fn);
264
272void gpio_set_function_masked64(uint64_t gpio_mask, gpio_function_t fn);
273
280 gpio_function_t gpio_get_function(uint gpio);
281
292void gpio_set_pulls(uint gpio, bool up, bool down);
293
299 static inline void gpio_pull_up(uint gpio) {
300 gpio_set_pulls(gpio, true, false);
301}
302
309 static inline bool gpio_is_pulled_up(uint gpio) {
310 return (pads_bank0_hw->io[gpio] & PADS_BANK0_GPIO0_PUE_BITS) != 0;
311}
312
318 static inline void gpio_pull_down(uint gpio) {
319 gpio_set_pulls(gpio, false, true);
320}
321
328 static inline bool gpio_is_pulled_down(uint gpio) {
329 return (pads_bank0_hw->io[gpio] & PADS_BANK0_GPIO0_PDE_BITS) != 0;
330}
331
337 static inline void gpio_disable_pulls(uint gpio) {
338 gpio_set_pulls(gpio, false, false);
339}
340
349void gpio_set_irqover(uint gpio, uint value);
350
357void gpio_set_outover(uint gpio, uint value);
358
365void gpio_set_inover(uint gpio, uint value);
366
373void gpio_set_oeover(uint gpio, uint value);
374
381void gpio_set_input_enabled(uint gpio, bool enabled);
382
395void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled);
396
403bool gpio_is_input_hysteresis_enabled(uint gpio);
404
412void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew);
413
421enum gpio_slew_rate gpio_get_slew_rate(uint gpio);
422
430void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive);
431
439enum gpio_drive_strength gpio_get_drive_strength(uint gpio);
440
466void gpio_set_irq_enabled(uint gpio, uint32_t event_mask, bool enabled);
467
468// PICO_CONFIG: GPIO_IRQ_CALLBACK_ORDER_PRIORITY, IRQ priority order of the default IRQ callback, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY, group=hardware_gpio
469#ifndef GPIO_IRQ_CALLBACK_ORDER_PRIORITY
470#define GPIO_IRQ_CALLBACK_ORDER_PRIORITY PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY
471#endif
472
473// PICO_CONFIG: GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, IRQ priority order of raw IRQ handlers if the priority is not specified, min=0, max=255, default=PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, group=hardware_gpio
474#ifndef GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
475#define GPIO_RAW_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
476#endif
477
492void gpio_set_irq_callback(gpio_irq_callback_t callback);
493
525void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t event_mask, bool enabled, gpio_irq_callback_t callback);
526
537void gpio_set_dormant_irq_enabled(uint gpio, uint32_t event_mask, bool enabled);
538
546 static inline uint32_t gpio_get_irq_event_mask(uint gpio) {
547 check_gpio_param(gpio);
548 io_bank0_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
549 &io_bank0_hw->proc1_irq_ctrl : &io_bank0_hw->proc0_irq_ctrl;
550 io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio >> 3u];
551 return (*status_reg >> (4 * (gpio & 7u))) & 0xfu;
552}
553
568void gpio_acknowledge_irq(uint gpio, uint32_t event_mask);
569
603void gpio_add_raw_irq_handler_with_order_priority_masked(uint32_t gpio_mask, irq_handler_t handler, uint8_t order_priority);
604
638void gpio_add_raw_irq_handler_with_order_priority_masked64(uint64_t gpio_mask, irq_handler_t handler, uint8_t order_priority);
639
669 static inline void gpio_add_raw_irq_handler_with_order_priority(uint gpio, irq_handler_t handler, uint8_t order_priority) {
670 check_gpio_param(gpio);
671#if NUM_BANK0_GPIOS > 32
672 gpio_add_raw_irq_handler_with_order_priority_masked64(1ull << gpio, handler, order_priority);
673#else
674 gpio_add_raw_irq_handler_with_order_priority_masked(1u << gpio, handler, order_priority);
675#endif
676}
677
708void gpio_add_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler);
709
740void gpio_add_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler);
741
768 static inline void gpio_add_raw_irq_handler(uint gpio, irq_handler_t handler) {
769 check_gpio_param(gpio);
770#if NUM_BANK0_GPIOS > 32
771 gpio_add_raw_irq_handler_masked64(1ull << gpio, handler);
772#else
773 gpio_add_raw_irq_handler_masked(1u << gpio, handler);
774#endif
775}
776
788void gpio_remove_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler);
789
801void gpio_remove_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler);
802
814 static inline void gpio_remove_raw_irq_handler(uint gpio, irq_handler_t handler) {
815 check_gpio_param(gpio);
816#if NUM_BANK0_GPIOS > 32
817 gpio_remove_raw_irq_handler_masked64(1ull << gpio, handler);
818#else
819 gpio_remove_raw_irq_handler_masked(1u << gpio, handler);
820#endif
821}
822
831void gpio_init(uint gpio);
832
838void gpio_deinit(uint gpio);
839
848void gpio_init_mask(uint gpio_mask);
849// ----------------------------------------------------------------------------
850// Input
851// ----------------------------------------------------------------------------
852
859 static inline bool gpio_get(uint gpio) {
860#if NUM_BANK0_GPIOS <= 32
861 return sio_hw->gpio_in & (1u << gpio);
862#else
863 if (gpio < 32) {
864 return sio_hw->gpio_in & (1u << gpio);
865 } else {
866 return sio_hw->gpio_hi_in & (1u << (gpio - 32));
867 }
868#endif
869}
870
876 static inline uint32_t gpio_get_all(void) {
877#if PICO_USE_GPIO_COPROCESSOR
878 return gpioc_lo_in_get();
879#else
880 return sio_hw->gpio_in;
881#endif
882}
883
889 static inline uint64_t gpio_get_all64(void) {
890#if PICO_USE_GPIO_COPROCESSOR
891 return gpioc_hilo_in_get();
892#elif NUM_BANK0_GPIOS <= 32
893 return sio_hw->gpio_in;
894#else
895 return sio_hw->gpio_in | (((uint64_t)sio_hw->gpio_hi_in) << 32u);
896#endif
897}
898
899// ----------------------------------------------------------------------------
900// Output
901// ----------------------------------------------------------------------------
902
908 static inline void gpio_set_mask(uint32_t mask) {
909#if PICO_USE_GPIO_COPROCESSOR
910 gpioc_lo_out_set(mask);
911#else
912 sio_hw->gpio_set = mask;
913#endif
914}
915
921 static inline void gpio_set_mask64(uint64_t mask) {
922#if PICO_USE_GPIO_COPROCESSOR
923 gpioc_hilo_out_set(mask);
924#elif NUM_BANK0_GPIOS <= 32
925 sio_hw->gpio_set = (uint32_t)mask;
926#else
927 sio_hw->gpio_set = (uint32_t)mask;
928 sio_hw->gpio_hi_set = (uint32_t)(mask >> 32u);
929#endif
930}
931
938 static inline void gpio_set_mask_n(uint n, uint32_t mask) {
939 if (!n) {
940 gpio_set_mask(mask);
941 } else if (n == 1) {
942#if PICO_USE_GPIO_COPROCESSOR
943 gpioc_hi_out_set(mask);
944#elif NUM_BANK0_GPIOS >= 32
945 sio_hw->gpio_hi_set = mask;
946#endif
947 }
948}
949
955 static inline void gpio_clr_mask(uint32_t mask) {
956#if PICO_USE_GPIO_COPROCESSOR
957 gpioc_lo_out_clr(mask);
958#else
959 sio_hw->gpio_clr = mask;
960#endif
961}
962
968 static inline void gpio_clr_mask64(uint64_t mask) {
969#if PICO_USE_GPIO_COPROCESSOR
970 gpioc_hilo_out_clr(mask);
971#elif NUM_BANK0_GPIOS <= 32
972 sio_hw->gpio_clr = (uint32_t)mask;
973#else
974 sio_hw->gpio_clr = (uint32_t)mask;
975 sio_hw->gpio_hi_clr = (uint32_t)(mask >> 32u);
976#endif
977}
978
979
986 static inline void gpio_clr_mask_n(uint n, uint32_t mask) {
987 if (!n) {
988 gpio_clr_mask(mask);
989 } else if (n == 1) {
990#if PICO_USE_GPIO_COPROCESSOR
991 gpioc_hi_out_clr(mask);
992#elif NUM_BANK0_GPIOS >= 32
993 sio_hw->gpio_hi_clr = mask;
994#endif
995 }
996}
997
1003 static inline void gpio_xor_mask(uint32_t mask) {
1004#if PICO_USE_GPIO_COPROCESSOR
1005 gpioc_lo_out_xor(mask);
1006#else
1007 sio_hw->gpio_togl = mask;
1008#endif
1009}
1010
1016 static inline void gpio_xor_mask64(uint64_t mask) {
1017#if PICO_USE_GPIO_COPROCESSOR
1018 gpioc_hilo_out_xor(mask);
1019#elif NUM_BANK0_GPIOS <= 32
1020 sio_hw->gpio_togl = (uint32_t)mask;
1021#else
1022 sio_hw->gpio_togl = (uint32_t)mask;
1023 sio_hw->gpio_hi_togl = (uint32_t)(mask >> 32u);
1024#endif
1025}
1026
1033 static inline void gpio_xor_mask_n(uint n, uint32_t mask) {
1034 if (!n) {
1035 gpio_xor_mask(mask);
1036 } else if (n == 1) {
1037#if PICO_USE_GPIO_COPROCESSOR
1038 gpioc_hi_out_xor(mask);
1039#elif NUM_BANK0_GPIOS >= 32
1040 sio_hw->gpio_hi_togl = mask;
1041#endif
1042 }
1043}
1044
1056 static inline void gpio_put_masked(uint32_t mask, uint32_t value) {
1057#if PICO_USE_GPIO_COPROCESSOR
1058 gpioc_lo_out_xor((gpioc_lo_out_get() ^ value) & mask);
1059#else
1060 sio_hw->gpio_togl = (sio_hw->gpio_out ^ value) & mask;
1061#endif
1062}
1063
1075 static inline void gpio_put_masked64(uint64_t mask, uint64_t value) {
1076#if PICO_USE_GPIO_COPROCESSOR
1077 gpioc_hilo_out_xor((gpioc_hilo_out_get() ^ value) & mask);
1078#elif NUM_BANK0_GPIOS <= 32
1079 sio_hw->gpio_togl = (sio_hw->gpio_out ^ (uint32_t)value) & (uint32_t)mask;
1080#else
1081 sio_hw->gpio_togl = (sio_hw->gpio_out ^ (uint32_t)value) & (uint32_t)mask;
1082 sio_hw->gpio_hi_togl = (sio_hw->gpio_hi_out ^ (uint32_t)(value>>32u)) & (uint32_t)(mask>>32u);
1083#endif
1084}
1085
1098 static inline void gpio_put_masked_n(uint n, uint32_t mask, uint32_t value) {
1099 if (!n) {
1100 gpio_put_masked(mask, value);
1101 } else if (n == 1) {
1102#if PICO_USE_GPIO_COPROCESSOR
1103 gpioc_hi_out_xor((gpioc_hi_out_get() ^ value) & mask);
1104#else
1105 sio_hw->gpio_hi_togl = (sio_hw->gpio_hi_out ^ value) & mask;
1106#endif
1107 }
1108}
1109
1115 static inline void gpio_put_all(uint32_t value) {
1116#if PICO_USE_GPIO_COPROCESSOR
1117 gpioc_lo_out_put(value);
1118#else
1119 sio_hw->gpio_out = value;
1120#endif
1121}
1122
1128 static inline void gpio_put_all64(uint64_t value) {
1129#if PICO_USE_GPIO_COPROCESSOR
1130 gpioc_hilo_out_put(value);
1131#elif NUM_BANK0_GPIOS <= 32
1132 sio_hw->gpio_out = (uint32_t)value;
1133#else
1134 sio_hw->gpio_out = (uint32_t)value;
1135 sio_hw->gpio_hi_out = (uint32_t)(value >> 32u);
1136#endif
1137}
1138
1145 static inline void gpio_put(uint gpio, bool value) {
1146#if PICO_USE_GPIO_COPROCESSOR
1147 gpioc_bit_out_put(gpio, value);
1148#elif NUM_BANK0_GPIOS <= 32
1149 uint32_t mask = 1ul << gpio;
1150 if (value)
1151 gpio_set_mask(mask);
1152 else
1153 gpio_clr_mask(mask);
1154#else
1155 uint32_t mask = 1ul << (gpio & 0x1fu);
1156 if (gpio < 32) {
1157 if (value) {
1158 sio_hw->gpio_set = mask;
1159 } else {
1160 sio_hw->gpio_clr = mask;
1161 }
1162 } else {
1163 if (value) {
1164 sio_hw->gpio_hi_set = mask;
1165 } else {
1166 sio_hw->gpio_hi_clr = mask;
1167 }
1168 }
1169#endif
1170}
1171
1188 static inline bool gpio_get_out_level(uint gpio) {
1189#if NUM_BANK0_GPIOS <= 32
1190 return sio_hw->gpio_out & (1u << gpio);
1191#else
1192 uint32_t bits = gpio < 32 ? sio_hw->gpio_out : sio_hw->gpio_hi_out;
1193 return bits & (1u << (gpio & 0x1fu));
1194#endif
1195}
1196
1197// ----------------------------------------------------------------------------
1198// Direction
1199// ----------------------------------------------------------------------------
1200
1208 static inline void gpio_set_dir_out_masked(uint32_t mask) {
1209#if PICO_USE_GPIO_COPROCESSOR
1210 gpioc_lo_oe_set(mask);
1211#else
1212 sio_hw->gpio_oe_set = mask;
1213#endif
1214}
1215
1223 static inline void gpio_set_dir_out_masked64(uint64_t mask) {
1224#if PICO_USE_GPIO_COPROCESSOR
1225 gpioc_hilo_oe_set(mask);
1226#elif NUM_BANK0_GPIOS <= 32
1227 sio_hw->gpio_oe_set = mask;
1228#else
1229 sio_hw->gpio_oe_set = (uint32_t)mask;
1230 sio_hw->gpio_hi_oe_set = (uint32_t)(mask >> 32u);
1231#endif
1232}
1233
1239 static inline void gpio_set_dir_in_masked(uint32_t mask) {
1240#if PICO_USE_GPIO_COPROCESSOR
1241 gpioc_lo_oe_clr(mask);
1242#else
1243 sio_hw->gpio_oe_clr = mask;
1244#endif
1245}
1246
1252 static inline void gpio_set_dir_in_masked64(uint64_t mask) {
1253#if PICO_USE_GPIO_COPROCESSOR
1254 gpioc_hilo_oe_clr(mask);
1255#elif NUM_BANK0_GPIOS <= 32
1256 sio_hw->gpio_oe_clr = mask;
1257#else
1258 sio_hw->gpio_oe_clr = (uint32_t)mask;
1259 sio_hw->gpio_hi_oe_clr = (uint32_t)(mask >> 32u);
1260#endif
1261}
1262
1274 static inline void gpio_set_dir_masked(uint32_t mask, uint32_t value) {
1275#if PICO_USE_GPIO_COPROCESSOR
1276 gpioc_lo_oe_xor((gpioc_lo_oe_get() ^ value) & mask);
1277#else
1278 sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ value) & mask;
1279#endif
1280}
1281
1293 static inline void gpio_set_dir_masked64(uint64_t mask, uint64_t value) {
1294#if PICO_USE_GPIO_COPROCESSOR
1295 gpioc_hilo_oe_xor((gpioc_hilo_oe_get() ^ value) & mask);
1296#elif NUM_BANK0_GPIOS <= 32
1297 sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ (uint32_t)value) & (uint32_t)mask;
1298#else
1299 sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ (uint32_t)value) & (uint32_t)mask;
1300 sio_hw->gpio_hi_oe_togl = (sio_hw->gpio_hi_oe ^ (uint32_t)(value >> 32u)) & (uint32_t)(mask >> 32u);
1301#endif
1302}
1303
1304
1310 static inline void gpio_set_dir_all_bits(uint32_t values) {
1311#if PICO_USE_GPIO_COPROCESSOR
1312 gpioc_lo_oe_put(values);
1313#else
1314 sio_hw->gpio_oe = values;
1315#endif
1316}
1317
1323 static inline void gpio_set_dir_all_bits64(uint64_t values) {
1324#if PICO_USE_GPIO_COPROCESSOR
1325 gpioc_hilo_oe_put(values);
1326#elif NUM_BANK0_GPIOS <= 32
1327 sio_hw->gpio_oe = (uint32_t)values;
1328#else
1329 sio_hw->gpio_oe = (uint32_t)values;
1330 sio_hw->gpio_hi_oe = (uint32_t)(values >> 32u);
1331#endif
1332}
1333
1340 static inline void gpio_set_dir(uint gpio, bool out) {
1341#if PICO_USE_GPIO_COPROCESSOR
1342 gpioc_bit_oe_put(gpio, out);
1343#elif PICO_RP2040 || NUM_BANK0_GPIOS <= 32
1344 uint32_t mask = 1ul << gpio;
1345 if (out)
1346 gpio_set_dir_out_masked(mask);
1347 else
1348 gpio_set_dir_in_masked(mask);
1349#else
1350 uint32_t mask = 1u << (gpio & 0x1fu);
1351 if (gpio < 32) {
1352 if (out) {
1353 sio_hw->gpio_oe_set = mask;
1354 } else {
1355 sio_hw->gpio_oe_clr = mask;
1356 }
1357 } else {
1358 if (out) {
1359 sio_hw->gpio_hi_oe_set = mask;
1360 } else {
1361 sio_hw->gpio_hi_oe_clr = mask;
1362 }
1363 }
1364#endif
1365}
1366
1373 static inline bool gpio_is_dir_out(uint gpio) {
1374#if NUM_BANK0_GPIOS <= 32
1375 return sio_hw->gpio_oe & (1u << (gpio));
1376#else
1377 uint32_t bits = gpio < 32 ? sio_hw->gpio_oe : sio_hw->gpio_hi_oe;
1378 return bits & (1u << (gpio & 0x1fu));
1379#endif
1380}
1381
1388 static inline uint gpio_get_dir(uint gpio) {
1389 return gpio_is_dir_out(gpio); // note GPIO_OUT is 1/true and GPIO_IN is 0/false anyway
1390}
1391
1392#if PICO_SECURE
1393static inline void gpio_assign_to_ns(uint gpio, bool ns) {
1394 check_gpio_param(gpio);
1395 if (ns) hw_set_bits(&accessctrl_hw->gpio_nsmask[gpio/32], 1u << (gpio & 0x1fu));
1396 else hw_clear_bits(&accessctrl_hw->gpio_nsmask[gpio/32], 1u << (gpio & 0x1fu));
1397}
1398#endif
1399extern void gpio_debug_pins_init(void);
1400
1401#ifdef __cplusplus
1402}
1403#endif
1404
1405
1406// PICO_CONFIG: PICO_DEBUG_PIN_BASE, First pin to use for debug output (if enabled), min=0, max=28, default=19, group=hardware_gpio
1407#ifndef PICO_DEBUG_PIN_BASE
1408#define PICO_DEBUG_PIN_BASE 19u
1409#endif
1410
1411// PICO_CONFIG: PICO_DEBUG_PIN_COUNT, Number of pins to use for debug output (if enabled), min=1, max=28, default=3, group=hardware_gpio
1412#ifndef PICO_DEBUG_PIN_COUNT
1413#define PICO_DEBUG_PIN_COUNT 3u
1414#endif
1415
1416#ifndef __cplusplus
1417// note these two macros may only be used once per and only apply per compilation unit (hence the CU_)
1418#define CU_REGISTER_DEBUG_PINS(...) enum __unused DEBUG_PIN_TYPE { _none = 0, __VA_ARGS__ }; static enum DEBUG_PIN_TYPE __selected_debug_pins;
1419#define CU_SELECT_DEBUG_PINS(x) static enum DEBUG_PIN_TYPE __selected_debug_pins = (x);
1420#define DEBUG_PINS_ENABLED(p) (__selected_debug_pins == (p))
1421#else
1422#define CU_REGISTER_DEBUG_PINS(p...) \
1423 enum DEBUG_PIN_TYPE { _none = 0, p }; \
1424 template <enum DEBUG_PIN_TYPE> class __debug_pin_settings { \
1425 public: \
1426 static inline bool enabled() { return false; } \
1427 };
1428#define CU_SELECT_DEBUG_PINS(x) template<> inline bool __debug_pin_settings<x>::enabled() { return true; };
1429#define DEBUG_PINS_ENABLED(p) (__debug_pin_settings<p>::enabled())
1430#endif
1431#define DEBUG_PINS_SET(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_set_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
1432#define DEBUG_PINS_CLR(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_clr_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
1433#define DEBUG_PINS_XOR(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_xor_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
1434
1435#endif // _GPIO_H_
gpio_dir
gpio_dir
Definition: gpio.h:170
GPIO_OUT
@ GPIO_OUT
set GPIO to output
Definition: gpio.h:171
GPIO_IN
@ GPIO_IN
set GPIO to input
Definition: gpio.h:172
gpio_override
gpio_override
Definition: gpio.h:207
GPIO_OVERRIDE_INVERT
@ GPIO_OVERRIDE_INVERT
invert peripheral signal selected via gpio_set_function
Definition: gpio.h:209
GPIO_OVERRIDE_HIGH
@ GPIO_OVERRIDE_HIGH
drive high/enable output
Definition: gpio.h:211
GPIO_OVERRIDE_LOW
@ GPIO_OVERRIDE_LOW
drive low/disable output
Definition: gpio.h:210
GPIO_OVERRIDE_NORMAL
@ GPIO_OVERRIDE_NORMAL
peripheral signal selected via gpio_set_function
Definition: gpio.h:208
hw_set_bits
static __force_inline void hw_set_bits(io_rw_32 *addr, uint32_t mask)
Atomically set the specified bits to 1 in a HW register.
Definition: address_mapped.h:135
hw_clear_bits
static __force_inline void hw_clear_bits(io_rw_32 *addr, uint32_t mask)
Atomically clear the specified bits to 0 in a HW register.
Definition: address_mapped.h:145
gpio_add_raw_irq_handler_with_order_priority
static void gpio_add_raw_irq_handler_with_order_priority(uint gpio, irq_handler_t handler, uint8_t order_priority)
Adds a raw GPIO IRQ handler for a specific GPIO on the current core.
Definition: gpio.h:669
gpio_set_irq_enabled
void gpio_set_irq_enabled(uint gpio, uint32_t event_mask, bool enabled)
Enable or disable specific interrupt events for specified GPIO.
Definition: gpio.c:186
gpio_acknowledge_irq
void gpio_acknowledge_irq(uint gpio, uint32_t event_mask)
Acknowledge a GPIO interrupt for the specified events on the calling core.
Definition: gpio.c:259
gpio_get_out_level
static bool gpio_get_out_level(uint gpio)
Determine whether a GPIO is currently driven high or low.
Definition: gpio.h:1188
gpio_put_all64
static void gpio_put_all64(uint64_t value)
Drive all pins simultaneously.
Definition: gpio.h:1128
gpio_set_dormant_irq_enabled
void gpio_set_dormant_irq_enabled(uint gpio, uint32_t event_mask, bool enabled)
Enable dormant wake up interrupt for specified GPIO and events.
Definition: gpio.c:253
gpio_set_drive_strength
void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive)
Set drive strength for a specified GPIO.
Definition: gpio.c:138
gpio_function_t
enum gpio_function_rp2040 gpio_function_t
GPIO pin function selectors on RP2040 (used as typedef gpio_function_t)
gpio_get_drive_strength
enum gpio_drive_strength gpio_get_drive_strength(uint gpio)
Determine current drive strength for a specified GPIO.
Definition: gpio.c:146
gpio_drive_strength
gpio_drive_strength
Drive strength levels for GPIO outputs.
Definition: gpio.h:232
gpio_set_input_hysteresis_enabled
void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled)
Enable/disable GPIO input hysteresis (Schmitt trigger)
Definition: gpio.c:106
gpio_set_function
void gpio_set_function(uint gpio, gpio_function_t fn)
Select GPIO function.
Definition: gpio.c:38
gpio_get_function
gpio_function_t gpio_get_function(uint gpio)
Determine current GPIO function.
Definition: gpio.c:56
gpio_add_raw_irq_handler_masked64
void gpio_add_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler)
Adds a raw GPIO IRQ handler for the specified GPIOs on the current core.
Definition: gpio.c:237
gpio_set_oeover
void gpio_set_oeover(uint gpio, uint value)
Select GPIO output enable override.
Definition: gpio.c:98
gpio_remove_raw_irq_handler_masked
void gpio_remove_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler)
Removes a raw GPIO IRQ handler for the specified GPIOs on the current core.
Definition: gpio.c:241
gpio_get_dir
static uint gpio_get_dir(uint gpio)
Get a specific GPIO direction.
Definition: gpio.h:1388
gpio_set_dir_masked64
static void gpio_set_dir_masked64(uint64_t mask, uint64_t value)
Set multiple GPIO directions.
Definition: gpio.h:1293
gpio_add_raw_irq_handler
static void gpio_add_raw_irq_handler(uint gpio, irq_handler_t handler)
Adds a raw GPIO IRQ handler for a specific GPIO on the current core.
Definition: gpio.h:768
gpio_init_mask
void gpio_init_mask(uint gpio_mask)
Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO)
Definition: gpio.c:291
gpio_pull_up
static void gpio_pull_up(uint gpio)
Set specified GPIO to be pulled up.
Definition: gpio.h:299
gpio_set_function_masked
void gpio_set_function_masked(uint32_t gpio_mask, gpio_function_t fn)
Select the function for multiple GPIOs.
Definition: gpio.c:300
gpio_set_irq_callback
void gpio_set_irq_callback(gpio_irq_callback_t callback)
Set the generic callback used for GPIO IRQ events for the current core.
Definition: gpio.c:208
gpio_get_slew_rate
enum gpio_slew_rate gpio_get_slew_rate(uint gpio)
Determine current slew rate for a specified GPIO.
Definition: gpio.c:128
gpio_remove_raw_irq_handler
static void gpio_remove_raw_irq_handler(uint gpio, irq_handler_t handler)
Removes a raw GPIO IRQ handler for the specified GPIO on the current core.
Definition: gpio.h:814
gpio_deinit
void gpio_deinit(uint gpio)
Resets a GPIO back to the NULL function, i.e. disables it.
Definition: gpio.c:287
gpio_set_dir_all_bits
static void gpio_set_dir_all_bits(uint32_t values)
Set direction of all pins simultaneously.
Definition: gpio.h:1310
gpio_is_pulled_down
static bool gpio_is_pulled_down(uint gpio)
Determine if the specified GPIO is pulled down.
Definition: gpio.h:328
gpio_set_inover
void gpio_set_inover(uint gpio, uint value)
Select GPIO input override.
Definition: gpio.c:82
gpio_set_irq_enabled_with_callback
void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t event_mask, bool enabled, gpio_irq_callback_t callback)
Convenience function which performs multiple GPIO IRQ related initializations.
Definition: gpio.c:201
gpio_irq_level
gpio_irq_level
GPIO Interrupt level definitions (GPIO events)
Definition: gpio.h:190
gpio_xor_mask
static void gpio_xor_mask(uint32_t mask)
Toggle every GPIO appearing in mask.
Definition: gpio.h:1003
gpio_set_dir
static void gpio_set_dir(uint gpio, bool out)
Set a single GPIO direction.
Definition: gpio.h:1340
gpio_clr_mask
static void gpio_clr_mask(uint32_t mask)
Drive low every GPIO appearing in mask.
Definition: gpio.h:955
gpio_put_masked_n
static void gpio_put_masked_n(uint n, uint32_t mask, uint32_t value)
Drive GPIOs high/low depending on parameters.
Definition: gpio.h:1098
gpio_set_dir_out_masked64
static void gpio_set_dir_out_masked64(uint64_t mask)
Set a number of GPIOs to output.
Definition: gpio.h:1223
gpio_put
static void gpio_put(uint gpio, bool value)
Drive a single GPIO high/low.
Definition: gpio.h:1145
gpio_xor_mask_n
static void gpio_xor_mask_n(uint n, uint32_t mask)
Toggle every GPIO appearing in mask.
Definition: gpio.h:1033
gpio_slew_rate
gpio_slew_rate
Slew rate limiting levels for GPIO outputs.
Definition: gpio.h:221
gpio_set_input_enabled
void gpio_set_input_enabled(uint gpio, bool enabled)
Enable GPIO input.
Definition: gpio.c:273
gpio_add_raw_irq_handler_with_order_priority_masked64
void gpio_add_raw_irq_handler_with_order_priority_masked64(uint64_t gpio_mask, irq_handler_t handler, uint8_t order_priority)
Adds a raw GPIO IRQ handler for the specified GPIOs on the current core.
Definition: gpio.c:227
gpio_set_dir_in_masked
static void gpio_set_dir_in_masked(uint32_t mask)
Set a number of GPIOs to input.
Definition: gpio.h:1239
gpio_put_all
static void gpio_put_all(uint32_t value)
Drive all pins simultaneously.
Definition: gpio.h:1115
gpio_set_dir_out_masked
static void gpio_set_dir_out_masked(uint32_t mask)
Set a number of GPIOs to output.
Definition: gpio.h:1208
gpio_set_outover
void gpio_set_outover(uint gpio, uint value)
Set GPIO output override.
Definition: gpio.c:90
gpio_set_function_masked64
void gpio_set_function_masked64(uint64_t gpio_mask, gpio_function_t fn)
Select the function for multiple GPIOs.
Definition: gpio.c:309
gpio_init
void gpio_init(uint gpio)
Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO)
Definition: gpio.c:281
gpio_irq_callback_t
void(* gpio_irq_callback_t)(uint gpio, uint32_t event_mask)
Definition: gpio.h:205
gpio_remove_raw_irq_handler_masked64
void gpio_remove_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler)
Removes a raw GPIO IRQ handler for the specified GPIOs on the current core.
Definition: gpio.c:247
gpio_set_mask_n
static void gpio_set_mask_n(uint n, uint32_t mask)
Drive high every GPIO appearing in mask.
Definition: gpio.h:938
gpio_clr_mask_n
static void gpio_clr_mask_n(uint n, uint32_t mask)
Drive low every GPIO appearing in mask.
Definition: gpio.h:986
gpio_set_irqover
void gpio_set_irqover(uint gpio, uint value)
Set GPIO IRQ override.
Definition: gpio.c:73
gpio_set_mask64
static void gpio_set_mask64(uint64_t mask)
Drive high every GPIO appearing in mask.
Definition: gpio.h:921
gpio_is_dir_out
static bool gpio_is_dir_out(uint gpio)
Check if a specific GPIO direction is OUT.
Definition: gpio.h:1373
gpio_get_all64
static uint64_t gpio_get_all64(void)
Get raw value of all GPIOs.
Definition: gpio.h:889
gpio_put_masked64
static void gpio_put_masked64(uint64_t mask, uint64_t value)
Drive GPIOs high/low depending on parameters.
Definition: gpio.h:1075
gpio_set_dir_masked
static void gpio_set_dir_masked(uint32_t mask, uint32_t value)
Set multiple GPIO directions.
Definition: gpio.h:1274
gpio_clr_mask64
static void gpio_clr_mask64(uint64_t mask)
Drive low every GPIO appearing in mask.
Definition: gpio.h:968
gpio_set_dir_all_bits64
static void gpio_set_dir_all_bits64(uint64_t values)
Set direction of all pins simultaneously.
Definition: gpio.h:1323
gpio_set_pulls
void gpio_set_pulls(uint gpio, bool up, bool down)
Select up and down pulls on specific GPIO.
Definition: gpio.c:63
gpio_xor_mask64
static void gpio_xor_mask64(uint64_t mask)
Toggle every GPIO appearing in mask.
Definition: gpio.h:1016
gpio_is_input_hysteresis_enabled
bool gpio_is_input_hysteresis_enabled(uint gpio)
Determine whether input hysteresis is enabled on a specified GPIO.
Definition: gpio.c:115
gpio_set_dir_in_masked64
static void gpio_set_dir_in_masked64(uint64_t mask)
Set a number of GPIOs to input.
Definition: gpio.h:1252
gpio_is_pulled_up
static bool gpio_is_pulled_up(uint gpio)
Determine if the specified GPIO is pulled up.
Definition: gpio.h:309
gpio_put_masked
static void gpio_put_masked(uint32_t mask, uint32_t value)
Drive GPIOs high/low depending on parameters.
Definition: gpio.h:1056
gpio_disable_pulls
static void gpio_disable_pulls(uint gpio)
Disable pulls on specified GPIO.
Definition: gpio.h:337
gpio_get_all
static uint32_t gpio_get_all(void)
Get raw value of all GPIOs.
Definition: gpio.h:876
gpio_pull_down
static void gpio_pull_down(uint gpio)
Set specified GPIO to be pulled down.
Definition: gpio.h:318
gpio_set_slew_rate
void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew)
Set slew rate for a specified GPIO.
Definition: gpio.c:120
gpio_get_irq_event_mask
static uint32_t gpio_get_irq_event_mask(uint gpio)
Return the current interrupt status (pending events) for the given GPIO.
Definition: gpio.h:546
gpio_get
static bool gpio_get(uint gpio)
Get state of a single specified GPIO.
Definition: gpio.h:859
gpio_set_mask
static void gpio_set_mask(uint32_t mask)
Drive high every GPIO appearing in mask.
Definition: gpio.h:908
gpio_add_raw_irq_handler_with_order_priority_masked
void gpio_add_raw_irq_handler_with_order_priority_masked(uint32_t gpio_mask, irq_handler_t handler, uint8_t order_priority)
Adds a raw GPIO IRQ handler for the specified GPIOs on the current core.
Definition: gpio.c:221
gpio_add_raw_irq_handler_masked
void gpio_add_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler)
Adds a raw GPIO IRQ handler for the specified GPIOs on the current core.
Definition: gpio.c:233
GPIO_DRIVE_STRENGTH_2MA
@ GPIO_DRIVE_STRENGTH_2MA
2 mA nominal drive strength
Definition: gpio.h:233
GPIO_DRIVE_STRENGTH_8MA
@ GPIO_DRIVE_STRENGTH_8MA
8 mA nominal drive strength
Definition: gpio.h:235
GPIO_DRIVE_STRENGTH_12MA
@ GPIO_DRIVE_STRENGTH_12MA
12 mA nominal drive strength
Definition: gpio.h:236
GPIO_DRIVE_STRENGTH_4MA
@ GPIO_DRIVE_STRENGTH_4MA
4 mA nominal drive strength
Definition: gpio.h:234
GPIO_IRQ_EDGE_RISE
@ GPIO_IRQ_EDGE_RISE
IRQ when the GPIO has transitioned from a logical 1 to a logical 0.
Definition: gpio.h:194
GPIO_IRQ_EDGE_FALL
@ GPIO_IRQ_EDGE_FALL
IRQ when the GPIO has transitioned from a logical 0 to a logical 1.
Definition: gpio.h:193
GPIO_IRQ_LEVEL_LOW
@ GPIO_IRQ_LEVEL_LOW
IRQ when the GPIO pin is a logical 1.
Definition: gpio.h:191
GPIO_IRQ_LEVEL_HIGH
@ GPIO_IRQ_LEVEL_HIGH
IRQ when the GPIO pin is a logical 0.
Definition: gpio.h:192
GPIO_SLEW_RATE_FAST
@ GPIO_SLEW_RATE_FAST
Slew rate limiting disabled.
Definition: gpio.h:223
GPIO_SLEW_RATE_SLOW
@ GPIO_SLEW_RATE_SLOW
Slew rate limiting enabled.
Definition: gpio.h:222
irq_handler_t
void(* irq_handler_t)(void)
Interrupt handler function type.
Definition: irq.h:195
get_core_num
static __force_inline uint get_core_num(void)
Get the current core number.
Definition: platform.h:141
irq.h
pico.h
io_bank0_irq_ctrl_hw_t
Definition: io_bank0.h:67