v2.0.0
spi.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_SPI_H
9#define _HARDWARE_STRUCTS_SPI_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/spi.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/spi.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
26 typedef struct {
27 _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0
28 // Control register 0, SSPCR0 on page 3-4
29 // 0x0000ff00 [15:8] SCR (0x00) Serial clock rate
30 // 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only
31 // 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only
32 // 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format
33 // 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation
34 io_rw_32 cr0;
35
36 _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1
37 // Control register 1, SSPCR1 on page 3-5
38 // 0x00000008 [3] SOD (0) Slave-mode output disable
39 // 0x00000004 [2] MS (0) Master or slave mode select
40 // 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled
41 // 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled
42 io_rw_32 cr1;
43
44 _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR
45 // Data register, SSPDR on page 3-6
46 // 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO
47 io_rw_32 dr;
48
49 _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR
50 // Status register, SSPSR on page 3-7
51 // 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle
52 // 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full
53 // 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty
54 // 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full
55 // 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty
56 io_ro_32 sr;
57
58 _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR
59 // Clock prescale register, SSPCPSR on page 3-8
60 // 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor
61 io_rw_32 cpsr;
62
63 _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC
64 // Interrupt mask set or clear register, SSPIMSC on page 3-9
65 // 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty...
66 // 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or...
67 // 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty...
68 // 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written...
69 io_rw_32 imsc;
70
71 _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS
72 // Raw interrupt status register, SSPRIS on page 3-10
73 // 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the...
74 // 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the...
75 // 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the...
76 // 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the...
77 io_ro_32 ris;
78
79 _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS
80 // Masked interrupt status register, SSPMIS on page 3-11
81 // 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after...
82 // 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after...
83 // 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after...
84 // 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,...
85 io_ro_32 mis;
86
87 _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR
88 // Interrupt clear register, SSPICR on page 3-11
89 // 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt
90 // 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt
91 io_rw_32 icr;
92
93 _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR
94 // DMA control register, SSPDMACR on page 3-12
95 // 0x00000002 [1] TXDMAE (0) Transmit DMA Enable
96 // 0x00000001 [0] RXDMAE (0) Receive DMA Enable
97 io_rw_32 dmacr;
98} spi_hw_t;
99
100#define spi0_hw ((spi_hw_t *)SPI0_BASE)
101#define spi1_hw ((spi_hw_t *)SPI1_BASE)
102static_assert(sizeof (spi_hw_t) == 0x0028, "");
103
104#endif // _HARDWARE_STRUCTS_SPI_H
105
address_mapped.h
spi_hw_t
Definition: spi.h:26