v2.0.0
dma.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_DMA_H
9#define _HARDWARE_STRUCTS_DMA_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/dma.h"
17#include "hardware/structs/dma_debug.h"
18
19// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_dma
20//
21// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
22// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
23//
24// Bit-field descriptions are of the form:
25// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
26
27typedef struct {
28 _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR
29 // DMA Channel 0 Read Address pointer
30 // 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes
31 io_rw_32 read_addr;
32
33 _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR
34 // DMA Channel 0 Write Address pointer
35 // 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes
36 io_rw_32 write_addr;
37
38 _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT
39 // DMA Channel 0 Transfer Count
40 // 0xf0000000 [31:28] MODE (0x0) When MODE is 0x0, the transfer count decrements with...
41 // 0x0fffffff [27:0] COUNT (0x0000000) 28-bit transfer count (256 million transfers maximum)
42 io_rw_32 transfer_count;
43
44 _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG
45 // DMA Channel 0 Control and Status
46 // 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags
47 // 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error
48 // 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error
49 // 0x04000000 [26] BUSY (0) This flag goes high when the channel starts a new...
50 // 0x02000000 [25] SNIFF_EN (0) If 1, this channel's data transfers are visible to the...
51 // 0x01000000 [24] BSWAP (0) Apply byte-swap transformation to DMA data
52 // 0x00800000 [23] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the...
53 // 0x007e0000 [22:17] TREQ_SEL (0x00) Select a Transfer Request signal
54 // 0x0001e000 [16:13] CHAIN_TO (0x0) When this channel completes, it will trigger the channel...
55 // 0x00001000 [12] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses
56 // 0x00000f00 [11:8] RING_SIZE (0x0) Size of address wrap region
57 // 0x00000080 [7] INCR_WRITE_REV (0) If 1, and INCR_WRITE is 1, the write address is...
58 // 0x00000040 [6] INCR_WRITE (0) If 1, the write address increments with each transfer
59 // 0x00000020 [5] INCR_READ_REV (0) If 1, and INCR_READ is 1, the read address is...
60 // 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer
61 // 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word)
62 // 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in...
63 // 0x00000001 [0] EN (0) DMA Channel Enable
64 io_rw_32 ctrl_trig;
65
66 _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL
67 // Alias for channel 0 CTRL register
68 // 0xffffffff [31:0] CH0_AL1_CTRL (-)
69 io_rw_32 al1_ctrl;
70
71 _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR
72 // Alias for channel 0 READ_ADDR register
73 // 0xffffffff [31:0] CH0_AL1_READ_ADDR (-)
74 io_rw_32 al1_read_addr;
75
76 _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR
77 // Alias for channel 0 WRITE_ADDR register
78 // 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-)
79 io_rw_32 al1_write_addr;
80
81 _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG
82 // Alias for channel 0 TRANS_COUNT register +
83 // 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-)
84 io_rw_32 al1_transfer_count_trig;
85
86 _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL
87 // Alias for channel 0 CTRL register
88 // 0xffffffff [31:0] CH0_AL2_CTRL (-)
89 io_rw_32 al2_ctrl;
90
91 _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT
92 // Alias for channel 0 TRANS_COUNT register
93 // 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-)
94 io_rw_32 al2_transfer_count;
95
96 _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR
97 // Alias for channel 0 READ_ADDR register
98 // 0xffffffff [31:0] CH0_AL2_READ_ADDR (-)
99 io_rw_32 al2_read_addr;
100
101 _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG
102 // Alias for channel 0 WRITE_ADDR register +
103 // 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-)
104 io_rw_32 al2_write_addr_trig;
105
106 _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL
107 // Alias for channel 0 CTRL register
108 // 0xffffffff [31:0] CH0_AL3_CTRL (-)
109 io_rw_32 al3_ctrl;
110
111 _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR
112 // Alias for channel 0 WRITE_ADDR register
113 // 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-)
114 io_rw_32 al3_write_addr;
115
116 _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT
117 // Alias for channel 0 TRANS_COUNT register
118 // 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-)
119 io_rw_32 al3_transfer_count;
120
121 _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG
122 // Alias for channel 0 READ_ADDR register +
123 // 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-)
124 io_rw_32 al3_read_addr_trig;
125} dma_channel_hw_t;
126
127 typedef struct {
128 _REG_(DMA_MPU_BAR0_OFFSET) // DMA_MPU_BAR0
129 // Base address register for MPU region 0
130 // 0xffffffe0 [31:5] ADDR (0x0000000) This MPU region matches addresses where addr[31:5] (the...
131 io_rw_32 bar;
132
133 _REG_(DMA_MPU_LAR0_OFFSET) // DMA_MPU_LAR0
134 // Limit address register for MPU region 0
135 // 0xffffffe0 [31:5] ADDR (0x0000000) Limit address bits 31:5
136 // 0x00000004 [2] S (0) Determines the Secure/Non-secure (=1/0) status of...
137 // 0x00000002 [1] P (0) Determines the Privileged/Unprivileged (=1/0) status of...
138 // 0x00000001 [0] EN (0) Region enable
139 io_rw_32 lar;
140} dma_mpu_region_hw_t;
141
142typedef struct {
143 _REG_(DMA_INTR_OFFSET) // DMA_INTR
144 // Interrupt Status (raw)
145 // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0
146 io_rw_32 intr;
147
148 _REG_(DMA_INTE0_OFFSET) // DMA_INTE0
149 // Interrupt Enables for IRQ 0
150 // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0
151 io_rw_32 inte;
152
153 _REG_(DMA_INTF0_OFFSET) // DMA_INTF0
154 // Force Interrupts
155 // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTS0
156 io_rw_32 intf;
157
158 _REG_(DMA_INTS0_OFFSET) // DMA_INTS0
159 // Interrupt Status for IRQ 0
160 // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are...
161 io_rw_32 ints;
162} dma_irq_ctrl_hw_t;
163
164typedef struct {
165 dma_channel_hw_t ch[16];
166
167 union {
168 struct {
169 _REG_(DMA_INTR_OFFSET) // DMA_INTR
170 // Interrupt Status (raw)
171 // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0
172 io_rw_32 intr;
173
174 _REG_(DMA_INTE0_OFFSET) // DMA_INTE0
175 // Interrupt Enables for IRQ 0
176 // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0
177 io_rw_32 inte0;
178
179 _REG_(DMA_INTF0_OFFSET) // DMA_INTF0
180 // Force Interrupts
181 // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0
182 io_rw_32 intf0;
183
184 _REG_(DMA_INTS0_OFFSET) // DMA_INTS0
185 // Interrupt Status for IRQ 0
186 // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are...
187 io_rw_32 ints0;
188
189 uint32_t __pad0;
190
191 _REG_(DMA_INTE1_OFFSET) // DMA_INTE1
192 // Interrupt Enables for IRQ 1
193 // 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1
194 io_rw_32 inte1;
195
196 _REG_(DMA_INTF1_OFFSET) // DMA_INTF1
197 // Force Interrupts for IRQ 1
198 // 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1
199 io_rw_32 intf1;
200
201 _REG_(DMA_INTS1_OFFSET) // DMA_INTS1
202 // Interrupt Status (masked) for IRQ 1
203 // 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are...
204 io_rw_32 ints1;
205
206 uint32_t __pad1;
207
208 _REG_(DMA_INTE2_OFFSET) // DMA_INTE2
209 // Interrupt Enables for IRQ 2
210 // 0x0000ffff [15:0] INTE2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2
211 io_rw_32 inte2;
212
213 _REG_(DMA_INTF2_OFFSET) // DMA_INTF2
214 // Force Interrupts for IRQ 2
215 // 0x0000ffff [15:0] INTF2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2
216 io_rw_32 intf2;
217
218 _REG_(DMA_INTS2_OFFSET) // DMA_INTS2
219 // Interrupt Status (masked) for IRQ 2
220 // 0x0000ffff [15:0] INTS2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2
221 io_rw_32 ints2;
222
223 uint32_t __pad2;
224
225 _REG_(DMA_INTE3_OFFSET) // DMA_INTE3
226 // Interrupt Enables for IRQ 3
227 // 0x0000ffff [15:0] INTE3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3
228 io_rw_32 inte3;
229
230 _REG_(DMA_INTF3_OFFSET) // DMA_INTF3
231 // Force Interrupts for IRQ 3
232 // 0x0000ffff [15:0] INTF3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3
233 io_rw_32 intf3;
234
235 _REG_(DMA_INTS3_OFFSET) // DMA_INTS3
236 // Interrupt Status (masked) for IRQ 3
237 // 0x0000ffff [15:0] INTS3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3
238 io_rw_32 ints3;
239 };
240 dma_irq_ctrl_hw_t irq_ctrl[4];
241 };
242
243 // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
244 _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
245 // Pacing timer (generate periodic TREQs)
246 // 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend
247 // 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor
248 io_rw_32 timer[4];
249
250 _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
251 // Trigger one or more channels simultaneously
252 // 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel
253 io_wo_32 multi_channel_trigger;
254
255 _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL
256 // Sniffer Control
257 // 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)...
258 // 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read
259 // 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,...
260 // 0x000001e0 [8:5] CALC (0x0)
261 // 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe
262 // 0x00000001 [0] EN (0) Enable sniffer
263 io_rw_32 sniff_ctrl;
264
265 _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA
266 // Data accumulator for sniff hardware
267 // 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA...
268 io_rw_32 sniff_data;
269
270 uint32_t _pad0;
271
272 _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS
273 // Debug RAF, WAF, TDF levels
274 // 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level
275 // 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level
276 // 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level
277 io_ro_32 fifo_levels;
278
279 _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT
280 // Abort an in-progress transfer sequence on one or more channels
281 // 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel
282 io_wo_32 abort;
283
284 _REG_(DMA_N_CHANNELS_OFFSET) // DMA_N_CHANNELS
285 // The number of channels this DMA instance is equipped with
286 // 0x0000001f [4:0] N_CHANNELS (-)
287 io_ro_32 n_channels;
288
289 uint32_t _pad1[5];
290
291 // (Description copied from array index 0 register DMA_SECCFG_CH0 applies similarly to other array indexes)
292 _REG_(DMA_SECCFG_CH0_OFFSET) // DMA_SECCFG_CH0
293 // Security level configuration for channel 0.
294 // 0x00000004 [2] LOCK (0) LOCK is 0 at reset, and is set to 1 automatically upon a...
295 // 0x00000002 [1] S (1) Secure channel
296 // 0x00000001 [0] P (1) Privileged channel
297 io_rw_32 seccfg_ch[16];
298
299 // (Description copied from array index 0 register DMA_SECCFG_IRQ0 applies similarly to other array indexes)
300 _REG_(DMA_SECCFG_IRQ0_OFFSET) // DMA_SECCFG_IRQ0
301 // Security configuration for IRQ 0
302 // 0x00000002 [1] S (1) Secure IRQ
303 // 0x00000001 [0] P (1) Privileged IRQ
304 io_rw_32 seccfg_irq[4];
305
306 _REG_(DMA_SECCFG_MISC_OFFSET) // DMA_SECCFG_MISC
307 // Miscellaneous security configuration
308 // 0x00000200 [9] TIMER3_S (1) If 1, the TIMER3 register is only accessible from a...
309 // 0x00000100 [8] TIMER3_P (1) If 1, the TIMER3 register is only accessible from a...
310 // 0x00000080 [7] TIMER2_S (1) If 1, the TIMER2 register is only accessible from a...
311 // 0x00000040 [6] TIMER2_P (1) If 1, the TIMER2 register is only accessible from a...
312 // 0x00000020 [5] TIMER1_S (1) If 1, the TIMER1 register is only accessible from a...
313 // 0x00000010 [4] TIMER1_P (1) If 1, the TIMER1 register is only accessible from a...
314 // 0x00000008 [3] TIMER0_S (1) If 1, the TIMER0 register is only accessible from a...
315 // 0x00000004 [2] TIMER0_P (1) If 1, the TIMER0 register is only accessible from a...
316 // 0x00000002 [1] SNIFF_S (1) If 1, the sniffer can see data transfers from Secure...
317 // 0x00000001 [0] SNIFF_P (1) If 1, the sniffer can see data transfers from Privileged...
318 io_rw_32 seccfg_misc;
319
320 uint32_t _pad2[11];
321
322 _REG_(DMA_MPU_CTRL_OFFSET) // DMA_MPU_CTRL
323 // Control register for DMA MPU
324 // 0x00000008 [3] NS_HIDE_ADDR (0) By default, when a region's S bit is clear,...
325 // 0x00000004 [2] S (0) Determine whether an address not covered by an active...
326 // 0x00000002 [1] P (0) Determine whether an address not covered by an active...
327 io_rw_32 mpu_ctrl;
328
329 dma_mpu_region_hw_t mpu_region[8];
330} dma_hw_t;
331
332#define dma_hw ((dma_hw_t *)DMA_BASE)
333static_assert(sizeof (dma_hw_t) == 0x0544, "");
334
335#endif // _HARDWARE_STRUCTS_DMA_H
336
address_mapped.h
dma_channel_hw_t
Definition: dma.h:27
dma_hw_t
Definition: dma.h:146
dma_irq_ctrl_hw_t
Definition: dma.h:124
dma_mpu_region_hw_t
Definition: dma.h:127