v2.0.0
adc.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_ADC_H
9#define _HARDWARE_STRUCTS_ADC_H
10
15#include "hardware/address_mapped.h"
16#include "hardware/regs/adc.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_adc
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
26typedef struct {
27 _REG_(ADC_CS_OFFSET) // ADC_CS
28 // ADC Control and Status
29 // 0x01ff0000 [24:16] RROBIN (0x000) Round-robin sampling
30 // 0x0000f000 [15:12] AINSEL (0x0) Select analog mux input
31 // 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error
32 // 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;...
33 // 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion
34 // 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1
35 // 0x00000004 [2] START_ONCE (0) Start a single conversion
36 // 0x00000002 [1] TS_EN (0) Power on temperature sensor
37 // 0x00000001 [0] EN (0) Power on ADC and enable its clock
38 io_rw_32 cs;
39
40 _REG_(ADC_RESULT_OFFSET) // ADC_RESULT
41 // Result of most recent ADC conversion
42 // 0x00000fff [11:0] RESULT (0x000)
43 io_ro_32 result;
44
45 _REG_(ADC_FCS_OFFSET) // ADC_FCS
46 // FIFO control and status
47 // 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold
48 // 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO
49 // 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed
50 // 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed
51 // 0x00000200 [9] FULL (0)
52 // 0x00000100 [8] EMPTY (0)
53 // 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data
54 // 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside...
55 // 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size
56 // 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion
57 io_rw_32 fcs;
58
59 _REG_(ADC_FIFO_OFFSET) // ADC_FIFO
60 // Conversion result FIFO
61 // 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error
62 // 0x00000fff [11:0] VAL (-)
63 io_ro_32 fifo;
64
65 _REG_(ADC_DIV_OFFSET) // ADC_DIV
66 // Clock divider
67 // 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor
68 // 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor
69 io_rw_32 div;
70
71 _REG_(ADC_INTR_OFFSET) // ADC_INTR
72 // Raw Interrupts
73 // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
74 io_ro_32 intr;
75
76 _REG_(ADC_INTE_OFFSET) // ADC_INTE
77 // Interrupt Enable
78 // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
79 io_rw_32 inte;
80
81 _REG_(ADC_INTF_OFFSET) // ADC_INTF
82 // Interrupt Force
83 // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
84 io_rw_32 intf;
85
86 _REG_(ADC_INTS_OFFSET) // ADC_INTS
87 // Interrupt status after masking & forcing
88 // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
89 io_ro_32 ints;
90} adc_hw_t;
91
92#define adc_hw ((adc_hw_t *)ADC_BASE)
93static_assert(sizeof (adc_hw_t) == 0x0024, "");
94
95#endif // _HARDWARE_STRUCTS_ADC_H
96
address_mapped.h
adc_hw_t
Definition: adc.h:26