| Digital Power Starter Kit 3 Firmware dsPIC33C Boost Converter Voltage Mode Control Example |

config_bits.c
1 /*
2 * File: config_bits.c
3 * Author: M91406
4 *
5 * Created on July 8, 2019, 2:39 PM
6 */
7
8
9 #include <xc.h>
10 #include "hal.h"
11
12 // Configuration bits: selected in the GUI
13
14 /*******************************************************************************************************/
15 // FICD
16
17 #pragma config ICS = PGD1 //ICD Communication Channel Select bits->Communicate on PGC2 and PGD2
18 #pragma config JTAGEN = OFF //JTAG Enable bit->JTAG is disabled
19 #pragma config NOBTSWP = DISABLED //BOOTSWP instruction disable bit->BOOTSWP instruction is disabled
20
21 /*******************************************************************************************************/
22 // FALTREG
23 //
24 // Alternate Working Register Interrupt Priority Level COnfiguration
25 // OFF -> Not Assigned
26 // IPL1 ... IPL6 -> Interrupt Priority Level 1 ... 6
27
28 #if (_OSTIMER_PRIORITY == 0)
29 #pragma config CTXT1 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
30 #elif (_OSTIMER_PRIORITY == 1)
31 #pragma config CTXT1 = IPL1 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
32 #elif (_OSTIMER_PRIORITY == 2)
33 #pragma config CTXT1 = IPL2 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
34 #elif (_OSTIMER_PRIORITY == 3)
35 #pragma config CTXT1 = IPL3 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
36 #elif (_OSTIMER_PRIORITY == 4)
37 #pragma config CTXT1 = IPL4 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
38 #elif (_OSTIMER_PRIORITY == 5)
39 #pragma config CTXT1 = IPL5 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
40 #elif (_OSTIMER_PRIORITY == 6)
41 #pragma config CTXT1 = IPL6 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
42 #else
43 #pragma config CTXT1 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
44 #pragma message "WARNING: operating system timer priority invalid."
45 #endif
46
47 #if (BOOST_VOUT_ISR_PRIORITY == 0)
48 #pragma config CTXT2 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
49 #elif (BOOST_VOUT_ISR_PRIORITY == 1)
50 #pragma config CTXT2 = IPL1 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
51 #elif (BOOST_VOUT_ISR_PRIORITY == 2)
52 #pragma config CTXT1 = IPL2 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
53 #elif (BOOST_VOUT_ISR_PRIORITY == 3)
54 #pragma config CTXT2 = IPL3 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
55 #elif (BOOST_VOUT_ISR_PRIORITY == 4)
56 #pragma config CTXT2 = IPL4 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
57 #elif (BOOST_VOUT_ISR_PRIORITY == 5)
58 #pragma config CTXT2 = IPL5 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
59 #elif (BOOST_VOUT_ISR_PRIORITY == 6)
60 #pragma config CTXT2 = IPL6 //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
61 #else
62 #pragma config CTXT2 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits
63 #pragma message "WARNING: boost converter output voltage loop control interrupt priority invalid."
64 #endif
65
66 #pragma config CTXT3 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits->Not Assigned
67 #pragma config CTXT4 = OFF //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits->Not Assigned
68
69 /*******************************************************************************************************/
70 // FSEC
71 #pragma config BWRP = OFF //Boot Segment Write-Protect bit->Boot Segment may be written
72 #pragma config BSS = DISABLED //Boot Segment Code-Protect Level bits->No Protection (other than BWRP)
73 #pragma config BSEN = OFF //Boot Segment Control bit->No Boot Segment
74 #pragma config GWRP = OFF //General Segment Write-Protect bit->General Segment may be written
75 #pragma config GSS = DISABLED //General Segment Code-Protect Level bits->No Protection (other than GWRP)
76 #pragma config CWRP = OFF //Configuration Segment Write-Protect bit->Configuration Segment may be written
77 #pragma config CSS = DISABLED //Configuration Segment Code-Protect Level bits->No Protection (other than CWRP)
78 #pragma config AIVTDIS = OFF //Alternate Interrupt Vector Table bit->Disabled AIVT
79
80 // FBSLIM
81 #pragma config BSLIM = 8191 //Boot Segment Flash Page Address Limit bits->8191
82
83 // FOSCSEL
84 #pragma config FNOSC = FRC //Oscillator Source Selection->Fast RC Oscillator with divide-by-N with PLL module (FRCPLL)
85 #pragma config IESO = OFF //Two-speed Oscillator Start-up Enable bit->Start up with user-selected oscillator source
86
87 // FOSC
88 #pragma config POSCMD = NONE //Primary Oscillator Mode Select bits->Primary Oscillator disabled
89 #pragma config OSCIOFNC = ON //OSC2 Pin Function bit->OSC2 is general purpose digital I/O pin
90 #pragma config FCKSM = CSECMD //Clock Switching Mode bits->Clock switching is enabled,Fail-safe Clock Monitor is disabled
91 #pragma config PLLKEN = ON //PLL Lock Status Control->PLL lock signal will be used to disable PLL clock output if lock is lost
92 #pragma config XTCFG = G3 //XT Config->24-32 MHz crystals
93 #pragma config XTBST = ENABLE //XT Boost->Boost the kick-start
94
95 // FWDT
96 //#pragma config RWDTPS = PS2147483648 //Run Mode Watchdog Timer Post Scaler select bits->1:2147483648
97 #pragma config RCLKSEL = LPRC //Watchdog Timer Clock Select bits->Always use LPRC
98 #pragma config WINDIS = OFF //Watchdog Timer Window Enable bit->Watchdog Timer in Window mode
99 #pragma config WDTWIN = WIN25 //Watchdog Timer Window Select bits->WDT Window is 25% of WDT period
100 //#pragma config SWDTPS = PS2147483648 //Sleep Mode Watchdog Timer Post Scaler select bits->1:2147483648
101 #pragma config FWDTEN = ON_SW //Watchdog Timer Enable bit->WDT controlled via SW, use WDTCON.ON bit
102
103 // FPOR
104 #pragma config BISTDIS = DISABLED //Memory BIST Feature Disable->mBIST on reset feature disabled
105
106 // FDMTIVTL
107 #pragma config DMTIVTL = 0 //Dead Man Timer Interval low word->0
108
109 // FDMTIVTH
110 #pragma config DMTIVTH = 0 //Dead Man Timer Interval high word->0
111
112 // FDMTCNTL
113 #pragma config DMTCNTL = 0 //Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF)->0
114
115 // FDMTCNTH
116 #pragma config DMTCNTH = 0 //Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF)->0
117
118 // FDMT
119 #pragma config DMTDIS = OFF //Dead Man Timer Disable bit->Dead Man Timer is Disabled and can be enabled by software
120
121 // FDEVOPT
122 #pragma config ALTI2C1 = OFF //Alternate I2C1 Pin bit->I2C1 mapped to SDA1/SCL1 pins
123 #pragma config ALTI2C2 = OFF //Alternate I2C2 Pin bit->I2C2 mapped to SDA2/SCL2 pins
124 #pragma config ALTI2C3 = OFF //Alternate I2C3 Pin bit->I2C3 mapped to SDA3/SCL3 pins
125 #pragma config SMBEN = SMBUS //SM Bus Enable->SMBus input threshold is enabled
126 #pragma config SPI2PIN = PPS //SPI2 Pin Select bit->SPI2 uses I/O remap (PPS) pins
127
128 // FBTSEQ
129 #pragma config BSEQ = 4095 //Relative value defining which partition will be active after device Reset; the partition containing a lower boot number will be active->4095
130 #pragma config IBSEQ = 4095 //The one's complement of BSEQ; must be calculated by the user and written during device programming.->4095
131
132 // FBOOT
133 #pragma config BTMODE = SINGLE //Device Boot Mode Configuration->Device is in Single Boot (legacy) mode