| Digital Power Starter Kit 3 Firmware dsPIC33C Boost Converter Voltage Mode Control Example |

p33c_dma.h
1 /* Microchip Technology Inc. and its subsidiaries. You may use this software
2 * and any derivatives exclusively with Microchip products.
3 *
4 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
5 * EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
6 * WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
7 * PARTICULAR PURPOSE, OR ITS INTERACTION WITH MICROCHIP PRODUCTS, COMBINATION
8 * WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.
9 *
10 * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
11 * INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
12 * WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
13 * BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
14 * FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS
15 * IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF
16 * ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
17 *
18 * MICROCHIP PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE
19 * TERMS.
20 */
21
22 /**************************************************************************************************
23 * @file p33c_dma.h
24 * @see p33c_dma.c
25 * @brief Generic DIrect Memory Access Driver Module (header file)
26 * @details
27 * This additional header file contains defines for all required bit-settings of all related
28 * special function registers of a peripheral module and/or instance.
29 * This file is an additional header file on top of the generic device header file.
30 *
31 *************************************************************************************************/
32
33 // This is a guard condition so that contents of this file are not included
34 // more than once.
35 #ifndef P33C_DMA_SFR_ABSTRACTION_H
36 #define P33C_DMA_SFR_ABSTRACTION_H
37
38 // Include standard header files
39 #include <xc.h> // include processor files - each processor file is guarded.
40 #include <stdint.h> // include standard integer data types
41 #include <stdbool.h> // include standard boolean data types
42 #include <stddef.h> // include standard definition data types
43
44
45 // GENERIC PDM DMA MODULE SPECIAL FUNCTION REGISTER SET
46 #ifndef P33C_DMA_MODULE_s
47
48 /***********************************************************************************
49 * @ingroup lib-layer-pral-properties-public-dma
50 * @struct P33C_DMA_MODULE_s
51 * @brief Abstracted set of Special Function Registers of the Direct Memory Access module
52 * @details
53 * This structure defines an abstracted set of Special Function Registers of
54 * Direct Memory Access peripheral module base registers. Users can use this
55 * abstracted set of registers to capture register settings from or write
56 * generic register settings to these peripheral base registers.
57 *
58 **********************************************************************************/
59
60 struct P33C_DMA_MODULE_s {
61 union {
62 volatile struct tagDMACONBITS bits; // Register bit-field
63 volatile uint16_t value; // 16-bit wide register value
64 } DmaCon; // DMACON: DMA Engine Control Register
65 union {
66 struct {
67 uint16_t DBUF : 16; // Register bit-field
68 } bits; // Register bit-field
69 uint16_t value; // 16-bit wide register value
70 } DmaBuf; // DMABUF: DMA Data Buffer Register
71 union {
72 struct {
73 uint16_t LADDR : 16; // Register bit-field
74 } bits; // Register bit-field
75 uint16_t value; // 16-bit wide register value
76 } DmaL; // DMAL: DMA Low Address Limit Register
77 union {
78 struct {
79 uint16_t HADDR : 16; // Register bit-field
80 } bits; // Register bit-field
81 uint16_t value; // 16-bit wide register value
82 } DmaH; // DMAH: DMA High Address Limit Register
83 } __attribute__((packed));
84 typedef struct P33C_DMA_MODULE_s P33C_DMA_MODULE_t; // DMA MODULE REGISTER SET
85
86 /*********************************************************************************
87 * @fn volatile struct P33C_DMA_MODULE_s* p33c_DmaModule_GetHandle(void)
88 * @ingroup lib-layer-pral-functions-public-dma
89 * @brief Gets pointer to DMA Module SFR set
90 * @param void
91 * @return struct P33C_DMA_MODULE_s Pointer to DMA module special function register set object
92 *
93 * @details
94 * This function returns the pointer to a DMA module register set in
95 * Special Function Register memory space. This pointer can be used to
96 * directly write to/read from the Special Function Registers of the
97 * DMA peripheral module configuration.
98 *********************************************************************************/
99 #define p33c_DmaModule_GetHandle() (struct P33C_DMA_MODULE_s*)&DMACON
100
101 #endif // end of P33C_DMA_MODULE_s
102
103 // GENERIC DMA INSTANCE SPECIAL FUNCTION REGISTER SET
104 #ifndef P33C_DMA_INSTANCE_s
105
106 /***********************************************************************************
107 * @ingroup lib-layer-pral-properties-public-dma
108 * @struct P33C_DMA_INSTANCE_s
109 * @brief Abstracted set of Special Function Registers of a Direct MEmory Access peripheral instance
110 * @details
111 * This structure defines an abstracted set of Special Function Registers of
112 * Direct Memory Access peripheral instance registers. It provides an
113 * abstracted set of registers to capture register settings from or write
114 * generic register settings to this peripheral instance.
115 *
116 **********************************************************************************/
117
118 struct P33C_DMA_INSTANCE_s{
119 union {
120 volatile struct tagDMACH0BITS bits; // Register bit-field
121 volatile uint16_t value; // 16-bit wide register value
122 } DMACHx; // DMACHx: DMA Channel x Control Register
123 union {
124 volatile struct tagDMAINT0BITS bits; // Register bit-field
125 volatile uint16_t value; // 16-bit wide register value
126 } DMAINTx; // DMAINTn: DMA Channel n Interrupt Control Register
127 union {
128 struct {
129 uint16_t SADDR : 16; // Register bit-field
130 } bits; // Register bit-field
131 uint16_t value; // 16-bit wide register value
132 } DMASRCx; // DMASRCx: DMA Channel x Source Address Register
133 union {
134 struct {
135 uint16_t DADDR : 16; // Register bit-field
136 } bits; // Register bit-field
137 uint16_t value; // 16-bit wide register value
138 } DMADSTx; // DDMADSTx: DMA Channel x Destination Address Register
139 union {
140 struct {
141 uint16_t CNT : 16; // Register bit-field
142 } bits; // Register bit-field
143 uint16_t value; // 16-bit wide register value
144 } DMACNTx; // DMACNTn: DMA Channel n Count Register
145 } __attribute__((packed));
146 typedef struct P33C_DMA_INSTANCE_s P33C_DMA_INSTANCE_t; // DMA INSTANCE REGISTER SET
147
148 /*********************************************************************************
149 * @ingroup lib-layer-pral-properties-public-dma
150 * @def P33C_DMA_COUNT
151 * @brief Derives the number of available DMA channel instances
152 * @details
153 * This macro derives the number of available DMA channel instances.
154 * This value is required to verify and limit user access to available
155 * instances only.
156 **********************************************************************************/
157 #if defined (DMACH7)
158 #define P33C_DMA_COUNT 8
159 #elif defined (DMACH6)
160 #define P33C_DMA_COUNT 7
161 #elif defined (DMACH5)
162 #define P33C_DMA_COUNT 6
163 #elif defined (DMACH4)
164 #define P33C_DMA_COUNT 5
165 #elif defined (DMACH3)
166 #define P33C_DMA_COUNT 4
167 #elif defined (DMACH2)
168 #define P33C_DMA_COUNT 3
169 #elif defined (DMACH1)
170 #define P33C_DMA_COUNT 2
171 #else
172 #pragma message "selected device has no supported DMA channels"
173 #endif
174
175 /*********************************************************************************
176 * @ingroup lib-layer-pral-properties-public-dma
177 * @def P33C_DMA_SFR_OFFSET
178 * @brief Derives the address offset between two peripheral instances
179 * @details
180 * This macro derives the address offset between two peripheral instances.
181 * Users can use this address offset to derive the start address to/from which
182 * the register set should be written or read.
183 **********************************************************************************/
184 #ifndef P33C_DMA_SFR_OFFSET
185 #define P33C_DMA_SFR_OFFSET ((volatile uint16_t)&DMACH1 - (volatile uint16_t)&DMACH0)
186 #endif
187
188 /*********************************************************************************
189 * @ingroup lib-layer-pral-properties-public-dma
190 * @def P33C_DACL_DEFAULT
191 * @brief Derives the address offset between two peripheral instances
192 * @details
193 * This macro derives the minimum memory address of the total memory range
194 * addressable by the DMA peripheral instances. Users can use this address
195 * to restore the default memory range addressable by the DMA peripheral.
196 **********************************************************************************/
197
198 #define P33C_DACL_DEFAULT 0x0000 // Default DMA address range minimum address
199
200 /*********************************************************************************
201 * @ingroup lib-layer-pral-properties-public-dma
202 * @def P33C_DACH_DEFAULT
203 * @brief Derives the maximum address of the DMA addressable range
204 * @details
205 * This macro derives the maximum memory address of the total memory range
206 * addressable by the DMA peripheral instances. Users can use this address
207 * to restore the default memory range addressable by the DMA peripheral.
208 **********************************************************************************/
209
210 #define P33C_DACH_DEFAULT 0x4FFF // Default DMA address range maximum address
211
212 /*********************************************************************************
213 * @fn volatile struct P33C_DMA_MODULE_s* p33c_DmaModule_GetHandle(void)
214 * @ingroup lib-layer-pral-functions-public-dma
215 * @brief Gets pointer to DMA Module SFR set
216 * @param void
217 * @return struct P33C_DMA_MODULE_s Pointer to DMA module special function register set object
218 *
219 * @details
220 * This function returns the pointer to a DMA module register set in
221 * Special Function Register memory space. This pointer can be used to
222 * directly write to/read from the Special Function Registers of the
223 * DMA peripheral module configuration.
224 *********************************************************************************/
225
226 extern volatile uint16_t* p33c_DmaChannel_Handles[];
227 #define p33c_DmaInstance_GetHandle(x) (struct P33C_DMA_INSTANCE_s*)p33c_DmaChannel_Handles[(x)]
228
229
230 #endif // end of P33C_DMA_INSTANCE_s
231
232 #define DMATRG_INT0 0x00 // External Interrupt 0
233 #define DMATRG_SCCP1 0x01 // SCCP1 Interrupt
234 #define DMATRG_SPI1_RX 0x02 // SPI1 Receiver
235 #define DMATRG_SPI1_TX 0x03 // SPI1 Transmitter
236 #define DMATRG_UART1_RX 0x04 // UART1 Receiver
237 #define DMATRG_UART1_TX 0x05 // UART1 Transmitter
238 #define DMATRG_ECC_BERR 0x06 // ECC Single Bit Error
239 #define DMATRG_NVM_WRITE 0x07 // NVM Write Complete
240 #define DMATRG_INT1 0x08 // External Interrupt 1
241 #define DMATRG_SI2C1 0x09 // I2C1 Device Event
242 #define DMATRG_MI2C1 0x0A // I2C1 Host Event
243 #define DMATRG_INT2 0x0B // External Interrupt 2
244 #define DMATRG_SCCP2 0x0C // SCCP2 Interrupt
245 #define DMATRG_INT3 0x0D // External Interrupt 3
246 #define DMATRG_UART2_RX 0x0E // UART2 Receiver
247 #define DMATRG_UART2_TX 0x0F // UART2 Transmitter
248 #define DMATRG_SPI2_RX 0x10 // SPI2 Receiver
249 #define DMATRG_SPI2_TX 0x11 // SPI2 Transmitter
250 #define DMATRG_SCCP3 0x12 // SCCP3 Interrupt
251 #define DMATRG_SI2C2 0x13 // I2C2 Device Event
252 #define DMATRG_MI2C2 0x14 // I2C2 Host Event
253 #define DMATRG_SCCP4 0x15 // SCCP4 Interrupt
254 #define DMATRG_SCCP5 0x16 // SCCP5 Interrupt
255 #define DMATRG_SCCP6 0x17 // SCCP6 Interrupt
256 #define DMATRG_CRC 0x18 // CRC Generator Interrupt
257 #define DMATRG_PWM_EVTA 0x19 // PWM Event A
258 #define DMATRG_PWM_EVTB 0x1B // PWM Event B
259 #define DMATRG_PG1EVT 0x1C // PWM Generator 1
260 #define DMATRG_PG2EVT 0x1D // PWM Generator 2
261 #define DMATRG_PG3EVT 0x1E // PWM Generator 3
262 #define DMATRG_PG4EVT 0x1F // PWM Generator 4
263 #define DMATRG_PG5EVT 0x20 // PWM Generator 5
264 #define DMATRG_PG6EVT 0x21 // PWM Generator 6
265 #define DMATRG_PG7EVT 0x22 // PWM Generator 7
266 #define DMATRG_PG8EVT 0x23 // PWM Generator 8
267 #define DMATRG_PWM_EVTC 0x24 // PWM Event C
268 #define DMATRG_SENT1 0x25 // SENT1 TX/RX
269 #define DMATRG_SENT2 0x26 // SENT2 TX/RX
270 #define DMATRG_ADC_DONE 0x27 // ADC1 Group Convert Done
271 #define DMATRG_AN0_DONE 0x28 // ADC Done AN0
272 #define DMATRG_AN1_DONE 0x29 // ADC Done AN1
273 #define DMATRG_AN2_DONE 0x2A // ADC Done AN2
274 #define DMATRG_AN3_DONE 0x2B // ADC Done AN3
275 #define DMATRG_AN4_DONE 0x2C // ADC Done AN4
276 #define DMATRG_AN5_DONE 0x2D // ADC Done AN5
277 #define DMATRG_AN6_DONE 0x2E // ADC Done AN6
278 #define DMATRG_AN7_DONE 0x2F // ADC Done AN7
279 #define DMATRG_AN8_DONE 0x30 // ADC Done AN8
280 #define DMATRG_AN9_DONE 0x31 // ADC Done AN9
281 #define DMATRG_AN10_DONE 0x32 // ADC Done AN10
282 #define DMATRG_AN11_DONE 0x33 // ADC Done AN11
283 #define DMATRG_AN12_DONE 0x34 // ADC Done AN12
284 #define DMATRG_AN13_DONE 0x35 // ADC Done AN13
285 #define DMATRG_AN14_DONE 0x36 // ADC Done AN14
286 #define DMATRG_AN15_DONE 0x37 // ADC Done AN15
287 #define DMATRG_AN16_DONE 0x38 // ADC Done AN16
288 #define DMATRG_AN17_DONE 0x39 // ADC Done AN17
289 #define DMATRG_AN18_DONE 0x3A // ADC Done AN18
290 #define DMATRG_AN19_DONE 0x3B // ADC Done AN19
291 #define DMATRG_AN20_DONE 0x3C // ADC Done AN20
292 #define DMATRG_AN21_DONE 0x3D // ADC Done AN21
293 #define DMATRG_AN22_DONE 0x3E // ADC Done AN22
294 #define DMATRG_AN23_DONE 0x3F // ADC Done AN23
295 #define DMATRG_AD1FLTR1 0x40 // Oversample Filter 1
296 #define DMATRG_AD1FLTR2 0x41 // Oversample Filter 2
297 #define DMATRG_AD1FLTR3 0x42 // Oversample Filter 3
298 #define DMATRG_AD1FLTR4 0x43 // Oversample Filter 4
299 #define DMATRG_CLC1 0x44 // CPC1 Positive Edge Interrupt
300 #define DMATRG_CLC2 0x45 // CPC2 Positive Edge Interrupt
301 #define DMATRG_SPI1_FLT 0x46 // SPI1 Fault Interrupt
302 #define DMATRG_SPI2_FLT 0x47 // SPI2 Fault Interrupt
303 #define DMATRG_PWM_EVTD 0x57 // PWM Event D
304 #define DMATRG_PWM_EVTE 0x58 // PWM Event E
305 #define DMATRG_PWM_EVTF 0x59 // PWM Event F
306 #define DMATRG_SCCP7 0x5C // SCCP7 Interrupt
307 #define DMATRG_SCCP8 0x5D // SCCP8 Interrupt
308 #define DMATRG_CLC3 0x60 // CPC1 Positive Edge Interrupt
309 #define DMATRG_CLC4 0x61 // CPC2 Positive Edge Interrupt
310 #define DMATRG_SPI3_RX 0x62 // SPI3 Receiver
311 #define DMATRG_SPI3_TX 0x63 // SPI3 Transmitter
312 #define DMATRG_SI2C3 0x64 // I2C3 Device Event
313 #define DMATRG_MI2C3 0x65 // I2C3 Host Event
314 #define DMATRG_SPI3_FLT 0x66 // SPI3 Fault Interrupt
315 #define DMATRG_MCCP9 0x67 // MCCP9 Interrupt
316 #define DMATRG_UART3_RX 0x68 // UART3 Receiver
317 #define DMATRG_UART3_TX 0x69 // UART3 Transmitter
318 #define DMATRG_AN24_DONE 0x6A // ADC Done AN24
319 #define DMATRG_AN25_DONE 0x6B // ADC Done AN25
320 #define DMATRG_PMP_EVT 0x6C // PMP Event
321 #define DMATRG_PMP_ERR 0x6D // PMP Error Event
322
323
324 /* ********************************************************************************************* *
325 * API FUNCTION PROTOTYPES
326 * ********************************************************************************************* */
327
328 extern volatile uint16_t p33c_DmaModule_Dispose(void);
329 extern volatile struct P33C_DMA_MODULE_s p33c_DmaModule_ConfigRead(void);
330 extern volatile uint16_t p33c_DmaModule_ConfigWrite(
331 volatile struct P33C_DMA_MODULE_s dmaConfig
332 );
333
334
335 extern volatile uint16_t p33c_DmaInstance_Dispose(volatile uint16_t dmaInstance);
336 extern volatile struct P33C_DMA_INSTANCE_s p33c_DmaInstance_ConfigRead(volatile uint16_t dmaInstance);
337 extern volatile uint16_t p33c_DmaInstance_ConfigWrite(
338 volatile uint16_t dmaInstance,
339 volatile struct P33C_DMA_INSTANCE_s dmaConfig
340 );
341
342 /* ********************************************************************************************* *
343 * DMA INSTANCE CONFIGURATION TEMPLATES
344 * ********************************************************************************************* */
345 extern volatile struct P33C_DMA_MODULE_s dmaModuleConfigClear;
346 extern volatile struct P33C_DMA_INSTANCE_s dmaInstanceConfigClear;
347
348 #endif /* P33C_DMA_SFR_ABSTRACTION_H */
349
350 // end of file
P33C_DMA_MODULE_s::DBUF
uint16_t DBUF
Definition: p33c_dma.h:67
P33C_DMA_MODULE_s::LADDR
uint16_t LADDR
Definition: p33c_dma.h:73
P33C_DMA_INSTANCE_s::SADDR
uint16_t SADDR
Definition: p33c_dma.h:129
P33C_DMA_INSTANCE_s::DMACHx
union P33C_DMA_INSTANCE_s::@106 DMACHx
P33C_DMA_MODULE_s::DmaBuf
union P33C_DMA_MODULE_s::@93 DmaBuf
P33C_DMA_INSTANCE_s::DADDR
uint16_t DADDR
Definition: p33c_dma.h:135
P33C_DMA_INSTANCE_s::DMAINTx
union P33C_DMA_INSTANCE_s::@107 DMAINTx
P33C_DMA_MODULE_s::value
uint16_t value
Definition: p33c_dma.h:69
P33C_DMA_INSTANCE_s::CNT
uint16_t CNT
Definition: p33c_dma.h:141
P33C_DMA_INSTANCE_s
Definition: p33c_dma.h:118
P33C_DMA_MODULE_s::value
volatile uint16_t value
Definition: p33c_dma.h:63
P33C_DMA_MODULE_s::DmaCon
union P33C_DMA_MODULE_s::@92 DmaCon
P33C_DMA_INSTANCE_s::value
uint16_t value
Definition: p33c_dma.h:131
P33C_DMA_INSTANCE_s::bits
volatile struct tagDMACH0BITS bits
Definition: p33c_dma.h:120
P33C_DMA_MODULE_s
Definition: p33c_dma.h:60
P33C_DMA_INSTANCE_s::DMASRCx
union P33C_DMA_INSTANCE_s::@108 DMASRCx
P33C_DMA_INSTANCE_s::DMACNTx
union P33C_DMA_INSTANCE_s::@110 DMACNTx
P33C_DMA_MODULE_s::bits
volatile struct tagDMACONBITS bits
Definition: p33c_dma.h:62
P33C_DMA_INSTANCE_s::value
volatile uint16_t value
Definition: p33c_dma.h:121
P33C_DMA_MODULE_s::HADDR
uint16_t HADDR
Definition: p33c_dma.h:79
P33C_DMA_INSTANCE_s::DMADSTx
union P33C_DMA_INSTANCE_s::@109 DMADSTx
P33C_DMA_MODULE_s::DmaL
union P33C_DMA_MODULE_s::@94 DmaL
P33C_DMA_MODULE_s::DmaH
union P33C_DMA_MODULE_s::@95 DmaH