| Digital Power Starter Kit 3 Firmware dsPIC33C Boost Converter Voltage Mode Control Example |

p33c_gpio.h
1 /* Microchip Technology Inc. and its subsidiaries. You may use this software
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3 *
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21
22 /**************************************************************************************************
23 * @file p33c_gpio.h
24 * @see p33c_gpio.c
25 * @brief Generic Digital Signal Processor Driver Module (header file)
26 * @details
27 * This additional header file contains defines for all required bit-settings of all related
28 * special function registers of a peripheral module and/or instance.
29 * This file is an additional header file on top of the generic device header file.
30 *
31 *************************************************************************************************/
32 /* Revision history:
33 * 12/10/20 1.0 initial release
34 *************************************************************************************************/
35
36 // This is a guard condition so that contents of this file are not included
37 // more than once.
38 #ifndef P33C_GPIO_SFR_ABSTRACTION_H
39 #define P33C_GPIO_SFR_ABSTRACTION_H
40
41 // Include standard header files
42 #include <xc.h> // include processor files - each processor file is guarded.
43 #include <stdint.h> // include standard integer data types
44 #include <stdbool.h> // include standard boolean data types
45 #include <stddef.h> // include standard definition data types
46
47 // GENERIC GPIO INSTANCE SPECIAL FUNCTION REGISTER SET
48 // DO NOT REORDER ELEMENTS AS THEY MAP ONTO DEVICE REGISTER MEMORY !!!
49 #ifndef P33C_GPIO_INSTANCE_s
50
51 struct ANSELx_s {
52 uint16_t ANSELx0:1; // Bit 0: Device Port Analog Select Register bit
53 uint16_t ANSELx1:1; // Bit 1: Device Port Analog Select Register bit
54 uint16_t ANSELx2:1; // Bit 2: Device Port Analog Select Register bit
55 uint16_t ANSELx3:1; // Bit 3: Device Port Analog Select Register bit
56 uint16_t ANSELx4:1; // Bit 4: Device Port Analog Select Register bit
57 uint16_t ANSELx5:1; // Bit 5: Device Port Analog Select Register bit
58 uint16_t ANSELx6:1; // Bit 6: Device Port Analog Select Register bit
59 uint16_t ANSELx7:1; // Bit 7: Device Port Analog Select Register bit
60 uint16_t ANSELx8:1; // Bit 8: Device Port Analog Select Register bit
61 uint16_t ANSELx9:1; // Bit 9: Device Port Analog Select Register bit
62 uint16_t ANSELx10:1; // Bit 10: Device Port Analog Select Register bit
63 uint16_t ANSELx11:1; // Bit 11: Device Port Analog Select Register bit
64 uint16_t ANSELx12:1; // Bit 12: Device Port Analog Select Register bit
65 uint16_t ANSELx13:1; // Bit 13: Device Port Analog Select Register bit
66 uint16_t ANSELx14:1; // Bit 14: Device Port Analog Select Register bit
67 uint16_t ANSELx15:1; // Bit 15: Device Port Analog Select Register bit
68 }__attribute__((packed)); //ANSELx: ANALOG SELECT FOR PORTx REGISTER
69 typedef struct ANSELx_s ANSELx_t; //ANSELx: ANALOG SELECT FOR PORTx REGISTER DATA TYPE
70
71 struct TRISx_s {
72 uint16_t TRISx0:1; // Bit 0: Device Port Output Enable Register bit
73 uint16_t TRISx1:1; // Bit 1: Device Port Output Enable Register bit
74 uint16_t TRISx2:1; // Bit 2: Device Port Output Enable Register bit
75 uint16_t TRISx3:1; // Bit 3: Device Port Output Enable Register bit
76 uint16_t TRISx4:1; // Bit 4: Device Port Output Enable Register bit
77 uint16_t TRISx5:1; // Bit 5: Device Port Output Enable Register bit
78 uint16_t TRISx6:1; // Bit 6: Device Port Output Enable Register bit
79 uint16_t TRISx7:1; // Bit 7: Device Port Output Enable Register bit
80 uint16_t TRISx8:1; // Bit 8: Device Port Output Enable Register bit
81 uint16_t TRISx9:1; // Bit 9: Device Port Output Enable Register bit
82 uint16_t TRISx10:1; // Bit 10: Device Port Output Enable Register bit
83 uint16_t TRISx11:1; // Bit 11: Device Port Output Enable Register bit
84 uint16_t TRISx12:1; // Bit 12: Device Port Output Enable Register bit
85 uint16_t TRISx13:1; // Bit 13: Device Port Output Enable Register bit
86 uint16_t TRISx14:1; // Bit 14: Device Port Output Enable Register bit
87 uint16_t TRISx15:1; // Bit 15: Device Port Output Enable Register bit
88 }__attribute__((packed)); //TRISx: OUTPUT ENABLE FOR PORTx REGISTER
89 typedef struct TRISx_s TRISx_t; //TRISx: OUTPUT ENABLE FOR PORTx REGISTER DATA TYPE
90
91 struct PORTx_s {
92 uint16_t PORTx0:1; // Bit 0: Device Port Data Input Value Register bit
93 uint16_t PORTx1:1; // Bit 1: Device Port Data Input Value Register bit
94 uint16_t PORTx2:1; // Bit 2: Device Port Data Input Value Register bit
95 uint16_t PORTx3:1; // Bit 3: Device Port Data Input Value Register bit
96 uint16_t PORTx4:1; // Bit 4: Device Port Data Input Value Register bit
97 uint16_t PORTx5:1; // Bit 5: Device Port Data Input Value Register bit
98 uint16_t PORTx6:1; // Bit 6: Device Port Data Input Value Register bit
99 uint16_t PORTx7:1; // Bit 7: Device Port Data Input Value Register bit
100 uint16_t PORTx8:1; // Bit 8: Device Port Data Input Value Register bit
101 uint16_t PORTx9:1; // Bit 9: Device Port Data Input Value Register bit
102 uint16_t PORTx10:1; // Bit 10: Device Port Data Input Value Register bit
103 uint16_t PORTx11:1; // Bit 11: Device Port Data Input Value Register bit
104 uint16_t PORTx12:1; // Bit 12: Device Port Data Input Value Register bit
105 uint16_t PORTx13:1; // Bit 13: Device Port Data Input Value Register bit
106 uint16_t PORTx14:1; // Bit 14: Device Port Data Input Value Register bit
107 uint16_t PORTx15:1; // Bit 15: Device Port Data Input Value Register bit
108 }__attribute__((packed)); // PORTx: INPUT DATA FOR PORTx REGISTER
109 typedef struct PORTx_s PORTx_t; // PORTx: INPUT DATA FOR PORTx REGISTER DATA TYPE
110
111 struct LATx_s {
112 uint16_t LATx0:1; // Bit 0: Device Port Latch Register bit
113 uint16_t LATx1:1; // Bit 1: Device Port Latch Register bit
114 uint16_t LATx2:1; // Bit 2: Device Port Latch Register bit
115 uint16_t LATx3:1; // Bit 3: Device Port Latch Register bit
116 uint16_t LATx4:1; // Bit 4: Device Port Latch Register bit
117 uint16_t LATx5:1; // Bit 5: Device Port Latch Register bit
118 uint16_t LATx6:1; // Bit 6: Device Port Latch Register bit
119 uint16_t LATx7:1; // Bit 7: Device Port Latch Register bit
120 uint16_t LATx8:1; // Bit 8: Device Port Latch Register bit
121 uint16_t LATx9:1; // Bit 9: Device Port Latch Register bit
122 uint16_t LATx10:1; // Bit 10: Device Port Latch Register bit
123 uint16_t LATx11:1; // Bit 11: Device Port Latch Register bit
124 uint16_t LATx12:1; // Bit 12: Device Port Latch Register bit
125 uint16_t LATx13:1; // Bit 13: Device Port Latch Register bit
126 uint16_t LATx14:1; // Bit 14: Device Port Latch Register bit
127 uint16_t LATx15:1; // Bit 15: Device Port Latch Register bit
128 }__attribute__((packed)); // LATx: OUTPUT PORT LATCH DATA FOR PORTx REGISTER
129 typedef struct LATx_s LATx_t; // LATx: OUTPUT PORT LATCH DATA FOR PORTx REGISTER DATA TYPE
130
131 struct ODCx_s {
132 uint16_t ODCx0:1; // Bit 0: Device Port Open-Drain Enable Register bit
133 uint16_t ODCx1:1; // Bit 1: Device Port Open-Drain Enable Register bit
134 uint16_t ODCx2:1; // Bit 2: Device Port Open-Drain Enable Register bit
135 uint16_t ODCx3:1; // Bit 3: Device Port Open-Drain Enable Register bit
136 uint16_t ODCx4:1; // Bit 4: Device Port Open-Drain Enable Register bit
137 uint16_t ODCx5:1; // Bit 5: Device Port Open-Drain Enable Register bit
138 uint16_t ODCx6:1; // Bit 6: Device Port Open-Drain Enable Register bit
139 uint16_t ODCx7:1; // Bit 7: Device Port Open-Drain Enable Register bit
140 uint16_t ODCx8:1; // Bit 8: Device Port Open-Drain Enable Register bit
141 uint16_t ODCx9:1; // Bit 9: Device Port Open-Drain Enable Register bit
142 uint16_t ODCx10:1; // Bit 10: Device Port Open-Drain Enable Register bit
143 uint16_t ODCx11:1; // Bit 11: Device Port Open-Drain Enable Register bit
144 uint16_t ODCx12:1; // Bit 12: Device Port Open-Drain Enable Register bit
145 uint16_t ODCx13:1; // Bit 13: Device Port Open-Drain Enable Register bit
146 uint16_t ODCx14:1; // Bit 14: Device Port Open-Drain Enable Register bit
147 uint16_t ODCx15:1; // Bit 15: Device Port Open-Drain Enable Register bit
148 }__attribute__((packed)); // ODCx: OPEN-DRAIN ENABLE FOR PORTx REGISTER
149 typedef struct ODCx_s ODCx_t; // ODCx: OPEN-DRAIN ENABLE FOR PORTx REGISTER DATA TYPE
150
151 struct CNPUx_s {
152 uint16_t CNPUx0:1; // Bit 0: Device Port Change Notification Pull-Up Enable Register bit
153 uint16_t CNPUx1:1; // Bit 1: Device Port Change Notification Pull-Up Enable Register bit
154 uint16_t CNPUx2:1; // Bit 2: Device Port Change Notification Pull-Up Enable Register bit
155 uint16_t CNPUx3:1; // Bit 3: Device Port Change Notification Pull-Up Enable Register bit
156 uint16_t CNPUx4:1; // Bit 4: Device Port Change Notification Pull-Up Enable Register bit
157 uint16_t CNPUx5:1; // Bit 5: Device Port Change Notification Pull-Up Enable Register bit
158 uint16_t CNPUx6:1; // Bit 6: Device Port Change Notification Pull-Up Enable Register bit
159 uint16_t CNPUx7:1; // Bit 7: Device Port Change Notification Pull-Up Enable Register bit
160 uint16_t CNPUx8:1; // Bit 8: Device Port Change Notification Pull-Up Enable Register bit
161 uint16_t CNPUx9:1; // Bit 9: Device Port Change Notification Pull-Up Enable Register bit
162 uint16_t CNPUx10:1; // Bit 10: Device Port Change Notification Pull-Up Enable Register bit
163 uint16_t CNPUx11:1; // Bit 11: Device Port Change Notification Pull-Up Enable Register bit
164 uint16_t CNPUx12:1; // Bit 12: Device Port Change Notification Pull-Up Enable Register bit
165 uint16_t CNPUx13:1; // Bit 13: Device Port Change Notification Pull-Up Enable Register bit
166 uint16_t CNPUx14:1; // Bit 14: Device Port Change Notification Pull-Up Enable Register bit
167 uint16_t CNPUx15:1; // Bit 15: Device Port Change Notification Pull-Up Enable Register bit
168 }__attribute__((packed)); // CNPUx: CHANGE NOTIFICATION PULL-UP ENABLE FOR PORTx REGISTER
169 typedef struct CNPUx_s CNPUx_t; // CNPUx: CHANGE NOTIFICATION PULL-UP ENABLE FOR PORTx REGISTER DATA TYPE
170
171 struct CNPDx_s {
172 uint16_t CNPDx0:1; // Bit 0: Device Port Change Notification Pull-Down Enable Register bit
173 uint16_t CNPDx1:1; // Bit 1: Device Port Change Notification Pull-Down Enable Register bit
174 uint16_t CNPDx2:1; // Bit 2: Device Port Change Notification Pull-Down Enable Register bit
175 uint16_t CNPDx3:1; // Bit 3: Device Port Change Notification Pull-Down Enable Register bit
176 uint16_t CNPDx4:1; // Bit 4: Device Port Change Notification Pull-Down Enable Register bit
177 uint16_t CNPDx5:1; // Bit 5: Device Port Change Notification Pull-Down Enable Register bit
178 uint16_t CNPDx6:1; // Bit 6: Device Port Change Notification Pull-Down Enable Register bit
179 uint16_t CNPDx7:1; // Bit 7: Device Port Change Notification Pull-Down Enable Register bit
180 uint16_t CNPDx8:1; // Bit 8: Device Port Change Notification Pull-Down Enable Register bit
181 uint16_t CNPDx9:1; // Bit 9: Device Port Change Notification Pull-Down Enable Register bit
182 uint16_t CNPDx10:1; // Bit 10: Device Port Change Notification Pull-Down Enable Register bit
183 uint16_t CNPDx11:1; // Bit 11: Device Port Change Notification Pull-Down Enable Register bit
184 uint16_t CNPDx12:1; // Bit 12: Device Port Change Notification Pull-Down Enable Register bit
185 uint16_t CNPDx13:1; // Bit 13: Device Port Change Notification Pull-Down Enable Register bit
186 uint16_t CNPDx14:1; // Bit 14: Device Port Change Notification Pull-Down Enable Register bit
187 uint16_t CNPDx15:1; // Bit 15: Device Port Change Notification Pull-Down Enable Register bit
188 }__attribute__((packed)); // CNPDx: CHANGE NOTIFICATION PULL-DOWN ENABLE FOR PORTx REGISTER
189 typedef struct CNPDx_s CNPDx_t; // CNPDx: CHANGE NOTIFICATION PULL-DOWN ENABLE FOR PORTx REGISTER DATA TYPE
190
191 struct CNEN0x_s {
192 uint16_t CNEN0x0:1; // Bit 0: Device Port Change Notification Interrupt Enable Register bit
193 uint16_t CNEN0x1:1; // Bit 1: Device Port Change Notification Interrupt Enable Register bit
194 uint16_t CNEN0x2:1; // Bit 2: Device Port Change Notification Interrupt Enable Register bit
195 uint16_t CNEN0x3:1; // Bit 3: Device Port Change Notification Interrupt Enable Register bit
196 uint16_t CNEN0x4:1; // Bit 4: Device Port Change Notification Interrupt Enable Register bit
197 uint16_t CNEN0x5:1; // Bit 5: Device Port Change Notification Interrupt Enable Register bit
198 uint16_t CNEN0x6:1; // Bit 6: Device Port Change Notification Interrupt Enable Register bit
199 uint16_t CNEN0x7:1; // Bit 7: Device Port Change Notification Interrupt Enable Register bit
200 uint16_t CNEN0x8:1; // Bit 8: Device Port Change Notification Interrupt Enable Register bit
201 uint16_t CNEN0x9:1; // Bit 9: Device Port Change Notification Interrupt Enable Register bit
202 uint16_t CNEN0x10:1; // Bit 10: Device Port Change Notification Interrupt Enable Register bit
203 uint16_t CNEN0x11:1; // Bit 11: Device Port Change Notification Interrupt Enable Register bit
204 uint16_t CNEN0x12:1; // Bit 12: Device Port Change Notification Interrupt Enable Register bit
205 uint16_t CNEN0x13:1; // Bit 13: Device Port Change Notification Interrupt Enable Register bit
206 uint16_t CNEN0x14:1; // Bit 14: Device Port Change Notification Interrupt Enable Register bit
207 uint16_t CNEN0x15:1; // Bit 15: Device Port Change Notification Interrupt Enable Register bit
208 }__attribute__((packed)); // CNEN0x: CHANGE NOTIFICATION INTERRUPT ENABLE FOR PORTx REGISTER
209 typedef struct CNEN0x_s CNCEN0x_t; // CNEN0x: CHANGE NOTIFICATION INTERRUPT ENABLE FOR PORTx REGISTER DATA TYPE
210
211 struct CNSTATx_s {
212 uint16_t CNSTATx0:1; // Bit 0: Device Port Change Notification Status Register bit
213 uint16_t CNSTATx1:1; // Bit 1: Device Port Change Notification Status Register bit
214 uint16_t CNSTATx2:1; // Bit 2: Device Port Change Notification Status Register bit
215 uint16_t CNSTATx3:1; // Bit 3: Device Port Change Notification Status Register bit
216 uint16_t CNSTATx4:1; // Bit 4: Device Port Change Notification Status Register bit
217 uint16_t CNSTATx5:1; // Bit 5: Device Port Change Notification Status Register bit
218 uint16_t CNSTATx6:1; // Bit 6: Device Port Change Notification Status Register bit
219 uint16_t CNSTATx7:1; // Bit 7: Device Port Change Notification Status Register bit
220 uint16_t CNSTATx8:1; // Bit 8: Device Port Change Notification Status Register bit
221 uint16_t CNSTATx9:1; // Bit 9: Device Port Change Notification Status Register bit
222 uint16_t CNSTATx10:1; // Bit 10: Device Port Change Notification Status Register bit
223 uint16_t CNSTATx11:1; // Bit 11: Device Port Change Notification Status Register bit
224 uint16_t CNSTATx12:1; // Bit 12: Device Port Change Notification Status Register bit
225 uint16_t CNSTATx13:1; // Bit 13: Device Port Change Notification Status Register bit
226 uint16_t CNSTATx14:1; // Bit 14: Device Port Change Notification Status Register bit
227 uint16_t CNSTATx15:1; // Bit 15: Device Port Change Notification Status Register bit
228 }__attribute__((packed)); // CNSTATx: CHANGE NOTIFICATION STATUS FOR PORTx REGISTER
229 typedef struct CNSTATx_s CNSTATx_t; // CNSTATx: CHANGE NOTIFICATION STATUS FOR PORTx REGISTER DATA TYPE
230
231 struct CNEN1x_s {
232 uint16_t CNEN1x0:1; // Bit 0: Device Port Change Notification Edge Select Register bit
233 uint16_t CNEN1x1:1; // Bit 1: Device Port Change Notification Edge Select Register bit
234 uint16_t CNEN1x2:1; // Bit 2: Device Port Change Notification Edge Select Register bit
235 uint16_t CNEN1x3:1; // Bit 3: Device Port Change Notification Edge Select Register bit
236 uint16_t CNEN1x4:1; // Bit 4: Device Port Change Notification Edge Select Register bit
237 uint16_t CNEN1x5:1; // Bit 5: Device Port Change Notification Edge Select Register bit
238 uint16_t CNEN1x6:1; // Bit 6: Device Port Change Notification Edge Select Register bit
239 uint16_t CNEN1x7:1; // Bit 7: Device Port Change Notification Edge Select Register bit
240 uint16_t CNEN1x8:1; // Bit 8: Device Port Change Notification Edge Select Register bit
241 uint16_t CNEN1x9:1; // Bit 9: Device Port Change Notification Edge Select Register bit
242 uint16_t CNEN1x10:1; // Bit 10: Device Port Change Notification Edge Select Register bit
243 uint16_t CNEN1x11:1; // Bit 11: Device Port Change Notification Edge Select Register bit
244 uint16_t CNEN1x12:1; // Bit 12: Device Port Change Notification Edge Select Register bit
245 uint16_t CNEN1x13:1; // Bit 13: Device Port Change Notification Edge Select Register bit
246 uint16_t CNEN1x14:1; // Bit 14: Device Port Change Notification Edge Select Register bit
247 uint16_t CNEN1x15:1; // Bit 15: Device Port Change Notification Edge Select Register bit
248 }__attribute__((packed)); // CNEN1x: CHANGE NOTIFICATION EDGE SELECT FOR PORTx REGISTER
249 typedef struct CNEN1x_s CNCEN1x_t; // CNEN1x: CHANGE NOTIFICATION EDGE SELECT FOR PORTx REGISTER DATA TYPE
250
251 struct CNFx_s {
252 uint16_t CNFx0:1; // Bit 0: Device Port Change Notification Interrupt Flag Register bit
253 uint16_t CNFx1:1; // Bit 1: Device Port Change Notification Interrupt Flag Register bit
254 uint16_t CNFx2:1; // Bit 2: Device Port Change Notification Interrupt Flag Register bit
255 uint16_t CNFx3:1; // Bit 3: Device Port Change Notification Interrupt Flag Register bit
256 uint16_t CNFx4:1; // Bit 4: Device Port Change Notification Interrupt Flag Register bit
257 uint16_t CNFx5:1; // Bit 5: Device Port Change Notification Interrupt Flag Register bit
258 uint16_t CNFx6:1; // Bit 6: Device Port Change Notification Interrupt Flag Register bit
259 uint16_t CNFx7:1; // Bit 7: Device Port Change Notification Interrupt Flag Register bit
260 uint16_t CNFx8:1; // Bit 8: Device Port Change Notification Interrupt Flag Register bit
261 uint16_t CNFx9:1; // Bit 9: Device Port Change Notification Interrupt Flag Register bit
262 uint16_t CNFx10:1; // Bit 10: Device Port Change Notification Interrupt Flag Register bit
263 uint16_t CNFx11:1; // Bit 11: Device Port Change Notification Interrupt Flag Register bit
264 uint16_t CNFx12:1; // Bit 12: Device Port Change Notification Interrupt Flag Register bit
265 uint16_t CNFx13:1; // Bit 13: Device Port Change Notification Interrupt Flag Register bit
266 uint16_t CNFx14:1; // Bit 14: Device Port Change Notification Interrupt Flag Register bit
267 uint16_t CNFx15:1; // Bit 15: Device Port Change Notification Interrupt Flag Register bit
268 }__attribute__((packed)); // CNFx: CHANGE NOTIFICATION INTERRUPT FLAG FOR PORTx REGISTER
269 typedef struct CNFx_s CNCFx_t; // CNFx: CHANGE NOTIFICATION INTERRUPT FLAG FOR PORTx REGISTER DATA TYPE
270
271 struct P33C_GPIO_INSTANCE_s {
272 union {
273 volatile struct ANSELx_s bits; // Register bit-field
274 volatile uint16_t value; // 16-bit wide register value
275 }ANSELx; // ANSELx: ANALOG SELECT FOR PORTx REGISTER
276 union {
277 volatile struct TRISx_s bits; // Register bit-field
278 volatile uint16_t value; // 16-bit wide register value
279 }TRISx; // TRISx: OUTPUT ENABLE FOR PORTx REGISTER
280 union {
281 volatile struct PORTx_s bits; // Register bit-field
282 volatile uint16_t value; // 16-bit wide register value
283 }PORTx; // PORTx: INPUT DATA FOR PORTx REGISTER
284 union {
285 volatile struct LATx_s bits; // Register bit-field
286 volatile uint16_t value; // 16-bit wide register value
287 }LATx; // LATx: OUTPUT DATA FOR PORTx REGISTER
288 union {
289 volatile struct ODCx_s bits; // Register bit-field
290 volatile uint16_t value; // 16-bit wide register value
291 }ODCx; // ODCx: OPEN-DRAIN ENABLE FOR PORTx REGISTER
292 union {
293 volatile struct CNPUx_s bits; // Register bit-field
294 volatile uint16_t value; // 16-bit wide register value
295 }CNPUx; // CNPUx: CHANGE NOTIFICATION PULL-UP ENABLE FOR PORTx REGISTER
296 union {
297 volatile struct CNPDx_s bits; // Register bit-field
298 volatile uint16_t value; // 16-bit wide register value
299 }CNPDx; // CNPDx: CHANGE NOTIFICATION PULL-DOWN ENABLE FOR PORTx REGISTER
300 union {
301 volatile struct tagCNCONABITS bits; // Register bit-field
302 volatile uint16_t value; // 16-bit wide register value
303 }CNCONx; // CNCONx: CHANGE NOTIFICATION CONTROL FOR PORTx REGISTER
304 union {
305 volatile struct CNEN0x_s bits; // Register bit-field
306 volatile uint16_t value; // 16-bit wide register value
307 }CNEN0x; // CNEN0x: CHANGE NOTIFICATION INTERRUPT ENABLE FOR PORTx REGISTER
308 union {
309 volatile struct CNSTATx_s bits; // Register bit-field
310 volatile uint16_t value; // 16-bit wide register value
311 }CNSTATx; // CNSTATx: CHANGE NOTIFICATION STATUS FOR PORTx REGISTER
312 union {
313 volatile struct CNEN1x_s bits; // Register bit-field
314 volatile uint16_t value; // 16-bit wide register value
315 }CNEN1x; // CNEN1x: CHANGE NOTIFICATION EDGE SELECT FOR PORTx REGISTER
316 union {
317 volatile struct CNFx_s bits; // Register bit-field
318 volatile uint16_t value; // 16-bit wide register value
319 }CNFx; // CNFx: CHANGE NOTIFICATION INTERRUPT FLAG FOR PORTx REGISTER
320 } __attribute__((packed)); // GPIO REGISTER SET
321 typedef struct P33C_GPIO_INSTANCE_s P33C_GPIO_INSTANCE_t;
322
323 #define P33C_GPIO_SFR_OFFSET ((volatile uint16_t)&ANSELB - (volatile uint16_t)&ANSELA)
324
325 #if defined (TRISE)
326 #define P33C_PORT_COUNT 5
327
328 #elif defined (TRISD)
329 #define P33C_PORT_COUNT 4
330
331 #elif defined (TRISC)
332 #define P33C_PORT_COUNT 3
333
334 #elif defined (TRISB)
335 #define P33C_PORT_COUNT 2
336
337 #elif defined (TRISA)
338 #define P33C_PORT_COUNT 1
339
340 #endif
341
342 /*********************************************************************************
343 * @fn struct P33C_GPIO_INSTANCE_s* p33c_GpioInstance_GetHandle(volatile uint16_t gpioInstance)
344 * @ingroup lib-layer-pral-functions-public-gpio
345 * @brief Gets pointer to GPIO Instance SFR set
346 * @param gpioInstance Index of the selected GPIO Instance (1=Port A, 2=Port B, etc.)
347 * @return Pointer to GPIO instance object of type struct P33C_GPIO_INSTANCE_s of the selected GPIO instance
348 *
349 * @details
350 * This function returns the pointer to a GPIO instance register set in
351 * Special Function Register memory space. This pointer can be used to directly
352 * write to/read from the Special Function Registers of a given peripheral
353 * instance.
354 *
355 *********************************************************************************/
356
357 extern volatile uint16_t* p33c_GpioInstance_Handles[];
358 #define p33c_GpioInstance_GetHandle(x) (struct P33C_GPIO_INSTANCE_s*)p33c_GpioInstance_Handles[(x)]
359
360 #endif
361
362 /* ********************************************************************************************* *
363 * DEVICE PIN DECLARATIONS FOR INDIRECT PORT PIN ADDRESSING
364 * ********************************************************************************************* */
365
366 struct GPIO_PORT_PIN_s {
367 volatile uint16_t port; // Integer index of device port
368 volatile uint16_t pin; // integer index of device pin within port group
369 volatile uint16_t rpid; // Remappable Pin ID
370 }; // generic device port ID structure
371 typedef struct GPIO_PORT_PIN_s GPIO_PORT_PIN_t; // Generic device port ID structure data type
372
373 // Device Pin Declarations
374
375 // Port A
376 #if defined (_TRISA0)
377 extern volatile struct GPIO_PORT_PIN_s PIN_RA0;
378 #define PIN_RA0 PIN_RA0
379 #endif
380 #if defined (_TRISA1)
381 extern volatile struct GPIO_PORT_PIN_s PIN_RA1;
382 #define PIN_RA1 PIN_RA1
383 #endif
384 #if defined (_TRISA2)
385 extern volatile struct GPIO_PORT_PIN_s PIN_RA2;
386 #define PIN_RA2 PIN_RA2
387 #endif
388 #if defined (_TRISA3)
389 extern volatile struct GPIO_PORT_PIN_s PIN_RA3;
390 #define PIN_RA3 PIN_RA3
391 #endif
392 #if defined (_TRISA4)
393 extern volatile struct GPIO_PORT_PIN_s PIN_RA4;
394 #define PIN_RA4 PIN_RA4
395 #endif
396
397
398 // Port B
399 #if defined (_TRISB0)
400 extern volatile struct GPIO_PORT_PIN_s PIN_RB0;
401 #define PIN_RB0 PIN_RB0
402 #endif
403 #if defined (_TRISB1)
404 extern volatile struct GPIO_PORT_PIN_s PIN_RB1;
405 #define PIN_RB1 PIN_RB1
406 #endif
407 #if defined (_TRISB2)
408 extern volatile struct GPIO_PORT_PIN_s PIN_RB2;
409 #define PIN_RB2 PIN_RB2
410 #endif
411 #if defined (_TRISB3)
412 extern volatile struct GPIO_PORT_PIN_s PIN_RB3;
413 #define PIN_RB3 PIN_RB3
414 #endif
415 #if defined (_TRISB4)
416 extern volatile struct GPIO_PORT_PIN_s PIN_RB4;
417 #define PIN_RB4 PIN_RB4
418 #endif
419 #if defined (_TRISB5)
420 extern volatile struct GPIO_PORT_PIN_s PIN_RB5;
421 #define PIN_RB5 PIN_RB5
422 #endif
423 #if defined (_TRISB6)
424 extern volatile struct GPIO_PORT_PIN_s PIN_RB6;
425 #define PIN_RB6 PIN_RB6
426 #endif
427 #if defined (_TRISB7)
428 extern volatile struct GPIO_PORT_PIN_s PIN_RB7;
429 #define PIN_RB7 PIN_RB7
430 #endif
431 #if defined (_TRISB8)
432 extern volatile struct GPIO_PORT_PIN_s PIN_RB8;
433 #define PIN_RB8 PIN_RB8
434 #endif
435 #if defined (_TRISB9)
436 extern volatile struct GPIO_PORT_PIN_s PIN_RB9;
437 #define PIN_RB9 PIN_RB9
438 #endif
439 #if defined (_TRISB10)
440 extern volatile struct GPIO_PORT_PIN_s PIN_RB10;
441 #define PIN_RB10 PIN_RB10
442 #endif
443 #if defined (_TRISB11)
444 extern volatile struct GPIO_PORT_PIN_s PIN_RB11;
445 #define PIN_RB11 PIN_RB11
446 #endif
447 #if defined (_TRISB12)
448 extern volatile struct GPIO_PORT_PIN_s PIN_RB12;
449 #define PIN_RB12 PIN_RB12
450 #endif
451 #if defined (_TRISB13)
452 extern volatile struct GPIO_PORT_PIN_s PIN_RB13;
453 #define PIN_RB13 PIN_RB13
454 #endif
455 #if defined (_TRISB14)
456 extern volatile struct GPIO_PORT_PIN_s PIN_RB14;
457 #define PIN_RB14 PIN_RB14
458 #endif
459 #if defined (_TRISB15)
460 extern volatile struct GPIO_PORT_PIN_s PIN_RB15;
461 #define PIN_RB15 PIN_RB15
462 #endif
463
464 // Port C
465 #if defined (_TRISC0)
466 extern volatile struct GPIO_PORT_PIN_s PIN_RC0;
467 #define PIN_RC0 PIN_RC0
468 #endif
469 #if defined (_TRISC1)
470 extern volatile struct GPIO_PORT_PIN_s PIN_RC1;
471 #define PIN_RC1 PIN_RC1
472 #endif
473 #if defined (_TRISC2)
474 extern volatile struct GPIO_PORT_PIN_s PIN_RC2;
475 #define PIN_RC2 PIN_RC2
476 #endif
477 #if defined (_TRISC3)
478 extern volatile struct GPIO_PORT_PIN_s PIN_RC3;
479 #define PIN_RC3 PIN_RC3
480 #endif
481 #if defined (_TRISC4)
482 extern volatile struct GPIO_PORT_PIN_s PIN_RC4;
483 #define PIN_RC4 PIN_RC4
484 #endif
485 #if defined (_TRISC5)
486 extern volatile struct GPIO_PORT_PIN_s PIN_RC5;
487 #define PIN_RC5 PIN_RC5
488 #endif
489 #if defined (_TRISC6)
490 extern volatile struct GPIO_PORT_PIN_s PIN_RC6;
491 #define PIN_RC6 PIN_RC6
492 #endif
493 #if defined (_TRISC7)
494 extern volatile struct GPIO_PORT_PIN_s PIN_RC7;
495 #define PIN_RC7 PIN_RC7
496 #endif
497 #if defined (_TRISC8)
498 extern volatile struct GPIO_PORT_PIN_s PIN_RC8;
499 #define PIN_RC8 PIN_RC8
500 #endif
501 #if defined (_TRISC9)
502 extern volatile struct GPIO_PORT_PIN_s PIN_RC9;
503 #define PIN_RC9 PIN_RC9
504 #endif
505 #if defined (_TRISC10)
506 extern volatile struct GPIO_PORT_PIN_s PIN_RC10;
507 #define PIN_RC10 PIN_RC10
508 #endif
509 #if defined (_TRISC11)
510 extern volatile struct GPIO_PORT_PIN_s PIN_RC11;
511 #define PIN_RC11 PIN_RC11
512 #endif
513 #if defined (_TRISC12)
514 extern volatile struct GPIO_PORT_PIN_s PIN_RC12;
515 #define PIN_RC12 PIN_RC12
516 #endif
517 #if defined (_TRISC13)
518 extern volatile struct GPIO_PORT_PIN_s PIN_RC13;
519 #define PIN_RC13 PIN_RC13
520 #endif
521 #if defined (_TRISC14)
522 extern volatile struct GPIO_PORT_PIN_s PIN_RC14;
523 #define PIN_RC14 PIN_RC14
524 #endif
525 #if defined (_TRISC15)
526 extern volatile struct GPIO_PORT_PIN_s PIN_RC15;
527 #define PIN_RC15 PIN_RC15
528 #endif
529
530 // Port D
531 #if defined (_TRISD0)
532 extern volatile struct GPIO_PORT_PIN_s PIN_RD0;
533 #define PIN_RD0 PIN_RD0
534 #endif
535 #if defined (_TRISD1)
536 extern volatile struct GPIO_PORT_PIN_s PIN_RD1;
537 #define PIN_RD1 PIN_RD1
538 #endif
539 #if defined (_TRISD2)
540 extern volatile struct GPIO_PORT_PIN_s PIN_RD2;
541 #define PIN_RD2 PIN_RD2
542 #endif
543 #if defined (_TRISD3)
544 extern volatile struct GPIO_PORT_PIN_s PIN_RD3;
545 #define PIN_RD3 PIN_RD3
546 #endif
547 #if defined (_TRISD4)
548 extern volatile struct GPIO_PORT_PIN_s PIN_RD4;
549 #define PIN_RD4 PIN_RD4
550 #endif
551 #if defined (_TRISD5)
552 extern volatile struct GPIO_PORT_PIN_s PIN_RD5;
553 #define PIN_RD5 PIN_RD5
554 #endif
555 #if defined (_TRISD6)
556 extern volatile struct GPIO_PORT_PIN_s PIN_RD6;
557 #define PIN_RD6 PIN_RD6
558 #endif
559 #if defined (_TRISD7)
560 extern volatile struct GPIO_PORT_PIN_s PIN_RD7;
561 #define PIN_RD7 PIN_RD7
562 #endif
563 #if defined (_TRISD8)
564 extern volatile struct GPIO_PORT_PIN_s PIN_RD8;
565 #define PIN_RD8 PIN_RD8
566 #endif
567 #if defined (_TRISD9)
568 extern volatile struct GPIO_PORT_PIN_s PIN_RD9;
569 #define PIN_RD9 PIN_RD9
570 #endif
571 #if defined (_TRISD10)
572 extern volatile struct GPIO_PORT_PIN_s PIN_RD10;
573 #define PIN_RD10 PIN_RD10
574 #endif
575 #if defined (_TRISD11)
576 extern volatile struct GPIO_PORT_PIN_s PIN_RD11;
577 #define PIN_RD11 PIN_RD11
578 #endif
579 #if defined (_TRISD12)
580 extern volatile struct GPIO_PORT_PIN_s PIN_RD12;
581 #define PIN_RD12 PIN_RD12
582 #endif
583 #if defined (_TRISD13)
584 extern volatile struct GPIO_PORT_PIN_s PIN_RD13;
585 #define PIN_RD13 PIN_RD13
586 #endif
587 #if defined (_TRISD14)
588 extern volatile struct GPIO_PORT_PIN_s PIN_RD14;
589 #define PIN_RD14 PIN_RD14
590 #endif
591 #if defined (_TRISD15)
592 extern volatile struct GPIO_PORT_PIN_s PIN_RD15;
593 #define PIN_RD15 PIN_RD15
594 #endif
595
596 // Port E
597 #if defined (_TRISE0)
598 extern volatile struct GPIO_PORT_PIN_s PIN_RE0;
599 #define PIN_RE0 PIN_RE0
600 #endif
601 #if defined (_TRISE1)
602 extern volatile struct GPIO_PORT_PIN_s PIN_RE1;
603 #define PIN_RE1 PIN_RE1
604 #endif
605 #if defined (_TRISE2)
606 extern volatile struct GPIO_PORT_PIN_s PIN_RE2;
607 #define PIN_RE2 PIN_RE2
608 #endif
609 #if defined (_TRISE3)
610 extern volatile struct GPIO_PORT_PIN_s PIN_RE3;
611 #define PIN_RE3 PIN_RE3
612 #endif
613 #if defined (_TRISE4)
614 extern volatile struct GPIO_PORT_PIN_s PIN_RE4;
615 #define PIN_RE4 PIN_RE4
616 #endif
617 #if defined (_TRISE5)
618 extern volatile struct GPIO_PORT_PIN_s PIN_RE5;
619 #define PIN_RE5 PIN_RE5
620 #endif
621 #if defined (_TRISE6)
622 extern volatile struct GPIO_PORT_PIN_s PIN_RE6;
623 #define PIN_RE6 PIN_RE6
624 #endif
625 #if defined (_TRISE7)
626 extern volatile struct GPIO_PORT_PIN_s PIN_RE7;
627 #define PIN_RE7 PIN_RE7
628 #endif
629 #if defined (_TRISE8)
630 extern volatile struct GPIO_PORT_PIN_s PIN_RE8;
631 #define PIN_RE8 PIN_RE8
632 #endif
633 #if defined (_TRISE9)
634 extern volatile struct GPIO_PORT_PIN_s PIN_RE9;
635 #define PIN_RE9 PIN_RE9
636 #endif
637 #if defined (_TRISE10)
638 extern volatile struct GPIO_PORT_PIN_s PIN_RE10;
639 #define PIN_RE10 PIN_RE10
640 #endif
641 #if defined (_TRISE11)
642 extern volatile struct GPIO_PORT_PIN_s PIN_RE11;
643 #define PIN_RE11 PIN_RE11
644 #endif
645 #if defined (_TRISE12)
646 extern volatile struct GPIO_PORT_PIN_s PIN_RE12;
647 #define PIN_RE12 PIN_RE12
648 #endif
649 #if defined (_TRISE13)
650 extern volatile struct GPIO_PORT_PIN_s PIN_RE13;
651 #define PIN_RE13 PIN_RE13
652 #endif
653 #if defined (_TRISE14)
654 extern volatile struct GPIO_PORT_PIN_s PIN_RE14;
655 #define PIN_RE14 PIN_RE14
656 #endif
657 #if defined (_TRISE15)
658 extern volatile struct GPIO_PORT_PIN_s PIN_RE15;
659 #define PIN_RE15 PIN_RE15
660 #endif
661
662 /* ********************************************************************************************* *
663 * API FUNCTION PROTOTYPES
664 * ********************************************************************************************* */
665
666 extern volatile uint16_t p33c_GpioInstance_Dispose(
667 volatile uint16_t gpioInstance
668 );
669
670 extern volatile struct P33C_GPIO_INSTANCE_s p33c_GpioInstance_ConfigRead(
671 volatile uint16_t gpioInstance
672 );
673
674 extern volatile uint16_t p33c_GpioInstance_ConfigWrite(
675 volatile uint16_t gpioInstance,
676 volatile struct P33C_GPIO_INSTANCE_s gpioConfig
677 );
678
679 /* ********************************************************************************************* *
680 * GPIO INSTANCE CONFIGURATION TEMPLATES
681 * ********************************************************************************************* */
682 extern volatile struct P33C_GPIO_INSTANCE_s gpioConfigClear;
683
684 #endif /* P33C_GPIO_SFR_ABSTRACTION_H */
685
P33C_GPIO_INSTANCE_s::LATx
union P33C_GPIO_INSTANCE_s::@126 LATx
CNPDx_s::CNPDx6
uint16_t CNPDx6
Definition: p33c_gpio.h:178
CNSTATx_s::CNSTATx14
uint16_t CNSTATx14
Definition: p33c_gpio.h:226
CNSTATx_s::CNSTATx3
uint16_t CNSTATx3
Definition: p33c_gpio.h:215
ANSELx_s::ANSELx0
uint16_t ANSELx0
Definition: p33c_gpio.h:52
CNSTATx_s::CNSTATx2
uint16_t CNSTATx2
Definition: p33c_gpio.h:214
LATx_s::LATx15
uint16_t LATx15
Definition: p33c_gpio.h:127
TRISx_s::TRISx10
uint16_t TRISx10
Definition: p33c_gpio.h:82
PORTx_s::PORTx12
uint16_t PORTx12
Definition: p33c_gpio.h:104
P33C_GPIO_INSTANCE_s::value
volatile uint16_t value
Definition: p33c_gpio.h:274
PORTx_s::PORTx4
uint16_t PORTx4
Definition: p33c_gpio.h:96
P33C_GPIO_INSTANCE_s::CNEN0x
union P33C_GPIO_INSTANCE_s::@131 CNEN0x
ANSELx_s::ANSELx9
uint16_t ANSELx9
Definition: p33c_gpio.h:61
ANSELx_s::ANSELx13
uint16_t ANSELx13
Definition: p33c_gpio.h:65
TRISx_s::TRISx4
uint16_t TRISx4
Definition: p33c_gpio.h:76
P33C_GPIO_INSTANCE_s::TRISx
union P33C_GPIO_INSTANCE_s::@124 TRISx
ANSELx_s::ANSELx7
uint16_t ANSELx7
Definition: p33c_gpio.h:59
PORTx_s::PORTx14
uint16_t PORTx14
Definition: p33c_gpio.h:106
GPIO_PORT_PIN_s::port
volatile uint16_t port
Definition: p33c_gpio.h:367
LATx_s
Definition: p33c_gpio.h:111
PORTx_s::PORTx0
uint16_t PORTx0
Definition: p33c_gpio.h:92
CNEN0x_s::CNEN0x6
uint16_t CNEN0x6
Definition: p33c_gpio.h:198
ODCx_s::ODCx13
uint16_t ODCx13
Definition: p33c_gpio.h:145
TRISx_s::TRISx0
uint16_t TRISx0
Definition: p33c_gpio.h:72
LATx_s::LATx12
uint16_t LATx12
Definition: p33c_gpio.h:124
ANSELx_s
Definition: p33c_gpio.h:51
LATx_s::LATx9
uint16_t LATx9
Definition: p33c_gpio.h:121
CNSTATx_s::CNSTATx11
uint16_t CNSTATx11
Definition: p33c_gpio.h:223
CNPDx_s::CNPDx13
uint16_t CNPDx13
Definition: p33c_gpio.h:185
CNFx_s::CNFx10
uint16_t CNFx10
Definition: p33c_gpio.h:262
P33C_GPIO_INSTANCE_s::CNCONx
union P33C_GPIO_INSTANCE_s::@130 CNCONx
TRISx_s::TRISx11
uint16_t TRISx11
Definition: p33c_gpio.h:83
CNFx_s::CNFx12
uint16_t CNFx12
Definition: p33c_gpio.h:264
CNEN1x_s::CNEN1x1
uint16_t CNEN1x1
Definition: p33c_gpio.h:233
CNSTATx_s::CNSTATx8
uint16_t CNSTATx8
Definition: p33c_gpio.h:220
CNPDx_s::CNPDx12
uint16_t CNPDx12
Definition: p33c_gpio.h:184
CNPDx_s::CNPDx11
uint16_t CNPDx11
Definition: p33c_gpio.h:183
CNFx_s::CNFx3
uint16_t CNFx3
Definition: p33c_gpio.h:255
CNEN1x_s::CNEN1x0
uint16_t CNEN1x0
Definition: p33c_gpio.h:232
P33C_GPIO_INSTANCE_s::bits
volatile struct ANSELx_s bits
Definition: p33c_gpio.h:273
CNEN0x_s::CNEN0x0
uint16_t CNEN0x0
Definition: p33c_gpio.h:192
ODCx_s::ODCx2
uint16_t ODCx2
Definition: p33c_gpio.h:134
CNEN1x_s::CNEN1x10
uint16_t CNEN1x10
Definition: p33c_gpio.h:242
CNPUx_s::CNPUx2
uint16_t CNPUx2
Definition: p33c_gpio.h:154
CNPDx_s::CNPDx15
uint16_t CNPDx15
Definition: p33c_gpio.h:187
ANSELx_s::ANSELx5
uint16_t ANSELx5
Definition: p33c_gpio.h:57
CNFx_s::CNFx6
uint16_t CNFx6
Definition: p33c_gpio.h:258
PORTx_s
Definition: p33c_gpio.h:91
CNFx_s::CNFx7
uint16_t CNFx7
Definition: p33c_gpio.h:259
CNSTATx_s::CNSTATx15
uint16_t CNSTATx15
Definition: p33c_gpio.h:227
PORTx_s::PORTx15
uint16_t PORTx15
Definition: p33c_gpio.h:107
CNEN1x_s::CNEN1x5
uint16_t CNEN1x5
Definition: p33c_gpio.h:237
CNEN1x_s::CNEN1x4
uint16_t CNEN1x4
Definition: p33c_gpio.h:236
ODCx_s::ODCx0
uint16_t ODCx0
Definition: p33c_gpio.h:132
CNFx_s::CNFx13
uint16_t CNFx13
Definition: p33c_gpio.h:265
CNSTATx_s::CNSTATx6
uint16_t CNSTATx6
Definition: p33c_gpio.h:218
ODCx_s
Definition: p33c_gpio.h:131
ODCx_s::ODCx1
uint16_t ODCx1
Definition: p33c_gpio.h:133
CNPUx_s::CNPUx15
uint16_t CNPUx15
Definition: p33c_gpio.h:167
CNPUx_s::CNPUx10
uint16_t CNPUx10
Definition: p33c_gpio.h:162
CNEN0x_s::CNEN0x5
uint16_t CNEN0x5
Definition: p33c_gpio.h:197
GPIO_PORT_PIN_s::pin
volatile uint16_t pin
Definition: p33c_gpio.h:368
CNFx_s::CNFx8
uint16_t CNFx8
Definition: p33c_gpio.h:260
CNFx_s::CNFx9
uint16_t CNFx9
Definition: p33c_gpio.h:261
TRISx_s::TRISx13
uint16_t TRISx13
Definition: p33c_gpio.h:85
CNEN0x_s::CNEN0x8
uint16_t CNEN0x8
Definition: p33c_gpio.h:200
CNPUx_s::CNPUx1
uint16_t CNPUx1
Definition: p33c_gpio.h:153
LATx_s::LATx1
uint16_t LATx1
Definition: p33c_gpio.h:113
CNFx_s::CNFx5
uint16_t CNFx5
Definition: p33c_gpio.h:257
CNEN0x_s::CNEN0x13
uint16_t CNEN0x13
Definition: p33c_gpio.h:205
TRISx_s::TRISx5
uint16_t TRISx5
Definition: p33c_gpio.h:77
LATx_s::LATx5
uint16_t LATx5
Definition: p33c_gpio.h:117
LATx_s::LATx7
uint16_t LATx7
Definition: p33c_gpio.h:119
P33C_GPIO_INSTANCE_s::CNPDx
union P33C_GPIO_INSTANCE_s::@129 CNPDx
TRISx_s::TRISx8
uint16_t TRISx8
Definition: p33c_gpio.h:80
CNEN1x_s
Definition: p33c_gpio.h:231
P33C_GPIO_INSTANCE_s::ODCx
union P33C_GPIO_INSTANCE_s::@127 ODCx
P33C_GPIO_INSTANCE_s::ANSELx
union P33C_GPIO_INSTANCE_s::@123 ANSELx
CNPUx_s::CNPUx14
uint16_t CNPUx14
Definition: p33c_gpio.h:166
CNFx_s::CNFx2
uint16_t CNFx2
Definition: p33c_gpio.h:254
CNFx_s::CNFx15
uint16_t CNFx15
Definition: p33c_gpio.h:267
ANSELx_s::ANSELx3
uint16_t ANSELx3
Definition: p33c_gpio.h:55
TRISx_s::TRISx3
uint16_t TRISx3
Definition: p33c_gpio.h:75
CNEN0x_s::CNEN0x3
uint16_t CNEN0x3
Definition: p33c_gpio.h:195
CNEN1x_s::CNEN1x3
uint16_t CNEN1x3
Definition: p33c_gpio.h:235
TRISx_s::TRISx2
uint16_t TRISx2
Definition: p33c_gpio.h:74
GPIO_PORT_PIN_s::rpid
volatile uint16_t rpid
Definition: p33c_gpio.h:369
ODCx_s::ODCx9
uint16_t ODCx9
Definition: p33c_gpio.h:141
ANSELx_s::ANSELx1
uint16_t ANSELx1
Definition: p33c_gpio.h:53
ANSELx_s::ANSELx2
uint16_t ANSELx2
Definition: p33c_gpio.h:54
CNEN1x_s::CNEN1x9
uint16_t CNEN1x9
Definition: p33c_gpio.h:241
CNSTATx_s::CNSTATx4
uint16_t CNSTATx4
Definition: p33c_gpio.h:216
TRISx_s::TRISx9
uint16_t TRISx9
Definition: p33c_gpio.h:81
CNPDx_s::CNPDx14
uint16_t CNPDx14
Definition: p33c_gpio.h:186
P33C_GPIO_INSTANCE_s::CNSTATx
union P33C_GPIO_INSTANCE_s::@132 CNSTATx
CNFx_s::CNFx4
uint16_t CNFx4
Definition: p33c_gpio.h:256
CNSTATx_s::CNSTATx7
uint16_t CNSTATx7
Definition: p33c_gpio.h:219
TRISx_s::TRISx14
uint16_t TRISx14
Definition: p33c_gpio.h:86
CNEN1x_s::CNEN1x13
uint16_t CNEN1x13
Definition: p33c_gpio.h:245
ANSELx_s::ANSELx12
uint16_t ANSELx12
Definition: p33c_gpio.h:64
PORTx_s::PORTx11
uint16_t PORTx11
Definition: p33c_gpio.h:103
LATx_s::LATx4
uint16_t LATx4
Definition: p33c_gpio.h:116
ODCx_s::ODCx3
uint16_t ODCx3
Definition: p33c_gpio.h:135
CNPUx_s::CNPUx7
uint16_t CNPUx7
Definition: p33c_gpio.h:159
PORTx_s::PORTx9
uint16_t PORTx9
Definition: p33c_gpio.h:101
ODCx_s::ODCx5
uint16_t ODCx5
Definition: p33c_gpio.h:137
CNPDx_s::CNPDx7
uint16_t CNPDx7
Definition: p33c_gpio.h:179
CNEN0x_s::CNEN0x9
uint16_t CNEN0x9
Definition: p33c_gpio.h:201
ODCx_s::ODCx15
uint16_t ODCx15
Definition: p33c_gpio.h:147
LATx_s::LATx0
uint16_t LATx0
Definition: p33c_gpio.h:112
CNPUx_s::CNPUx6
uint16_t CNPUx6
Definition: p33c_gpio.h:158
PORTx_s::PORTx7
uint16_t PORTx7
Definition: p33c_gpio.h:99
CNPDx_s
Definition: p33c_gpio.h:171
CNSTATx_s::CNSTATx10
uint16_t CNSTATx10
Definition: p33c_gpio.h:222
LATx_s::LATx6
uint16_t LATx6
Definition: p33c_gpio.h:118
CNEN1x_s::CNEN1x2
uint16_t CNEN1x2
Definition: p33c_gpio.h:234
CNFx_s::CNFx14
uint16_t CNFx14
Definition: p33c_gpio.h:266
PORTx_s::PORTx2
uint16_t PORTx2
Definition: p33c_gpio.h:94
CNPUx_s::CNPUx8
uint16_t CNPUx8
Definition: p33c_gpio.h:160
PORTx_s::PORTx3
uint16_t PORTx3
Definition: p33c_gpio.h:95
ANSELx_s::ANSELx11
uint16_t ANSELx11
Definition: p33c_gpio.h:63
PORTx_s::PORTx6
uint16_t PORTx6
Definition: p33c_gpio.h:98
CNPUx_s::CNPUx5
uint16_t CNPUx5
Definition: p33c_gpio.h:157
CNPDx_s::CNPDx3
uint16_t CNPDx3
Definition: p33c_gpio.h:175
CNSTATx_s::CNSTATx1
uint16_t CNSTATx1
Definition: p33c_gpio.h:213
TRISx_s::TRISx7
uint16_t TRISx7
Definition: p33c_gpio.h:79
ANSELx_s::ANSELx15
uint16_t ANSELx15
Definition: p33c_gpio.h:67
GPIO_PORT_PIN_s
Definition: p33c_gpio.h:366
P33C_GPIO_INSTANCE_s
Definition: p33c_gpio.h:271
LATx_s::LATx14
uint16_t LATx14
Definition: p33c_gpio.h:126
CNEN0x_s::CNEN0x12
uint16_t CNEN0x12
Definition: p33c_gpio.h:204
CNPDx_s::CNPDx2
uint16_t CNPDx2
Definition: p33c_gpio.h:174
CNSTATx_s
Definition: p33c_gpio.h:211
CNPUx_s::CNPUx13
uint16_t CNPUx13
Definition: p33c_gpio.h:165
CNEN0x_s::CNEN0x7
uint16_t CNEN0x7
Definition: p33c_gpio.h:199
TRISx_s::TRISx15
uint16_t TRISx15
Definition: p33c_gpio.h:87
CNSTATx_s::CNSTATx0
uint16_t CNSTATx0
Definition: p33c_gpio.h:212
CNPUx_s
Definition: p33c_gpio.h:151
ODCx_s::ODCx4
uint16_t ODCx4
Definition: p33c_gpio.h:136
CNPUx_s::CNPUx11
uint16_t CNPUx11
Definition: p33c_gpio.h:163
ANSELx_s::ANSELx4
uint16_t ANSELx4
Definition: p33c_gpio.h:56
ODCx_s::ODCx11
uint16_t ODCx11
Definition: p33c_gpio.h:143
CNPDx_s::CNPDx9
uint16_t CNPDx9
Definition: p33c_gpio.h:181
LATx_s::LATx11
uint16_t LATx11
Definition: p33c_gpio.h:123
ANSELx_s::ANSELx10
uint16_t ANSELx10
Definition: p33c_gpio.h:62
CNPUx_s::CNPUx3
uint16_t CNPUx3
Definition: p33c_gpio.h:155
ODCx_s::ODCx10
uint16_t ODCx10
Definition: p33c_gpio.h:142
CNEN1x_s::CNEN1x15
uint16_t CNEN1x15
Definition: p33c_gpio.h:247
TRISx_s::TRISx12
uint16_t TRISx12
Definition: p33c_gpio.h:84
ODCx_s::ODCx7
uint16_t ODCx7
Definition: p33c_gpio.h:139
CNSTATx_s::CNSTATx9
uint16_t CNSTATx9
Definition: p33c_gpio.h:221
CNEN0x_s::CNEN0x15
uint16_t CNEN0x15
Definition: p33c_gpio.h:207
CNEN0x_s::CNEN0x1
uint16_t CNEN0x1
Definition: p33c_gpio.h:193
LATx_s::LATx13
uint16_t LATx13
Definition: p33c_gpio.h:125
P33C_GPIO_INSTANCE_s::PORTx
union P33C_GPIO_INSTANCE_s::@125 PORTx
CNSTATx_s::CNSTATx12
uint16_t CNSTATx12
Definition: p33c_gpio.h:224
ODCx_s::ODCx6
uint16_t ODCx6
Definition: p33c_gpio.h:138
TRISx_s::TRISx6
uint16_t TRISx6
Definition: p33c_gpio.h:78
P33C_GPIO_INSTANCE_s::CNPUx
union P33C_GPIO_INSTANCE_s::@128 CNPUx
CNFx_s::CNFx11
uint16_t CNFx11
Definition: p33c_gpio.h:263
ODCx_s::ODCx8
uint16_t ODCx8
Definition: p33c_gpio.h:140
CNSTATx_s::CNSTATx13
uint16_t CNSTATx13
Definition: p33c_gpio.h:225
ANSELx_s::ANSELx14
uint16_t ANSELx14
Definition: p33c_gpio.h:66
LATx_s::LATx2
uint16_t LATx2
Definition: p33c_gpio.h:114
CNPDx_s::CNPDx10
uint16_t CNPDx10
Definition: p33c_gpio.h:182
ANSELx_s::ANSELx8
uint16_t ANSELx8
Definition: p33c_gpio.h:60
CNPDx_s::CNPDx0
uint16_t CNPDx0
Definition: p33c_gpio.h:172
CNEN1x_s::CNEN1x14
uint16_t CNEN1x14
Definition: p33c_gpio.h:246
CNEN1x_s::CNEN1x7
uint16_t CNEN1x7
Definition: p33c_gpio.h:239
CNFx_s
Definition: p33c_gpio.h:251
P33C_GPIO_INSTANCE_s::CNEN1x
union P33C_GPIO_INSTANCE_s::@133 CNEN1x
PORTx_s::PORTx8
uint16_t PORTx8
Definition: p33c_gpio.h:100
CNEN0x_s::CNEN0x11
uint16_t CNEN0x11
Definition: p33c_gpio.h:203
CNPUx_s::CNPUx12
uint16_t CNPUx12
Definition: p33c_gpio.h:164
CNEN0x_s
Definition: p33c_gpio.h:191
CNEN0x_s::CNEN0x14
uint16_t CNEN0x14
Definition: p33c_gpio.h:206
CNSTATx_s::CNSTATx5
uint16_t CNSTATx5
Definition: p33c_gpio.h:217
CNFx_s::CNFx0
uint16_t CNFx0
Definition: p33c_gpio.h:252
CNEN1x_s::CNEN1x6
uint16_t CNEN1x6
Definition: p33c_gpio.h:238
PORTx_s::PORTx1
uint16_t PORTx1
Definition: p33c_gpio.h:93
CNPUx_s::CNPUx9
uint16_t CNPUx9
Definition: p33c_gpio.h:161
CNPDx_s::CNPDx5
uint16_t CNPDx5
Definition: p33c_gpio.h:177
PORTx_s::PORTx5
uint16_t PORTx5
Definition: p33c_gpio.h:97
CNEN1x_s::CNEN1x12
uint16_t CNEN1x12
Definition: p33c_gpio.h:244
PORTx_s::PORTx13
uint16_t PORTx13
Definition: p33c_gpio.h:105
CNEN0x_s::CNEN0x2
uint16_t CNEN0x2
Definition: p33c_gpio.h:194
CNPDx_s::CNPDx4
uint16_t CNPDx4
Definition: p33c_gpio.h:176
CNEN0x_s::CNEN0x4
uint16_t CNEN0x4
Definition: p33c_gpio.h:196
ODCx_s::ODCx12
uint16_t ODCx12
Definition: p33c_gpio.h:144
ANSELx_s::ANSELx6
uint16_t ANSELx6
Definition: p33c_gpio.h:58
ODCx_s::ODCx14
uint16_t ODCx14
Definition: p33c_gpio.h:146
CNEN1x_s::CNEN1x8
uint16_t CNEN1x8
Definition: p33c_gpio.h:240
CNPUx_s::CNPUx4
uint16_t CNPUx4
Definition: p33c_gpio.h:156
LATx_s::LATx10
uint16_t LATx10
Definition: p33c_gpio.h:122
PORTx_s::PORTx10
uint16_t PORTx10
Definition: p33c_gpio.h:102
CNEN0x_s::CNEN0x10
uint16_t CNEN0x10
Definition: p33c_gpio.h:202
CNPDx_s::CNPDx8
uint16_t CNPDx8
Definition: p33c_gpio.h:180
CNFx_s::CNFx1
uint16_t CNFx1
Definition: p33c_gpio.h:253
LATx_s::LATx3
uint16_t LATx3
Definition: p33c_gpio.h:115
LATx_s::LATx8
uint16_t LATx8
Definition: p33c_gpio.h:120
TRISx_s
Definition: p33c_gpio.h:71
CNEN1x_s::CNEN1x11
uint16_t CNEN1x11
Definition: p33c_gpio.h:243
CNPUx_s::CNPUx0
uint16_t CNPUx0
Definition: p33c_gpio.h:152
TRISx_s::TRISx1
uint16_t TRISx1
Definition: p33c_gpio.h:73
CNPDx_s::CNPDx1
uint16_t CNPDx1
Definition: p33c_gpio.h:173
P33C_GPIO_INSTANCE_s::CNFx
union P33C_GPIO_INSTANCE_s::@134 CNFx