| Digital Power Starter Kit 3 Firmware dsPIC33C Boost Converter Voltage Mode Control Example |

p33c_osc.h
1 /*LICENSE ********************************************************************
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21 * ***************************************************************************/
22
23 /*****************************************************************************
24 *
25 * @file p33c_osc.h
26 * @author M91406
27 * @date October 27, 2017, 11:24 AM
28 *
29 * History:
30 * 10/27/17 initial release
31 * 07/07/18 separation of FJ, EP and CH/CK device families
32 *
33 * Know limitations in this release:
34 * - REFCLK is not supported
35 * ***************************************************************************/
36
37 #ifndef MCAL_P33SMPS_OSCILLATOR_H
38 #define MCAL_P33SMPS_OSCILLATOR_H
39
40 #include <xc.h> // include processor files - each processor file is guarded.
41 #include <stdint.h> // include standard integer types header file
42 #include <stdbool.h> // include standard boolean types header file
43
44 #include "p33smps_devices.h" // DEVICES header to derive device-dependent properties
45
46 /**************************************************************************************************
47 * System Frequencies
48 * Summary:
49 * Set of defines, data types and data structures for system frequency adaption
50 *
51 * Description:
52 * This library offers default preset for CPU frequencies to simplify the oscillator
53 * configuration for standard applications using the internal Fast RC oscillator (FRC).
54 * These parameters are supposed to be used with the function call init_FRCCLK_Defaults().
55 * To change the CPU frequency at any point during runtime, clock switching must be enabled
56 * by setting the configuration bit FCKSM:
57 *
58 * #pragma config FCKSM = CSECMD (Clock Switching Enabled/Clock Monitor Disabled)
59 * or CSECME (Clock Switching Enabled/Clock Monitor Enabled)
60 *
61 * Example:
62 * The following code line configures the internal FRC oscillator for 80 MIPS operation:
63 *
64 * init_FRCCLK_Defaults(CPU_SPEED_80_MIPS); // Configuring FRC for 80 MIPS operation
65 *
66 *************************************************************************************************/
67
68 enum CPU_SPEED_DEFAULTS_e {
69 CPU_SPEED_20_MIPS = 20, // CPU Speed setting for 20 MIPS operation
70 CPU_SPEED_30_MIPS = 30, // CPU Speed setting for 30 MIPS operation
71 CPU_SPEED_40_MIPS = 40, // CPU Speed setting for 40 MIPS operation
72 CPU_SPEED_50_MIPS = 50, // CPU Speed setting for 50 MIPS operation
73 CPU_SPEED_60_MIPS = 60, // CPU Speed setting for 60 MIPS operation
74 CPU_SPEED_70_MIPS = 70, // CPU Speed setting for 70 MIPS operation
75 CPU_SPEED_80_MIPS = 80, // CPU Speed setting for 80 MIPS operation
76 CPU_SPEED_90_MIPS = 90, // CPU Speed setting for 90 MIPS operation
77 CPU_SPEED_100_MIPS = 100 // CPU Speed setting for 100 MIPS operation
78 }; // Default CPU speed settings
79 typedef enum CPU_SPEED_DEFAULTS_e CPU_SPEED_DEFAULTS_t; // Default CPU speed settings data type
80
81
82 enum AUX_PLL_DEFAULTS_e {
83 AFPLLO_100_MHZ = 100, // Auxiliary PLL output frequency of 500 MHz
84 AFPLLO_200_MHZ = 200, // Auxiliary PLL output frequency of 500 MHz
85 AFPLLO_300_MHZ = 300, // Auxiliary PLL output frequency of 500 MHz
86 AFPLLO_400_MHZ = 400, // Auxiliary PLL output frequency of 500 MHz
87 AFPLLO_500_MHZ = 500, // Auxiliary PLL output frequency of 500 MHz (Default for high resolution PWM)
88 AFPLLO_600_MHZ = 600, // Auxiliary PLL output frequency of 600 MHz
89 AFPLLO_700_MHZ = 700, // Auxiliary PLL output frequency of 700 MHz
90 AFPLLO_800_MHZ = 800 // Auxiliary PLL output frequency of 800 MHz
91 }; // Default Auxiliary PLL output frequency settings
92 typedef enum AUX_PLL_DEFAULTS_e AUX_PLL_DEFAULTS_t; // Default Auxiliary PLL output frequency settings data type
93
94 /**************************************************************************************************
95 * @struct OSCILLATOR_SYSTEM_FREQUENCIES_s
96 * @brief Global data structure holding system frequencies of different clock domains
97 *
98 * @details
99 * The data structure "system_frequencies" of type OSCILLATOR_SYSTEM_FREQUENCIES_t is used
100 * to broadcast most recent system frequencies of multiple clock domains. Contents of this data
101 * structure are NOT updated automatically.
102 *
103 * The function p33c_Osc_GetFrequencies() must be called from user code to update/refresh the
104 * contents of this data structure every time a oscillator configuration has been changed.
105 *
106 * <p><b>Example:</b></p>
107 * The following code lines initialize the internal FRC oscillator for 100 MIPS operation and
108 * the auxiliary PLL for 500 MHz to support 250ps resolution of the PWM module. After both
109 * configurations have been set, the function 'osc_get_frequencies()' is used to update the
110 * most recent frequencies of multiple clock domains.
111 *
112 * @code{.c}
113 * init_FRCCLK_Defaults(CPU_SPEED_100_MIPS); // Initialize FRC for 100 MIPS operation
114 * init_AUXCLK_500MHz(); // Initialize AuxPLL for 500 MHz clock output
115 * osc_get_frequencies(0); // Update system frequencies data structure
116 * @endcode
117 *
118 * @note
119 * When an external oscillator is used, the function osc_get_frequencies() must be called
120 * to set the external frequency value in [Hz] and update all related frequencies accordingly.
121 * If only the internal FRC oscillator is used, this parameter should be set = 0.
122 * ***********************************************************************************************/
123
124 struct OSCILLATOR_SYSTEM_FREQUENCIES_s {
125 volatile uint32_t frc; // Internal fast RC oscillator frequency incl. tuning
126 volatile uint32_t fpri; // External primary oscillator frequency
127 volatile uint32_t fclk; // Clock frequency (currently active external or internal oscillator block input frequency)
128 volatile uint32_t fosc; // CPU Oscillator frequency (e.g. 200 MHz at 100 MIPS)
129 volatile uint32_t fcy; // CPU tick frequency (instruction cycle frequency = MIPS incl. DOZE divider)
130 volatile uint32_t fp; // Peripheral bus clock frequency
131 volatile uint32_t fpllo; // PLL output frequency
132 volatile uint32_t fvco; // PLL VCO frequency output incl. VCO divider
133 volatile float tp; // Peripheral bus clock period
134 volatile float tcy; // CPU instruction clock period
135 volatile uint32_t afpllo; // APLL output frequency
136 volatile uint32_t afvco; // APLL VCO frequency output incl. AVCO divider
137 }; // Data set of global system clock domain frequencies and periods
138 typedef struct OSCILLATOR_SYSTEM_FREQUENCIES_s OSCILLATOR_SYSTEM_FREQUENCIES_t; // Data set of global system clock domain frequencies and periods data type
139
140 /* FRC oscillator settings and tuning */
141 #if defined (__P33SMPS_CH__)
142
143 #define FRCTUN_MIN -32 // minimum tuning value
144 #define FRCTUN_MAX 31 // maximum tuning value
145 #define OSC_FRC_FREQ 8000000 // Frequency of the internal oscillator in [Hz]
146 #define OSC_FRC_TUN 0 // <OSCTUN> FRC Oscillator Tuning Rregister default value
147 #define OSC_TUN_STEP_PERCENTAGE 0.00047 // Oscillator frequency step size of <OSCTUN>
148
149 #elif defined (__P33SMPS_CK__)
150
151 #define FRCTUN_MIN -32 // minimum tuning value
152 #define FRCTUN_MAX 31 // maximum tuning value
153 #define OSC_FRC_FREQ 8000000 // Frequency of the internal oscillator in [Hz]
154 #define OSC_FRC_TUN 0 // <OSCTUN> FRC Oscillator Tuning Rregister value
155 #define OSC_TUN_STEP_PERCENTAGE 0.00047 // Oscillator frequency step size of <OSCTUN>
156
157 #else
158 #pragma message "error: === selected device family not supported by oscillator mcal driver library ==="
159 #endif
160
161 #define OSC_TUN_STEP_FREQUENCY (volatile int32_t)(OSC_FRC_FREQ * OSC_TUN_STEP_PERCENTAGE)
162
163 /* ***************************************************************************************
164 * BASIC DEFINES
165 * **************************************************************************************/
166
167 /* ===========================================================================
168 * OSCCON: OSCILLATOR CONTROL REGISTER
169 * ===========================================================================*/
170
171 #define REG_OSCCON_VALID_DATA_WRITE_MASK 0x0789
172 #define REG_OSCCON_VALID_DATA_READ_MASK 0x77A9
173
174 #define REG_OSCCON_OSWEN_REQUEST_SWITCH 0b0000000000001000
175 #define REG_OSCCON_OSWEN_SWITCH_COMPLETE 0b0000000000000000
176
177 enum OSCCON_OSWEN_e {
178 OSCCON_OSWEN_REQUEST_SWITCH = 0b1, // Requests oscillator switch to the selection specified by the NOSC<2:0> bits
179 OSCCON_OSWEN_SWITCH_COMPLETE = 0b0 // Oscillator switch is complete
180 }; // Oscillator Switch Enable bit
181 typedef enum OSCCON_OSWEN_e OSCCON_OSWEN_t; // Oscillator Switch Enable bit data type
182
183 #define REG_OSCCON_CF_CLKSTAT_FAIL 0b0000000000001000
184 #define REG_OSCCON_CF_CLKSTAT_OK 0b0000000000000000
185
186 enum OSCCON_CF_e {
187 OSCCON_CF_CLKSTAT_FAIL = 0b1, // FSCM has detected a clock failure
188 OSCCON_CF_CLKSTAT_OK = 0b0 // FSCM has not detected a clock failure
189 }; // Clock Fail Detect bit
190 typedef enum OSCCON_CF_e OSCCON_CF_t; // Clock Fail Detect bit data type
191
192 #define REG_OSCCON_LOCK_PLL_LOCKED 0b0000000000100000
193 #define REG_OSCCON_LOCK_PLL_UNLOCKED 0b0000000000000000
194
195 enum OSCCON_LOCK_e {
196 OSCCON_LOCK_PLL_LOCKED = 0b1, // Indicates that PLL is in lock or PLL start-up timer is satisfied
197 OSCCON_LOCK_PLL_UNLOCKED = 0b0 // Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
198 }; // PLL Lock Status bit (read-only)
199 typedef enum OSCCON_LOCK_e OSCCON_LOCK_t; // PLL Lock Status bit (read-only) data type
200
201 #define REG_OSCCON_CLKLOCK_LOCKED 0b0000000010000000
202 #define REG_OSCCON_CLKLOCK_UNLOCKED 0b0000000000000000
203
204 enum OSCCON_CLKLOCK_e{
205 OSCCON_CLKLOCK_LOCKED = 0b1, // If (FCKSM0 = 1), then clock and PLL configurations are locked; if (FCKSM0 = 0), then clock and PLL configurations may be modified
206 OSCCON_CLKLOCK_UNLOCKED = 0b0 // Clock and PLL selections are not locked, configurations may be modified
207 }; // Clock Lock Enable bit
208 typedef enum OSCCON_CLKLOCK_e OSCCON_CLKLOCK_t; // Clock Lock Enable bit data type
209
210 #define REG_OSCCON_NOSC_FRCDIVN 0b0000011100000000
211 #define REG_OSCCON_NOSC_BFRC 0b0000011000000000
212 #define REG_OSCCON_NOSC_LPRC 0b0000010100000000
213 #define REG_OSCCON_NOSC_PRIPLL 0b0000001100000000
214 #define REG_OSCCON_NOSC_PRI 0b0000001000000000
215 #define REG_OSCCON_NOSC_FRCPLL 0b0000000100000000
216 #define REG_OSCCON_NOSC_FRC 0b0000000000000000
217
218 #define REG_OSCCON_COSC_FRCDIVN 0b0111000000000000
219 #define REG_OSCCON_COSC_BFRC 0b0110000000000000
220 #define REG_OSCCON_COSC_LPRC 0b0101000000000000
221 #define REG_OSCCON_COSC_PRIPLL 0b0011000000000000
222 #define REG_OSCCON_COSC_PRI 0b0010000000000000
223 #define REG_OSCCON_COSC_FRCPLL 0b0001000000000000
224 #define REG_OSCCON_COSC_FRC 0b0000000000000000
225
226
227 enum OSCCON_xOSC_TYPE_e {
228 OSCCON_xOSC_FRC = 0b000, // Fast RC Oscillator, no PLL
229 OSCCON_xOSC_FRCPLL = 0b001, // Fast RC Oscillator with PLL
230 OSCCON_xOSC_PRI = 0b010, // Primary Oscillator (EC, XT, HS), no PLL
231 OSCCON_xOSC_PRIPLL = 0b011, // Primary Oscillator (EC, XT, HS) with PLL
232 OSCCON_xOSC_LPRC = 0b101, // Low Power Oscillator for Idle/Sleep Mode
233 OSCCON_xOSC_BFRC = 0b110, // Backup Fast RC Oscillator
234 OSCCON_xOSC_FRCDIVN = 0b111 // Fast RC Oscillator with variable Divider
235 }; // Oscillator Type Selection bits
236 typedef enum OSCCON_xOSC_TYPE_e OSCCON_xOSC_TYPE_t; // Oscillator Type Selection bits data type
237
238 struct P33C_OSC_CONFIG_s {
239 union {
240 struct {
241 volatile enum OSCCON_OSWEN_e OSWEN : 1; // Bit 0: Oscillator Switch Enable bit
242 volatile unsigned : 1; // Bit 1: reserved
243 volatile unsigned : 1; // Bit 2: reserved
244 volatile enum OSCCON_CF_e CF : 1; // Bit 3: Clock Fail Detect bit
245 volatile unsigned : 1; // Bit 4: reserved
246 volatile enum OSCCON_LOCK_e LOCK : 1; // Bit 5: PLL Lock Status bit (read only)
247 volatile unsigned : 1; // Bit 6: reserved
248 volatile enum OSCCON_CLKLOCK_e CLKLOCK : 1; // Bit 7: Clock Lock Enable bit
249 volatile enum OSCCON_xOSC_TYPE_e NOSC : 3; // Bit 8-10: New Oscillator Selection bits
250 volatile unsigned : 1; // Bit 11: reserved
251 volatile enum OSCCON_xOSC_TYPE_e COSC : 3; // Bit 12-14: Current Oscillator Selection bits (read only)
252 volatile unsigned : 1; // Bit 15: reserved
253 } __attribute__((packed)) bits;
254 volatile uint16_t value;
255 };
256
257 }; // Oscillator configuration special function register set
258 typedef struct P33C_OSC_CONFIG_s P33C_OSC_CONFIG_t; // Oscillator configuration special function register set data type
259
260 /* ===========================================================================
261 * CLKDIV: CLOCK DIVIDER REGISTER
262 * ===========================================================================*/
263
264 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
265
266 #define REG_CLKDIV_VALID_DATA_WRITE_MASK 0xFF0F
267 #define REG_CLKDIV_VALID_DATA_READ_MASK 0xFF0F
268
269 #define REG_CLKDIV_PLLPRE_DIV_MASK 0b0000000000001111
270 #define REG_CLKDIV_PLLPRE_DIVIDER_N1(x) {(x & REG_CLKDIV_PLLPRE_DIV_MASK)}
271
272 enum CLKDIV_PLLPRE_e {
273 CLKDIV_PLLDIV_N1_1 = 0b000001, // PLL Input Clock Divider Setting 1:1
274 CLKDIV_PLLDIV_N1_2 = 0b000010, // PLL Input Clock Divider Setting 1:2
275 CLKDIV_PLLDIV_N1_3 = 0b000011, // PLL Input Clock Divider Setting 1:3
276 CLKDIV_PLLDIV_N1_4 = 0b000100, // PLL Input Clock Divider Setting 1:4
277 CLKDIV_PLLDIV_N1_5 = 0b000101, // PLL Input Clock Divider Setting 1:5
278 CLKDIV_PLLDIV_N1_6 = 0b000110, // PLL Input Clock Divider Setting 1:6
279 CLKDIV_PLLDIV_N1_7 = 0b000111, // PLL Input Clock Divider Setting 1:7
280 CLKDIV_PLLDIV_N1_8 = 0b001000 // PLL Input Clock Divider Setting 1:8
281 }; // PLL Phase Detector Input Divider Select bits (also denoted as ?N1?, PLL prescaler) data type
282 typedef enum CLKDIV_PLLPRE_e CLKDIV_PLLPRE_t; // PLL Phase Detector Input Divider Select bits (also denoted as ?N1?, PLL prescaler) data type
283
284 #else
285 #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
286 #endif
287
288 #define REG_CLKDIV_DOZE_DIV_1 0b0000000000000000
289 #define REG_CLKDIV_DOZE_DIV_2 0b0001000000000000
290 #define REG_CLKDIV_DOZE_DIV_4 0b0010000000000000
291 #define REG_CLKDIV_DOZE_DIV_8 0b0011000000000000
292 #define REG_CLKDIV_DOZE_DIV_16 0b0100000000000000
293 #define REG_CLKDIV_DOZE_DIV_32 0b0101000000000000
294 #define REG_CLKDIV_DOZE_DIV_64 0b0110000000000000
295 #define REG_CLKDIV_DOZE_DIV_128 0b0111000000000000
296
297 enum CLKDIV_DOZE_e {
298 CLKDIV_DOZE_DIV_1 = 0b000, // FCY Clock Divider Setting 1:1
299 CLKDIV_DOZE_DIV_2 = 0b001, // FCY Clock Divider Setting 1:2
300 CLKDIV_DOZE_DIV_4 = 0b010, // FCY Clock Divider Setting 1:4
301 CLKDIV_DOZE_DIV_8 = 0b011, // FCY Clock Divider Setting 1:8
302 CLKDIV_DOZE_DIV_16 = 0b100, // FCY Clock Divider Setting 1:16
303 CLKDIV_DOZE_DIV_32 = 0b101, // FCY Clock Divider Setting 1:32
304 CLKDIV_DOZE_DIV_64 = 0b110, // FCY Clock Divider Setting 1:64
305 CLKDIV_DOZE_DIV_128 = 0b111 // FCY Clock Divider Setting 1:128
306 }; // Processor Clock Reduction Select bits
307 typedef enum CLKDIV_DOZE_e CLKDIV_DOZE_t; // Processor Clock Reduction Select bits data type
308
309 #define REG_CLKDIV_DOZEN_ENABLED 0b0000100000000000
310 #define REG_CLKDIV_DOZEN_DISABLED 0b0000000000000000
311
312 enum CLKDIV_DOZEN_e {
313 CLKDIV_DOZEN_ENABLED = 0b1, // DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
314 CLKDIV_DOZEN_DISABLED = 0b0 // Processor clock and peripheral clock ratio is forced to 1:1
315 }; // Doze Mode Enable bit
316 typedef enum CLKDIV_DOZEN_e CLKDIV_DOZEN_t; // Doze Mode Enable bit data type
317
318 #define REG_CLKDIV_FRCDIVN_256 0b0000011100000000
319 #define REG_CLKDIV_FRCDIVN_64 0b0000011000000000
320 #define REG_CLKDIV_FRCDIVN_32 0b0000010100000000
321 #define REG_CLKDIV_FRCDIVN_16 0b0000010000000000
322 #define REG_CLKDIV_FRCDIVN_8 0b0000001100000000
323 #define REG_CLKDIV_FRCDIVN_4 0b0000001000000000
324 #define REG_CLKDIV_FRCDIVN_2 0b0000000100000000
325 #define REG_CLKDIV_FRCDIVN_1 0b0000000000000000
326
327 enum CLKDIV_FRCDIVN_e {
328 CLKDIV_FRCDIVN_1 = 0b000, // Fast RC Oscillator Clock Divider Setting 1:1
329 CLKDIV_FRCDIVN_2 = 0b001, // Fast RC Oscillator Clock Divider Setting 1:2
330 CLKDIV_FRCDIVN_4 = 0b010, // Fast RC Oscillator Clock Divider Setting 1:4
331 CLKDIV_FRCDIVN_8 = 0b011, // Fast RC Oscillator Clock Divider Setting 1:8
332 CLKDIV_FRCDIVN_16 = 0b100, // Fast RC Oscillator Clock Divider Setting 1:16
333 CLKDIV_FRCDIVN_32 = 0b101, // Fast RC Oscillator Clock Divider Setting 1:32
334 CLKDIV_FRCDIVN_64 = 0b110, // Fast RC Oscillator Clock Divider Setting 1:64
335 CLKDIV_FRCDIVN_256 = 0b111 // Fast RC Oscillator Clock Divider Setting 1:256
336 }; // Internal Fast RC Oscillator Postscaler bits data type
337 typedef enum CLKDIV_FRCDIVN_e CLKDIV_FRCDIVN_t; // Internal Fast RC Oscillator Postscaler bits data type
338
339 #define REG_CLKDIV_ROI_ENABLED 0b1000000000000000
340 #define REG_CLKDIV_ROI_DISABLED 0b0000000000000000
341
342 enum CLKDIV_ROI_e {
343 CLKDIV_ROI_ENABLED = 0b1, // Interrupts will clear the DOZEN bit and the processor clock, and the peripheral clock ratio is set to 1:1
344 CLKDIV_ROI_DISABLED = 0b0 // Interrupts have no effect on the DOZEN bit
345 }; // Recover on Interrupt bit
346 typedef enum CLKDIV_ROI_e CLKDIV_ROI_t; // Recover on Interrupt bit data type
347
348 struct CLKDIV_s {
349 union {
350 struct {
351 volatile enum CLKDIV_PLLPRE_e PLLPRE : 4; // PLL Phase Detector Input Divider Select bits (also denoted as ?N1?, PLL prescaler)
352 volatile unsigned : 4;
353 volatile enum CLKDIV_FRCDIVN_e FRCDIV : 3; // Internal Fast RC Oscillator Postscaler bits
354 volatile enum CLKDIV_DOZEN_e DOZEN : 1; // Doze Mode Enable bit
355 volatile enum CLKDIV_DOZE_e DOZE : 3; // Processor Clock Reduction Select bits
356 volatile enum CLKDIV_ROI_e ROI : 1; // Recover on Interrupt bit
357 } __attribute__((packed)) bits;
358 volatile uint16_t value;
359 };
360 }; // CLKDIV: clock divider register data type
361 typedef struct CLKDIV_s CLKDIV_t; // CLKDIV: clock divider register data type
362
363
364 /* ===========================================================================
365 * PLLFBD: PLL FEEDBACK DIVIDER REGISTER
366 * ===========================================================================*/
367
368 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
369
370 #define REG_PLLFBD_VALID_DATA_WRITE_MASK 0x00FF
371 #define REG_PLLFBD_VALID_DATA_READ_MASK 0x00FF
372
373 #define REG_PLLFBD_PLLFBDIV_M_MASK 0b0000000011111111
374 #define REG_PLLFBD_MULTIPLIER_M(x) {(x & REG_PLLFBD_PLLFBDIV_M_MASK)}
375
376 enum PLLFBD_PLLFBDIV_e {
377 PLLFBD_PLLFBDIV_M_16 = 0b00010000, // PLL Input Clock Multiplier Setting x16
378 PLLFBD_PLLFBDIV_M_17 = 0b00010001, // PLL Input Clock Multiplier Setting x17
379 PLLFBD_PLLFBDIV_M_18 = 0b00010010, // PLL Input Clock Multiplier Setting x18
380 PLLFBD_PLLFBDIV_M_19 = 0b00010011, // PLL Input Clock Multiplier Setting x19
381 PLLFBD_PLLFBDIV_M_20 = 0b00010100, // PLL Input Clock Multiplier Setting x20
382 PLLFBD_PLLFBDIV_M_21 = 0b00010101, // PLL Input Clock Multiplier Setting x21
383 PLLFBD_PLLFBDIV_M_22 = 0b00010110, // PLL Input Clock Multiplier Setting x22
384 PLLFBD_PLLFBDIV_M_23 = 0b00010111, // PLL Input Clock Multiplier Setting x23
385 PLLFBD_PLLFBDIV_M_24 = 0b00011000, // PLL Input Clock Multiplier Setting x24
386 PLLFBD_PLLFBDIV_M_25 = 0b00011001, // PLL Input Clock Multiplier Setting x25
387 PLLFBD_PLLFBDIV_M_26 = 0b00011010, // PLL Input Clock Multiplier Setting x26
388 PLLFBD_PLLFBDIV_M_27 = 0b00011011, // PLL Input Clock Multiplier Setting x27
389 PLLFBD_PLLFBDIV_M_28 = 0b00011100, // PLL Input Clock Multiplier Setting x28
390 PLLFBD_PLLFBDIV_M_29 = 0b00011101, // PLL Input Clock Multiplier Setting x29
391 PLLFBD_PLLFBDIV_M_30 = 0b00011110, // PLL Input Clock Multiplier Setting x30
392 PLLFBD_PLLFBDIV_M_31 = 0b00011111, // PLL Input Clock Multiplier Setting x31
393 PLLFBD_PLLFBDIV_M_32 = 0b00100000, // PLL Input Clock Multiplier Setting x32
394 PLLFBD_PLLFBDIV_M_33 = 0b00100001, // PLL Input Clock Multiplier Setting x33
395 PLLFBD_PLLFBDIV_M_34 = 0b00100010, // PLL Input Clock Multiplier Setting x34
396 PLLFBD_PLLFBDIV_M_35 = 0b00100011, // PLL Input Clock Multiplier Setting x35
397 PLLFBD_PLLFBDIV_M_36 = 0b00100100, // PLL Input Clock Multiplier Setting x36
398 PLLFBD_PLLFBDIV_M_37 = 0b00100101, // PLL Input Clock Multiplier Setting x37
399 PLLFBD_PLLFBDIV_M_38 = 0b00100110, // PLL Input Clock Multiplier Setting x38
400 PLLFBD_PLLFBDIV_M_39 = 0b00100111, // PLL Input Clock Multiplier Setting x39
401 PLLFBD_PLLFBDIV_M_40 = 0b00101000, // PLL Input Clock Multiplier Setting x40
402 PLLFBD_PLLFBDIV_M_41 = 0b00101001, // PLL Input Clock Multiplier Setting x41
403 PLLFBD_PLLFBDIV_M_42 = 0b00101010, // PLL Input Clock Multiplier Setting x42
404 PLLFBD_PLLFBDIV_M_43 = 0b00101011, // PLL Input Clock Multiplier Setting x43
405 PLLFBD_PLLFBDIV_M_44 = 0b00101100, // PLL Input Clock Multiplier Setting x44
406 PLLFBD_PLLFBDIV_M_45 = 0b00101101, // PLL Input Clock Multiplier Setting x45
407 PLLFBD_PLLFBDIV_M_46 = 0b00101110, // PLL Input Clock Multiplier Setting x46
408 PLLFBD_PLLFBDIV_M_47 = 0b00101111, // PLL Input Clock Multiplier Setting x47
409 PLLFBD_PLLFBDIV_M_48 = 0b00110000, // PLL Input Clock Multiplier Setting x48
410 PLLFBD_PLLFBDIV_M_49 = 0b00110001, // PLL Input Clock Multiplier Setting x49
411 PLLFBD_PLLFBDIV_M_50 = 0b00110010, // PLL Input Clock Multiplier Setting x50
412 PLLFBD_PLLFBDIV_M_51 = 0b00110011, // PLL Input Clock Multiplier Setting x51
413 PLLFBD_PLLFBDIV_M_52 = 0b00110100, // PLL Input Clock Multiplier Setting x52
414 PLLFBD_PLLFBDIV_M_53 = 0b00110101, // PLL Input Clock Multiplier Setting x53
415 PLLFBD_PLLFBDIV_M_54 = 0b00110110, // PLL Input Clock Multiplier Setting x54
416 PLLFBD_PLLFBDIV_M_55 = 0b00110111, // PLL Input Clock Multiplier Setting x55
417 PLLFBD_PLLFBDIV_M_56 = 0b00111000, // PLL Input Clock Multiplier Setting x56
418 PLLFBD_PLLFBDIV_M_57 = 0b00111001, // PLL Input Clock Multiplier Setting x57
419 PLLFBD_PLLFBDIV_M_58 = 0b00111010, // PLL Input Clock Multiplier Setting x58
420 PLLFBD_PLLFBDIV_M_59 = 0b00111011, // PLL Input Clock Multiplier Setting x59
421 PLLFBD_PLLFBDIV_M_60 = 0b00111100, // PLL Input Clock Multiplier Setting x60
422 PLLFBD_PLLFBDIV_M_61 = 0b00111101, // PLL Input Clock Multiplier Setting x61
423 PLLFBD_PLLFBDIV_M_62 = 0b00111110, // PLL Input Clock Multiplier Setting x62
424 PLLFBD_PLLFBDIV_M_63 = 0b00111111, // PLL Input Clock Multiplier Setting x63
425 PLLFBD_PLLFBDIV_M_64 = 0b01000000, // PLL Input Clock Multiplier Setting x64
426 PLLFBD_PLLFBDIV_M_65 = 0b01000001, // PLL Input Clock Multiplier Setting x65
427 PLLFBD_PLLFBDIV_M_66 = 0b01000010, // PLL Input Clock Multiplier Setting x66
428 PLLFBD_PLLFBDIV_M_67 = 0b01000011, // PLL Input Clock Multiplier Setting x67
429 PLLFBD_PLLFBDIV_M_68 = 0b01000100, // PLL Input Clock Multiplier Setting x68
430 PLLFBD_PLLFBDIV_M_69 = 0b01000101, // PLL Input Clock Multiplier Setting x69
431 PLLFBD_PLLFBDIV_M_70 = 0b01000110, // PLL Input Clock Multiplier Setting x70
432 PLLFBD_PLLFBDIV_M_71 = 0b01000111, // PLL Input Clock Multiplier Setting x71
433 PLLFBD_PLLFBDIV_M_72 = 0b01001000, // PLL Input Clock Multiplier Setting x72
434 PLLFBD_PLLFBDIV_M_73 = 0b01001001, // PLL Input Clock Multiplier Setting x73
435 PLLFBD_PLLFBDIV_M_74 = 0b01001010, // PLL Input Clock Multiplier Setting x74
436 PLLFBD_PLLFBDIV_M_75 = 0b01001011, // PLL Input Clock Multiplier Setting x75
437 PLLFBD_PLLFBDIV_M_76 = 0b01001100, // PLL Input Clock Multiplier Setting x76
438 PLLFBD_PLLFBDIV_M_77 = 0b01001101, // PLL Input Clock Multiplier Setting x77
439 PLLFBD_PLLFBDIV_M_78 = 0b01001110, // PLL Input Clock Multiplier Setting x78
440 PLLFBD_PLLFBDIV_M_79 = 0b01001111, // PLL Input Clock Multiplier Setting x79
441 PLLFBD_PLLFBDIV_M_80 = 0b01010000, // PLL Input Clock Multiplier Setting x80
442 PLLFBD_PLLFBDIV_M_81 = 0b01010001, // PLL Input Clock Multiplier Setting x81
443 PLLFBD_PLLFBDIV_M_82 = 0b01010010, // PLL Input Clock Multiplier Setting x82
444 PLLFBD_PLLFBDIV_M_83 = 0b01010011, // PLL Input Clock Multiplier Setting x83
445 PLLFBD_PLLFBDIV_M_84 = 0b01010100, // PLL Input Clock Multiplier Setting x84
446 PLLFBD_PLLFBDIV_M_85 = 0b01010101, // PLL Input Clock Multiplier Setting x85
447 PLLFBD_PLLFBDIV_M_86 = 0b01010110, // PLL Input Clock Multiplier Setting x86
448 PLLFBD_PLLFBDIV_M_87 = 0b01010111, // PLL Input Clock Multiplier Setting x87
449 PLLFBD_PLLFBDIV_M_88 = 0b01011000, // PLL Input Clock Multiplier Setting x88
450 PLLFBD_PLLFBDIV_M_89 = 0b01011001, // PLL Input Clock Multiplier Setting x89
451 PLLFBD_PLLFBDIV_M_90 = 0b01011010, // PLL Input Clock Multiplier Setting x90
452 PLLFBD_PLLFBDIV_M_91 = 0b01011011, // PLL Input Clock Multiplier Setting x91
453 PLLFBD_PLLFBDIV_M_92 = 0b01011100, // PLL Input Clock Multiplier Setting x92
454 PLLFBD_PLLFBDIV_M_93 = 0b01011101, // PLL Input Clock Multiplier Setting x93
455 PLLFBD_PLLFBDIV_M_94 = 0b01011110, // PLL Input Clock Multiplier Setting x94
456 PLLFBD_PLLFBDIV_M_95 = 0b01011111, // PLL Input Clock Multiplier Setting x95
457 PLLFBD_PLLFBDIV_M_96 = 0b01100000, // PLL Input Clock Multiplier Setting x96
458 PLLFBD_PLLFBDIV_M_97 = 0b01100001, // PLL Input Clock Multiplier Setting x97
459 PLLFBD_PLLFBDIV_M_98 = 0b01100010, // PLL Input Clock Multiplier Setting x98
460 PLLFBD_PLLFBDIV_M_99 = 0b01100011, // PLL Input Clock Multiplier Setting x99
461 PLLFBD_PLLFBDIV_M_100 = 0b01100100, // PLL Input Clock Multiplier Setting x100
462 PLLFBD_PLLFBDIV_M_101 = 0b01100101, // PLL Input Clock Multiplier Setting x101
463 PLLFBD_PLLFBDIV_M_102 = 0b01100110, // PLL Input Clock Multiplier Setting x102
464 PLLFBD_PLLFBDIV_M_103 = 0b01100111, // PLL Input Clock Multiplier Setting x103
465 PLLFBD_PLLFBDIV_M_104 = 0b01101000, // PLL Input Clock Multiplier Setting x104
466 PLLFBD_PLLFBDIV_M_105 = 0b01101001, // PLL Input Clock Multiplier Setting x105
467 PLLFBD_PLLFBDIV_M_106 = 0b01101010, // PLL Input Clock Multiplier Setting x106
468 PLLFBD_PLLFBDIV_M_107 = 0b01101011, // PLL Input Clock Multiplier Setting x107
469 PLLFBD_PLLFBDIV_M_108 = 0b01101100, // PLL Input Clock Multiplier Setting x108
470 PLLFBD_PLLFBDIV_M_109 = 0b01101101, // PLL Input Clock Multiplier Setting x109
471 PLLFBD_PLLFBDIV_M_110 = 0b01101110, // PLL Input Clock Multiplier Setting x110
472 PLLFBD_PLLFBDIV_M_111 = 0b01101111, // PLL Input Clock Multiplier Setting x111
473 PLLFBD_PLLFBDIV_M_112 = 0b01110000, // PLL Input Clock Multiplier Setting x112
474 PLLFBD_PLLFBDIV_M_113 = 0b01110001, // PLL Input Clock Multiplier Setting x113
475 PLLFBD_PLLFBDIV_M_114 = 0b01110010, // PLL Input Clock Multiplier Setting x114
476 PLLFBD_PLLFBDIV_M_115 = 0b01110011, // PLL Input Clock Multiplier Setting x115
477 PLLFBD_PLLFBDIV_M_116 = 0b01110100, // PLL Input Clock Multiplier Setting x116
478 PLLFBD_PLLFBDIV_M_117 = 0b01110101, // PLL Input Clock Multiplier Setting x117
479 PLLFBD_PLLFBDIV_M_118 = 0b01110110, // PLL Input Clock Multiplier Setting x118
480 PLLFBD_PLLFBDIV_M_119 = 0b01110111, // PLL Input Clock Multiplier Setting x119
481 PLLFBD_PLLFBDIV_M_120 = 0b01111000, // PLL Input Clock Multiplier Setting x120
482 PLLFBD_PLLFBDIV_M_121 = 0b01111001, // PLL Input Clock Multiplier Setting x121
483 PLLFBD_PLLFBDIV_M_122 = 0b01111010, // PLL Input Clock Multiplier Setting x122
484 PLLFBD_PLLFBDIV_M_123 = 0b01111011, // PLL Input Clock Multiplier Setting x123
485 PLLFBD_PLLFBDIV_M_124 = 0b01111100, // PLL Input Clock Multiplier Setting x124
486 PLLFBD_PLLFBDIV_M_125 = 0b01111101, // PLL Input Clock Multiplier Setting x125
487 PLLFBD_PLLFBDIV_M_126 = 0b01111110, // PLL Input Clock Multiplier Setting x126
488 PLLFBD_PLLFBDIV_M_127 = 0b01111111, // PLL Input Clock Multiplier Setting x127
489 PLLFBD_PLLFBDIV_M_128 = 0b10000000, // PLL Input Clock Multiplier Setting x128
490 PLLFBD_PLLFBDIV_M_129 = 0b10000001, // PLL Input Clock Multiplier Setting x129
491 PLLFBD_PLLFBDIV_M_130 = 0b10000010, // PLL Input Clock Multiplier Setting x130
492 PLLFBD_PLLFBDIV_M_131 = 0b10000011, // PLL Input Clock Multiplier Setting x131
493 PLLFBD_PLLFBDIV_M_132 = 0b10000100, // PLL Input Clock Multiplier Setting x132
494 PLLFBD_PLLFBDIV_M_133 = 0b10000101, // PLL Input Clock Multiplier Setting x133
495 PLLFBD_PLLFBDIV_M_134 = 0b10000110, // PLL Input Clock Multiplier Setting x134
496 PLLFBD_PLLFBDIV_M_135 = 0b10000111, // PLL Input Clock Multiplier Setting x135
497 PLLFBD_PLLFBDIV_M_136 = 0b10001000, // PLL Input Clock Multiplier Setting x136
498 PLLFBD_PLLFBDIV_M_137 = 0b10001001, // PLL Input Clock Multiplier Setting x137
499 PLLFBD_PLLFBDIV_M_138 = 0b10001010, // PLL Input Clock Multiplier Setting x138
500 PLLFBD_PLLFBDIV_M_139 = 0b10001011, // PLL Input Clock Multiplier Setting x139
501 PLLFBD_PLLFBDIV_M_140 = 0b10001100, // PLL Input Clock Multiplier Setting x140
502 PLLFBD_PLLFBDIV_M_141 = 0b10001101, // PLL Input Clock Multiplier Setting x141
503 PLLFBD_PLLFBDIV_M_142 = 0b10001110, // PLL Input Clock Multiplier Setting x142
504 PLLFBD_PLLFBDIV_M_143 = 0b10001111, // PLL Input Clock Multiplier Setting x143
505 PLLFBD_PLLFBDIV_M_144 = 0b10010000, // PLL Input Clock Multiplier Setting x144
506 PLLFBD_PLLFBDIV_M_145 = 0b10010001, // PLL Input Clock Multiplier Setting x145
507 PLLFBD_PLLFBDIV_M_146 = 0b10010010, // PLL Input Clock Multiplier Setting x146
508 PLLFBD_PLLFBDIV_M_147 = 0b10010011, // PLL Input Clock Multiplier Setting x147
509 PLLFBD_PLLFBDIV_M_148 = 0b10010100, // PLL Input Clock Multiplier Setting x148
510 PLLFBD_PLLFBDIV_M_149 = 0b10010101, // PLL Input Clock Multiplier Setting x149
511 PLLFBD_PLLFBDIV_M_150 = 0b10010110, // PLL Input Clock Multiplier Setting x150
512 PLLFBD_PLLFBDIV_M_151 = 0b10010111, // PLL Input Clock Multiplier Setting x151
513 PLLFBD_PLLFBDIV_M_152 = 0b10011000, // PLL Input Clock Multiplier Setting x152
514 PLLFBD_PLLFBDIV_M_153 = 0b10011001, // PLL Input Clock Multiplier Setting x153
515 PLLFBD_PLLFBDIV_M_154 = 0b10011010, // PLL Input Clock Multiplier Setting x154
516 PLLFBD_PLLFBDIV_M_155 = 0b10011011, // PLL Input Clock Multiplier Setting x155
517 PLLFBD_PLLFBDIV_M_156 = 0b10011100, // PLL Input Clock Multiplier Setting x156
518 PLLFBD_PLLFBDIV_M_157 = 0b10011101, // PLL Input Clock Multiplier Setting x157
519 PLLFBD_PLLFBDIV_M_158 = 0b10011110, // PLL Input Clock Multiplier Setting x158
520 PLLFBD_PLLFBDIV_M_159 = 0b10011111, // PLL Input Clock Multiplier Setting x159
521 PLLFBD_PLLFBDIV_M_160 = 0b10100000, // PLL Input Clock Multiplier Setting x160
522 PLLFBD_PLLFBDIV_M_161 = 0b10100001, // PLL Input Clock Multiplier Setting x161
523 PLLFBD_PLLFBDIV_M_162 = 0b10100010, // PLL Input Clock Multiplier Setting x162
524 PLLFBD_PLLFBDIV_M_163 = 0b10100011, // PLL Input Clock Multiplier Setting x163
525 PLLFBD_PLLFBDIV_M_164 = 0b10100100, // PLL Input Clock Multiplier Setting x164
526 PLLFBD_PLLFBDIV_M_165 = 0b10100101, // PLL Input Clock Multiplier Setting x165
527 PLLFBD_PLLFBDIV_M_166 = 0b10100110, // PLL Input Clock Multiplier Setting x166
528 PLLFBD_PLLFBDIV_M_167 = 0b10100111, // PLL Input Clock Multiplier Setting x167
529 PLLFBD_PLLFBDIV_M_168 = 0b10101000, // PLL Input Clock Multiplier Setting x168
530 PLLFBD_PLLFBDIV_M_169 = 0b10101001, // PLL Input Clock Multiplier Setting x169
531 PLLFBD_PLLFBDIV_M_170 = 0b10101010, // PLL Input Clock Multiplier Setting x170
532 PLLFBD_PLLFBDIV_M_171 = 0b10101011, // PLL Input Clock Multiplier Setting x171
533 PLLFBD_PLLFBDIV_M_172 = 0b10101100, // PLL Input Clock Multiplier Setting x172
534 PLLFBD_PLLFBDIV_M_173 = 0b10101101, // PLL Input Clock Multiplier Setting x173
535 PLLFBD_PLLFBDIV_M_174 = 0b10101110, // PLL Input Clock Multiplier Setting x174
536 PLLFBD_PLLFBDIV_M_175 = 0b10101111, // PLL Input Clock Multiplier Setting x175
537 PLLFBD_PLLFBDIV_M_176 = 0b10110000, // PLL Input Clock Multiplier Setting x176
538 PLLFBD_PLLFBDIV_M_177 = 0b10110001, // PLL Input Clock Multiplier Setting x177
539 PLLFBD_PLLFBDIV_M_178 = 0b10110010, // PLL Input Clock Multiplier Setting x178
540 PLLFBD_PLLFBDIV_M_179 = 0b10110011, // PLL Input Clock Multiplier Setting x179
541 PLLFBD_PLLFBDIV_M_180 = 0b10110100, // PLL Input Clock Multiplier Setting x180
542 PLLFBD_PLLFBDIV_M_181 = 0b10110101, // PLL Input Clock Multiplier Setting x181
543 PLLFBD_PLLFBDIV_M_182 = 0b10110110, // PLL Input Clock Multiplier Setting x182
544 PLLFBD_PLLFBDIV_M_183 = 0b10110111, // PLL Input Clock Multiplier Setting x183
545 PLLFBD_PLLFBDIV_M_184 = 0b10111000, // PLL Input Clock Multiplier Setting x184
546 PLLFBD_PLLFBDIV_M_185 = 0b10111001, // PLL Input Clock Multiplier Setting x185
547 PLLFBD_PLLFBDIV_M_186 = 0b10111010, // PLL Input Clock Multiplier Setting x186
548 PLLFBD_PLLFBDIV_M_187 = 0b10111011, // PLL Input Clock Multiplier Setting x187
549 PLLFBD_PLLFBDIV_M_188 = 0b10111100, // PLL Input Clock Multiplier Setting x188
550 PLLFBD_PLLFBDIV_M_189 = 0b10111101, // PLL Input Clock Multiplier Setting x189
551 PLLFBD_PLLFBDIV_M_190 = 0b10111110, // PLL Input Clock Multiplier Setting x190
552 PLLFBD_PLLFBDIV_M_191 = 0b10111111, // PLL Input Clock Multiplier Setting x191
553 PLLFBD_PLLFBDIV_M_192 = 0b11000000, // PLL Input Clock Multiplier Setting x192
554 PLLFBD_PLLFBDIV_M_193 = 0b11000001, // PLL Input Clock Multiplier Setting x193
555 PLLFBD_PLLFBDIV_M_194 = 0b11000010, // PLL Input Clock Multiplier Setting x194
556 PLLFBD_PLLFBDIV_M_195 = 0b11000011, // PLL Input Clock Multiplier Setting x195
557 PLLFBD_PLLFBDIV_M_196 = 0b11000100, // PLL Input Clock Multiplier Setting x196
558 PLLFBD_PLLFBDIV_M_197 = 0b11000101, // PLL Input Clock Multiplier Setting x197
559 PLLFBD_PLLFBDIV_M_198 = 0b11000110, // PLL Input Clock Multiplier Setting x198
560 PLLFBD_PLLFBDIV_M_199 = 0b11000111, // PLL Input Clock Multiplier Setting x199
561 PLLFBD_PLLFBDIV_M_200 = 0b11001000 // PLL Input Clock Multiplier Setting x200
562 }; // PLL Feedback Divider bits (also denoted as ?M?, PLL multiplier) data type
563 typedef enum PLLFBD_PLLFBDIV_e PLLFBD_PLLFBDIV_t; // PLL Feedback Divider bits (also denoted as ?M?, PLL multiplier) data type
564
565 struct PLLFBD_s {
566 union {
567 struct {
568 volatile enum PLLFBD_PLLFBDIV_e PLLFBDIV : 8; // PLL Feedback Divider bits (also denoted as ?M?, PLL multiplier)
569 volatile unsigned : 8; // reserved
570 } __attribute__((packed)) bits;
571 volatile uint16_t value;
572 };
573 };
574 typedef struct PLLFBD_s PLLFBD_t;
575
576 #else
577 #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
578 #endif
579
580
581 /* ===========================================================================
582 * OSCTUN: FRC OSCILLATOR TUNING REGISTER
583 * ===========================================================================*/
584
585 #define REG_OSCTUN_VALID_DATA_WRITE_MASK 0x003F
586 #define REG_OSCTUN_VALID_DATA_READ_MASK 0x003F
587
588 #define REG_OSCTUN_TUNE_VALUE_MASK 0b0000000000111111
589 #define REG_OSCTUN_TUNE_VALUE(x) {(x & REG_OSCTUN_TUNE_VALUE_MASK)}
590
591 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
592
593 enum OSCTUN_TUN_e {
594 OSCTUN_TUN_MINUS_31 = 0b100001, // Center frequency -1.457% (=7.88344 MHz)
595 OSCTUN_TUN_MINUS_30 = 0b100010, // Center frequency -1.41% (=7.8872 MHz)
596 OSCTUN_TUN_MINUS_29 = 0b100011, // Center frequency -1.363% (=7.89096 MHz)
597 OSCTUN_TUN_MINUS_28 = 0b100100, // Center frequency -1.316% (=7.89472 MHz)
598 OSCTUN_TUN_MINUS_27 = 0b100101, // Center frequency -1.269% (=7.89848 MHz)
599 OSCTUN_TUN_MINUS_26 = 0b100110, // Center frequency -1.222% (=7.90224 MHz)
600 OSCTUN_TUN_MINUS_25 = 0b100111, // Center frequency -1.175% (=7.906 MHz)
601 OSCTUN_TUN_MINUS_24 = 0b101000, // Center frequency -1.128% (=7.90976 MHz)
602 OSCTUN_TUN_MINUS_23 = 0b101001, // Center frequency -1.081% (=7.91352 MHz)
603 OSCTUN_TUN_MINUS_22 = 0b101010, // Center frequency -1.034% (=7.91728 MHz)
604 OSCTUN_TUN_MINUS_21 = 0b101011, // Center frequency -0.987% (=7.92104 MHz)
605 OSCTUN_TUN_MINUS_20 = 0b101100, // Center frequency -0.94% (=7.9248 MHz)
606 OSCTUN_TUN_MINUS_19 = 0b101101, // Center frequency -0.893% (=7.92856 MHz)
607 OSCTUN_TUN_MINUS_18 = 0b101110, // Center frequency -0.846% (=7.93232 MHz)
608 OSCTUN_TUN_MINUS_17 = 0b101111, // Center frequency -0.799% (=7.93608 MHz)
609 OSCTUN_TUN_MINUS_16 = 0b110000, // Center frequency -0.752% (=7.93984 MHz)
610 OSCTUN_TUN_MINUS_15 = 0b110001, // Center frequency -0.705% (=7.9436 MHz)
611 OSCTUN_TUN_MINUS_14 = 0b110010, // Center frequency -0.658% (=7.94736 MHz)
612 OSCTUN_TUN_MINUS_13 = 0b110011, // Center frequency -0.611% (=7.95112 MHz)
613 OSCTUN_TUN_MINUS_12 = 0b110100, // Center frequency -0.564% (=7.95488 MHz)
614 OSCTUN_TUN_MINUS_11 = 0b110101, // Center frequency -0.517% (=7.95864 MHz)
615 OSCTUN_TUN_MINUS_10 = 0b110110, // Center frequency -0.47% (=7.9624 MHz)
616 OSCTUN_TUN_MINUS_9 = 0b110111, // Center frequency -0.423% (=7.96616 MHz)
617 OSCTUN_TUN_MINUS_8 = 0b111000, // Center frequency -0.376% (=7.96992 MHz)
618 OSCTUN_TUN_MINUS_7 = 0b111001, // Center frequency -0.329% (=7.97368 MHz)
619 OSCTUN_TUN_MINUS_6 = 0b111010, // Center frequency -0.282% (=7.97744 MHz)
620 OSCTUN_TUN_MINUS_5 = 0b111011, // Center frequency -0.235% (=7.9812 MHz)
621 OSCTUN_TUN_MINUS_4 = 0b111100, // Center frequency -0.188% (=7.98496 MHz)
622 OSCTUN_TUN_MINUS_3 = 0b111101, // Center frequency -0.141% (=7.98872 MHz)
623 OSCTUN_TUN_MINUS_2 = 0b111110, // Center frequency -0.094% (=7.99248 MHz)
624 OSCTUN_TUN_MINUS_1 = 0b111111, // Center frequency -0.047% (=7.99624 MHz)
625 OSCTUN_TUN_NOMINAL = 0b000000, // Center frequency +0% (=8 MHz)
626 OSCTUN_TUN_PLUS_1 = 0b000001, // Center frequency +0.047% (=8.00376 MHz)
627 OSCTUN_TUN_PLUS_2 = 0b000010, // Center frequency +0.094% (=8.00752 MHz)
628 OSCTUN_TUN_PLUS_3 = 0b000011, // Center frequency +0.141% (=8.01128 MHz)
629 OSCTUN_TUN_PLUS_4 = 0b000100, // Center frequency +0.188% (=8.01504 MHz)
630 OSCTUN_TUN_PLUS_5 = 0b000101, // Center frequency +0.235% (=8.0188 MHz)
631 OSCTUN_TUN_PLUS_6 = 0b000110, // Center frequency +0.282% (=8.02256 MHz)
632 OSCTUN_TUN_PLUS_7 = 0b000111, // Center frequency +0.329% (=8.02632 MHz)
633 OSCTUN_TUN_PLUS_8 = 0b001000, // Center frequency +0.376% (=8.03008 MHz)
634 OSCTUN_TUN_PLUS_9 = 0b001001, // Center frequency +0.423% (=8.03384 MHz)
635 OSCTUN_TUN_PLUS_10 = 0b001010, // Center frequency +0.47% (=8.0376 MHz)
636 OSCTUN_TUN_PLUS_11 = 0b001011, // Center frequency +0.517% (=8.04136 MHz)
637 OSCTUN_TUN_PLUS_12 = 0b001100, // Center frequency +0.564% (=8.04512 MHz)
638 OSCTUN_TUN_PLUS_13 = 0b001101, // Center frequency +0.611% (=8.04888 MHz)
639 OSCTUN_TUN_PLUS_14 = 0b001110, // Center frequency +0.658% (=8.05264 MHz)
640 OSCTUN_TUN_PLUS_15 = 0b001111, // Center frequency +0.705% (=8.0564 MHz)
641 OSCTUN_TUN_PLUS_16 = 0b010000, // Center frequency +0.752% (=8.06016 MHz)
642 OSCTUN_TUN_PLUS_17 = 0b010001, // Center frequency +0.799% (=8.06392 MHz)
643 OSCTUN_TUN_PLUS_18 = 0b010010, // Center frequency +0.846% (=8.06768 MHz)
644 OSCTUN_TUN_PLUS_19 = 0b010011, // Center frequency +0.893% (=8.07144 MHz)
645 OSCTUN_TUN_PLUS_20 = 0b010100, // Center frequency +0.94% (=8.0752 MHz)
646 OSCTUN_TUN_PLUS_21 = 0b010101, // Center frequency +0.987% (=8.07896 MHz)
647 OSCTUN_TUN_PLUS_22 = 0b010110, // Center frequency +1.034% (=8.08272 MHz)
648 OSCTUN_TUN_PLUS_23 = 0b010111, // Center frequency +1.081% (=8.08648 MHz)
649 OSCTUN_TUN_PLUS_24 = 0b011000, // Center frequency +1.128% (=8.09024 MHz)
650 OSCTUN_TUN_PLUS_25 = 0b011001, // Center frequency +1.175% (=8.094 MHz)
651 OSCTUN_TUN_PLUS_26 = 0b011010, // Center frequency +1.222% (=8.09776 MHz)
652 OSCTUN_TUN_PLUS_27 = 0b011011, // Center frequency +1.269% (=8.10152 MHz)
653 OSCTUN_TUN_PLUS_28 = 0b011100, // Center frequency +1.316% (=8.10528 MHz)
654 OSCTUN_TUN_PLUS_29 = 0b011101, // Center frequency +1.363% (=8.10904 MHz)
655 OSCTUN_TUN_PLUS_30 = 0b011110, // Center frequency +1.41% (=8.1128 MHz)
656 OSCTUN_TUN_PLUS_31 = 0b011111 // Center frequency +1.457% (=8.11656 MHz)
657 };
658 typedef enum OSCTUN_TUN_e OSCTUN_TUN_t; // FRC Oscillator Tuning bits
659
660 #else
661 #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
662 #endif
663
664 struct OSCTUN_s{
665 union {
666 struct {
667 volatile enum OSCTUN_TUN_e TUN : 6; // FRC Oscillator Tuning bits
668 volatile unsigned : 10; // reserved
669 } __attribute__((packed)) bits;
670 volatile uint16_t value;
671 };
672 };
673 typedef struct OSCTUN_s OSCTUN_t;
674
675 /* ===========================================================================
676 * PLLDIV: PLL OUTPUT DIVIDER REGISTER
677 * ===========================================================================*/
678
679 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
680
681 #define REG_PLLDIV_VALID_DATA_WRITE_MASK 0x0377
682 #define REG_PLLDIV_VALID_DATA_READ_MASK 0x0377
683
684 #define REG_PLLDIV_POST1DIV_N2_MASK 0b0000000001110000
685 #define REG_PLLDIV_POST1DIV_N2(x) {((x << 4) & REG_PLLDIV_POST1DIV_N2_MASK)}
686
687 #define REG_PLLDIV_POST2DIV_N3_MASK 0b0000000000000111
688 #define REG_PLLDIV_POST2DIV_N3(x) {(x & REG_PLLDIV_POST1DIV_N3_MASK)}
689
690 enum PLLDIV_POSTxDIV_e {
691 PLLDIV_POST2DIV_N2N3_1 = 0b001, // PLL Output Divider Ratio bits 1:1
692 PLLDIV_POST2DIV_N2N3_2 = 0b010, // PLL Output Divider Ratio bits 1:2
693 PLLDIV_POST2DIV_N2N3_3 = 0b011, // PLL Output Divider Ratio bits 1:3
694 PLLDIV_POST2DIV_N2N3_4 = 0b100, // PLL Output Divider Ratio bits 1:4
695 PLLDIV_POST2DIV_N2N3_5 = 0b101, // PLL Output Divider Ratio bits 1:5
696 PLLDIV_POST2DIV_N2N3_6 = 0b110, // PLL Output Divider Ratio bits 1:6
697 PLLDIV_POST2DIV_N2N3_7 = 0b111 // PLL Output Divider Ratio bits 1:7
698 }; // PLL Output Divider Ratio bits (also denoted as ?N2? and ?N3?, PLL divider)
699 typedef enum PLLDIV_POSTxDIV_e PLLDIV_POSTxDIV_t; // PLL Output Divider Ratio bits (also denoted as ?N2? and ?N3?, PLL divider) data type
700
701 #define REG_PLLDIV_VCODIV_FVCO_DIV_BY_1 0b0000001100000000
702 #define REG_PLLDIV_VCODIV_FVCO_DIV_BY_2 0b0000001000000000
703 #define REG_PLLDIV_VCODIV_FVCO_DIV_BY_3 0b0000000100000000
704 #define REG_PLLDIV_VCODIV_FVCO_DIV_BY_4 0b0000000000000000
705
706 enum PLLDIV_VCODIV_e{
707 PLLDIV_VCODIV_FVCO_DIV_BY_1 = 0b11, // PLL VCO Output Divider 1:1
708 PLLDIV_VCODIV_FVCO_DIV_BY_2 = 0b10, // PLL VCO Output Divider 1:2
709 PLLDIV_VCODIV_FVCO_DIV_BY_3 = 0b01, // PLL VCO Output Divider 1:3
710 PLLDIV_VCODIV_FVCO_DIV_BY_4 = 0b00 // PLL VCO Output Divider 1:4
711 }; // PLL VCO Output Divider Select bits
712 typedef enum PLLDIV_VCODIV_e PLLDIV_VCODIV_t; // PLL VCO Output Divider Select bits data type
713
714 struct PLLDIV_s {
715 union {
716 struct {
717 volatile enum PLLDIV_POSTxDIV_e POST2DIV : 3;
718 volatile unsigned : 1;
719 volatile enum PLLDIV_POSTxDIV_e POST1DIV : 3;
720 volatile unsigned : 1;
721 volatile enum PLLDIV_VCODIV_e VCODIV : 2;
722 volatile unsigned : 6;
723 } __attribute__((packed)) bits;
724 volatile uint16_t value;
725 };
726 };
727 typedef struct PLLDIV_s PLLDIV_t;
728
729 #endif
730
731
732 /* ===========================================================================
733 * ACLKCON1: AUXILIARY CLOCK CONTROL REGISTER
734 * ===========================================================================*/
735
736 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
737
738 #define REG_ACLKCON_VALID_DATA_WRITE_MASK 0xC10F
739 #define REG_ACLKCON_VALID_DATA_READ_MASK 0xC10F
740
741 #define REG_ACLKCON_APLLPRE_DIV_MASK 0b0000000000001111
742 #define REG_ACLKCON_APLLPRE_DIVIDER_N1(x) {(x & REG_ACLKCON_APLLPRE_DIV_MASK)}
743
744 enum ACLKCON_APLLPRE_e {
745 ACLKCON_APLLDIV_N1_1 = 0b000001, // APLL Input Clock Divider Setting 1:1
746 ACLKCON_APLLDIV_N1_2 = 0b000010, // APLL Input Clock Divider Setting 1:2
747 ACLKCON_APLLDIV_N1_3 = 0b000011, // APLL Input Clock Divider Setting 1:3
748 ACLKCON_APLLDIV_N1_4 = 0b000100, // APLL Input Clock Divider Setting 1:4
749 ACLKCON_APLLDIV_N1_5 = 0b000101, // APLL Input Clock Divider Setting 1:5
750 ACLKCON_APLLDIV_N1_6 = 0b000110, // APLL Input Clock Divider Setting 1:6
751 ACLKCON_APLLDIV_N1_7 = 0b000111, // APLL Input Clock Divider Setting 1:7
752 ACLKCON_APLLDIV_N1_8 = 0b001000 // APLL Input Clock Divider Setting 1:8
753 }; // PLL Phase Detector Input Divider Select bits (also denoted as ?N1?, PLL prescaler)
754 typedef enum ACLKCON_APLLPRE_e ACLKCON_APLLPRE_t; // PLL Phase Detector Input Divider Select bits (also denoted as ?N1?, PLL prescaler) data type
755
756 #define REG_ACLKCON_FRCSEL_FRC 0b0000000100000000
757 #define REG_ACLKCON_FRCSEL_PRI 0b0000000000000000
758
759 enum ACLKCON_FRCSEL_e{
760 PLLDIV_ACLKCON_FRCSEL_FRC = 0b1, // FRC is the clock source for APLL
761 PLLDIV_ACLKCON_FRCSEL_PRI = 0b0 // Primary Oscillator is the clock source for APLL
762 }; // APLL Clock Source Select bit
763 typedef enum ACLKCON_FRCSEL_e ACLKCON_FRCSEL_t; // APLL Clock Source Select bit data type
764
765 #define REG_ACLKCON_APLLCK_STAT_LOCKED 0b0100000000000000
766 #define REG_ACLKCON_APLLCK_STAT_UNLOCKED 0b0000000000000000
767
768 enum ACLKCON_APLLCK_e {
769 ACLKCON_APLLCK_STAT_LOCKED = 0b1, // APLL Phase-Locked State Status bit
770 ACLKCON_APLLCK_STAT_UNLOCKED = 0b0 // Auxiliary PLL is not in lock
771 }; // APLL Phase-Locked State Status bit
772 typedef enum ACLKCON_APLLCK_e ACLKCON_APLLCK_t; // APLL Phase-Locked State Status bit data type
773
774 #define REG_ACLKCON_APLLEN_ENABLED 0b1000000000000000
775 #define REG_ACLKCON_APLLEN_DISABLED 0b0000000000000000
776
777 enum ACLKCON_APLLEN_e {
778 ACLKCON_APLLEN_ENABLED = 0b1, // AFPLLO is connected to the APLL post-divider output (bypass disabled)
779 ACLKCON_APLLEN_DISABLED = 0b0 // AFPLLO is connected to the APLL input clock (bypass enabled)
780 }; // Auxiliary PLL Enable/Bypass select bit
781 typedef enum ACLKCON_APLLEN_e ACLKCON_APLLEN_t; // Auxiliary PLL Enable/Bypass select bit data type
782
783 struct ACLKCON_s {
784 union {
785 struct {
786 volatile enum ACLKCON_APLLPRE_e APLLPRE : 6;
787 volatile unsigned : 2;
788 volatile enum ACLKCON_FRCSEL_e FRCSEL : 1;
789 volatile unsigned : 5;
790 volatile enum ACLKCON_APLLCK_e APLLCK : 1;
791 volatile enum ACLKCON_APLLEN_e APLLEN : 1;
792 } __attribute__((packed)) bits;
793 volatile uint16_t value;
794 };
795 };
796 typedef struct ACLKCON_s ACLKCON_t;
797
798 #else
799 #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
800 #endif
801
802 /* ===========================================================================
803 * APLLFBD1: APLL FEEDBACK DIVIDER REGISTER
804 * ===========================================================================*/
805
806 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
807
808 #define REG_APLLFBD_VALID_DATA_WRITE_MASK 0x00FF
809 #define REG_APLLFBD_VALID_DATA_READ_MASK 0x00FF
810
811 #define REG_APLLFBD_APLLFBDIV_M_MASK 0b0000000011111111
812 #define REG_APLLFBD_MULTIPLIER_M(x) {(x & REG_APLLFBD_APLLFBDIV_M_MASK)}
813
814 enum APLLFBD_APLLFBDIV_e {
815 APLLFBD_APLLFBDIV_M_16 = 0b00010000, // APLL Input Clock Multiplier Setting x16
816 APLLFBD_APLLFBDIV_M_17 = 0b00010001, // APLL Input Clock Multiplier Setting x17
817 APLLFBD_APLLFBDIV_M_18 = 0b00010010, // APLL Input Clock Multiplier Setting x18
818 APLLFBD_APLLFBDIV_M_19 = 0b00010011, // APLL Input Clock Multiplier Setting x19
819 APLLFBD_APLLFBDIV_M_20 = 0b00010100, // APLL Input Clock Multiplier Setting x20
820 APLLFBD_APLLFBDIV_M_21 = 0b00010101, // APLL Input Clock Multiplier Setting x21
821 APLLFBD_APLLFBDIV_M_22 = 0b00010110, // APLL Input Clock Multiplier Setting x22
822 APLLFBD_APLLFBDIV_M_23 = 0b00010111, // APLL Input Clock Multiplier Setting x23
823 APLLFBD_APLLFBDIV_M_24 = 0b00011000, // APLL Input Clock Multiplier Setting x24
824 APLLFBD_APLLFBDIV_M_25 = 0b00011001, // APLL Input Clock Multiplier Setting x25
825 APLLFBD_APLLFBDIV_M_26 = 0b00011010, // APLL Input Clock Multiplier Setting x26
826 APLLFBD_APLLFBDIV_M_27 = 0b00011011, // APLL Input Clock Multiplier Setting x27
827 APLLFBD_APLLFBDIV_M_28 = 0b00011100, // APLL Input Clock Multiplier Setting x28
828 APLLFBD_APLLFBDIV_M_29 = 0b00011101, // APLL Input Clock Multiplier Setting x29
829 APLLFBD_APLLFBDIV_M_30 = 0b00011110, // APLL Input Clock Multiplier Setting x30
830 APLLFBD_APLLFBDIV_M_31 = 0b00011111, // APLL Input Clock Multiplier Setting x31
831 APLLFBD_APLLFBDIV_M_32 = 0b00100000, // APLL Input Clock Multiplier Setting x32
832 APLLFBD_APLLFBDIV_M_33 = 0b00100001, // APLL Input Clock Multiplier Setting x33
833 APLLFBD_APLLFBDIV_M_34 = 0b00100010, // APLL Input Clock Multiplier Setting x34
834 APLLFBD_APLLFBDIV_M_35 = 0b00100011, // APLL Input Clock Multiplier Setting x35
835 APLLFBD_APLLFBDIV_M_36 = 0b00100100, // APLL Input Clock Multiplier Setting x36
836 APLLFBD_APLLFBDIV_M_37 = 0b00100101, // APLL Input Clock Multiplier Setting x37
837 APLLFBD_APLLFBDIV_M_38 = 0b00100110, // APLL Input Clock Multiplier Setting x38
838 APLLFBD_APLLFBDIV_M_39 = 0b00100111, // APLL Input Clock Multiplier Setting x39
839 APLLFBD_APLLFBDIV_M_40 = 0b00101000, // APLL Input Clock Multiplier Setting x40
840 APLLFBD_APLLFBDIV_M_41 = 0b00101001, // APLL Input Clock Multiplier Setting x41
841 APLLFBD_APLLFBDIV_M_42 = 0b00101010, // APLL Input Clock Multiplier Setting x42
842 APLLFBD_APLLFBDIV_M_43 = 0b00101011, // APLL Input Clock Multiplier Setting x43
843 APLLFBD_APLLFBDIV_M_44 = 0b00101100, // APLL Input Clock Multiplier Setting x44
844 APLLFBD_APLLFBDIV_M_45 = 0b00101101, // APLL Input Clock Multiplier Setting x45
845 APLLFBD_APLLFBDIV_M_46 = 0b00101110, // APLL Input Clock Multiplier Setting x46
846 APLLFBD_APLLFBDIV_M_47 = 0b00101111, // APLL Input Clock Multiplier Setting x47
847 APLLFBD_APLLFBDIV_M_48 = 0b00110000, // APLL Input Clock Multiplier Setting x48
848 APLLFBD_APLLFBDIV_M_49 = 0b00110001, // APLL Input Clock Multiplier Setting x49
849 APLLFBD_APLLFBDIV_M_50 = 0b00110010, // APLL Input Clock Multiplier Setting x50
850 APLLFBD_APLLFBDIV_M_51 = 0b00110011, // APLL Input Clock Multiplier Setting x51
851 APLLFBD_APLLFBDIV_M_52 = 0b00110100, // APLL Input Clock Multiplier Setting x52
852 APLLFBD_APLLFBDIV_M_53 = 0b00110101, // APLL Input Clock Multiplier Setting x53
853 APLLFBD_APLLFBDIV_M_54 = 0b00110110, // APLL Input Clock Multiplier Setting x54
854 APLLFBD_APLLFBDIV_M_55 = 0b00110111, // APLL Input Clock Multiplier Setting x55
855 APLLFBD_APLLFBDIV_M_56 = 0b00111000, // APLL Input Clock Multiplier Setting x56
856 APLLFBD_APLLFBDIV_M_57 = 0b00111001, // APLL Input Clock Multiplier Setting x57
857 APLLFBD_APLLFBDIV_M_58 = 0b00111010, // APLL Input Clock Multiplier Setting x58
858 APLLFBD_APLLFBDIV_M_59 = 0b00111011, // APLL Input Clock Multiplier Setting x59
859 APLLFBD_APLLFBDIV_M_60 = 0b00111100, // APLL Input Clock Multiplier Setting x60
860 APLLFBD_APLLFBDIV_M_61 = 0b00111101, // APLL Input Clock Multiplier Setting x61
861 APLLFBD_APLLFBDIV_M_62 = 0b00111110, // APLL Input Clock Multiplier Setting x62
862 APLLFBD_APLLFBDIV_M_63 = 0b00111111, // APLL Input Clock Multiplier Setting x63
863 APLLFBD_APLLFBDIV_M_64 = 0b01000000, // APLL Input Clock Multiplier Setting x64
864 APLLFBD_APLLFBDIV_M_65 = 0b01000001, // APLL Input Clock Multiplier Setting x65
865 APLLFBD_APLLFBDIV_M_66 = 0b01000010, // APLL Input Clock Multiplier Setting x66
866 APLLFBD_APLLFBDIV_M_67 = 0b01000011, // APLL Input Clock Multiplier Setting x67
867 APLLFBD_APLLFBDIV_M_68 = 0b01000100, // APLL Input Clock Multiplier Setting x68
868 APLLFBD_APLLFBDIV_M_69 = 0b01000101, // APLL Input Clock Multiplier Setting x69
869 APLLFBD_APLLFBDIV_M_70 = 0b01000110, // APLL Input Clock Multiplier Setting x70
870 APLLFBD_APLLFBDIV_M_71 = 0b01000111, // APLL Input Clock Multiplier Setting x71
871 APLLFBD_APLLFBDIV_M_72 = 0b01001000, // APLL Input Clock Multiplier Setting x72
872 APLLFBD_APLLFBDIV_M_73 = 0b01001001, // APLL Input Clock Multiplier Setting x73
873 APLLFBD_APLLFBDIV_M_74 = 0b01001010, // APLL Input Clock Multiplier Setting x74
874 APLLFBD_APLLFBDIV_M_75 = 0b01001011, // APLL Input Clock Multiplier Setting x75
875 APLLFBD_APLLFBDIV_M_76 = 0b01001100, // APLL Input Clock Multiplier Setting x76
876 APLLFBD_APLLFBDIV_M_77 = 0b01001101, // APLL Input Clock Multiplier Setting x77
877 APLLFBD_APLLFBDIV_M_78 = 0b01001110, // APLL Input Clock Multiplier Setting x78
878 APLLFBD_APLLFBDIV_M_79 = 0b01001111, // APLL Input Clock Multiplier Setting x79
879 APLLFBD_APLLFBDIV_M_80 = 0b01010000, // APLL Input Clock Multiplier Setting x80
880 APLLFBD_APLLFBDIV_M_81 = 0b01010001, // APLL Input Clock Multiplier Setting x81
881 APLLFBD_APLLFBDIV_M_82 = 0b01010010, // APLL Input Clock Multiplier Setting x82
882 APLLFBD_APLLFBDIV_M_83 = 0b01010011, // APLL Input Clock Multiplier Setting x83
883 APLLFBD_APLLFBDIV_M_84 = 0b01010100, // APLL Input Clock Multiplier Setting x84
884 APLLFBD_APLLFBDIV_M_85 = 0b01010101, // APLL Input Clock Multiplier Setting x85
885 APLLFBD_APLLFBDIV_M_86 = 0b01010110, // APLL Input Clock Multiplier Setting x86
886 APLLFBD_APLLFBDIV_M_87 = 0b01010111, // APLL Input Clock Multiplier Setting x87
887 APLLFBD_APLLFBDIV_M_88 = 0b01011000, // APLL Input Clock Multiplier Setting x88
888 APLLFBD_APLLFBDIV_M_89 = 0b01011001, // APLL Input Clock Multiplier Setting x89
889 APLLFBD_APLLFBDIV_M_90 = 0b01011010, // APLL Input Clock Multiplier Setting x90
890 APLLFBD_APLLFBDIV_M_91 = 0b01011011, // APLL Input Clock Multiplier Setting x91
891 APLLFBD_APLLFBDIV_M_92 = 0b01011100, // APLL Input Clock Multiplier Setting x92
892 APLLFBD_APLLFBDIV_M_93 = 0b01011101, // APLL Input Clock Multiplier Setting x93
893 APLLFBD_APLLFBDIV_M_94 = 0b01011110, // APLL Input Clock Multiplier Setting x94
894 APLLFBD_APLLFBDIV_M_95 = 0b01011111, // APLL Input Clock Multiplier Setting x95
895 APLLFBD_APLLFBDIV_M_96 = 0b01100000, // APLL Input Clock Multiplier Setting x96
896 APLLFBD_APLLFBDIV_M_97 = 0b01100001, // APLL Input Clock Multiplier Setting x97
897 APLLFBD_APLLFBDIV_M_98 = 0b01100010, // APLL Input Clock Multiplier Setting x98
898 APLLFBD_APLLFBDIV_M_99 = 0b01100011, // APLL Input Clock Multiplier Setting x99
899 APLLFBD_APLLFBDIV_M_100 = 0b01100100, // APLL Input Clock Multiplier Setting x100
900 APLLFBD_APLLFBDIV_M_101 = 0b01100101, // APLL Input Clock Multiplier Setting x101
901 APLLFBD_APLLFBDIV_M_102 = 0b01100110, // APLL Input Clock Multiplier Setting x102
902 APLLFBD_APLLFBDIV_M_103 = 0b01100111, // APLL Input Clock Multiplier Setting x103
903 APLLFBD_APLLFBDIV_M_104 = 0b01101000, // APLL Input Clock Multiplier Setting x104
904 APLLFBD_APLLFBDIV_M_105 = 0b01101001, // APLL Input Clock Multiplier Setting x105
905 APLLFBD_APLLFBDIV_M_106 = 0b01101010, // APLL Input Clock Multiplier Setting x106
906 APLLFBD_APLLFBDIV_M_107 = 0b01101011, // APLL Input Clock Multiplier Setting x107
907 APLLFBD_APLLFBDIV_M_108 = 0b01101100, // APLL Input Clock Multiplier Setting x108
908 APLLFBD_APLLFBDIV_M_109 = 0b01101101, // APLL Input Clock Multiplier Setting x109
909 APLLFBD_APLLFBDIV_M_110 = 0b01101110, // APLL Input Clock Multiplier Setting x110
910 APLLFBD_APLLFBDIV_M_111 = 0b01101111, // APLL Input Clock Multiplier Setting x111
911 APLLFBD_APLLFBDIV_M_112 = 0b01110000, // APLL Input Clock Multiplier Setting x112
912 APLLFBD_APLLFBDIV_M_113 = 0b01110001, // APLL Input Clock Multiplier Setting x113
913 APLLFBD_APLLFBDIV_M_114 = 0b01110010, // APLL Input Clock Multiplier Setting x114
914 APLLFBD_APLLFBDIV_M_115 = 0b01110011, // APLL Input Clock Multiplier Setting x115
915 APLLFBD_APLLFBDIV_M_116 = 0b01110100, // APLL Input Clock Multiplier Setting x116
916 APLLFBD_APLLFBDIV_M_117 = 0b01110101, // APLL Input Clock Multiplier Setting x117
917 APLLFBD_APLLFBDIV_M_118 = 0b01110110, // APLL Input Clock Multiplier Setting x118
918 APLLFBD_APLLFBDIV_M_119 = 0b01110111, // APLL Input Clock Multiplier Setting x119
919 APLLFBD_APLLFBDIV_M_120 = 0b01111000, // APLL Input Clock Multiplier Setting x120
920 APLLFBD_APLLFBDIV_M_121 = 0b01111001, // APLL Input Clock Multiplier Setting x121
921 APLLFBD_APLLFBDIV_M_122 = 0b01111010, // APLL Input Clock Multiplier Setting x122
922 APLLFBD_APLLFBDIV_M_123 = 0b01111011, // APLL Input Clock Multiplier Setting x123
923 APLLFBD_APLLFBDIV_M_124 = 0b01111100, // APLL Input Clock Multiplier Setting x124
924 APLLFBD_APLLFBDIV_M_125 = 0b01111101, // APLL Input Clock Multiplier Setting x125
925 APLLFBD_APLLFBDIV_M_126 = 0b01111110, // APLL Input Clock Multiplier Setting x126
926 APLLFBD_APLLFBDIV_M_127 = 0b01111111, // APLL Input Clock Multiplier Setting x127
927 APLLFBD_APLLFBDIV_M_128 = 0b10000000, // APLL Input Clock Multiplier Setting x128
928 APLLFBD_APLLFBDIV_M_129 = 0b10000001, // APLL Input Clock Multiplier Setting x129
929 APLLFBD_APLLFBDIV_M_130 = 0b10000010, // APLL Input Clock Multiplier Setting x130
930 APLLFBD_APLLFBDIV_M_131 = 0b10000011, // APLL Input Clock Multiplier Setting x131
931 APLLFBD_APLLFBDIV_M_132 = 0b10000100, // APLL Input Clock Multiplier Setting x132
932 APLLFBD_APLLFBDIV_M_133 = 0b10000101, // APLL Input Clock Multiplier Setting x133
933 APLLFBD_APLLFBDIV_M_134 = 0b10000110, // APLL Input Clock Multiplier Setting x134
934 APLLFBD_APLLFBDIV_M_135 = 0b10000111, // APLL Input Clock Multiplier Setting x135
935 APLLFBD_APLLFBDIV_M_136 = 0b10001000, // APLL Input Clock Multiplier Setting x136
936 APLLFBD_APLLFBDIV_M_137 = 0b10001001, // APLL Input Clock Multiplier Setting x137
937 APLLFBD_APLLFBDIV_M_138 = 0b10001010, // APLL Input Clock Multiplier Setting x138
938 APLLFBD_APLLFBDIV_M_139 = 0b10001011, // APLL Input Clock Multiplier Setting x139
939 APLLFBD_APLLFBDIV_M_140 = 0b10001100, // APLL Input Clock Multiplier Setting x140
940 APLLFBD_APLLFBDIV_M_141 = 0b10001101, // APLL Input Clock Multiplier Setting x141
941 APLLFBD_APLLFBDIV_M_142 = 0b10001110, // APLL Input Clock Multiplier Setting x142
942 APLLFBD_APLLFBDIV_M_143 = 0b10001111, // APLL Input Clock Multiplier Setting x143
943 APLLFBD_APLLFBDIV_M_144 = 0b10010000, // APLL Input Clock Multiplier Setting x144
944 APLLFBD_APLLFBDIV_M_145 = 0b10010001, // APLL Input Clock Multiplier Setting x145
945 APLLFBD_APLLFBDIV_M_146 = 0b10010010, // APLL Input Clock Multiplier Setting x146
946 APLLFBD_APLLFBDIV_M_147 = 0b10010011, // APLL Input Clock Multiplier Setting x147
947 APLLFBD_APLLFBDIV_M_148 = 0b10010100, // APLL Input Clock Multiplier Setting x148
948 APLLFBD_APLLFBDIV_M_149 = 0b10010101, // APLL Input Clock Multiplier Setting x149
949 APLLFBD_APLLFBDIV_M_150 = 0b10010110, // APLL Input Clock Multiplier Setting x150
950 APLLFBD_APLLFBDIV_M_151 = 0b10010111, // APLL Input Clock Multiplier Setting x151
951 APLLFBD_APLLFBDIV_M_152 = 0b10011000, // APLL Input Clock Multiplier Setting x152
952 APLLFBD_APLLFBDIV_M_153 = 0b10011001, // APLL Input Clock Multiplier Setting x153
953 APLLFBD_APLLFBDIV_M_154 = 0b10011010, // APLL Input Clock Multiplier Setting x154
954 APLLFBD_APLLFBDIV_M_155 = 0b10011011, // APLL Input Clock Multiplier Setting x155
955 APLLFBD_APLLFBDIV_M_156 = 0b10011100, // APLL Input Clock Multiplier Setting x156
956 APLLFBD_APLLFBDIV_M_157 = 0b10011101, // APLL Input Clock Multiplier Setting x157
957 APLLFBD_APLLFBDIV_M_158 = 0b10011110, // APLL Input Clock Multiplier Setting x158
958 APLLFBD_APLLFBDIV_M_159 = 0b10011111, // APLL Input Clock Multiplier Setting x159
959 APLLFBD_APLLFBDIV_M_160 = 0b10100000, // APLL Input Clock Multiplier Setting x160
960 APLLFBD_APLLFBDIV_M_161 = 0b10100001, // APLL Input Clock Multiplier Setting x161
961 APLLFBD_APLLFBDIV_M_162 = 0b10100010, // APLL Input Clock Multiplier Setting x162
962 APLLFBD_APLLFBDIV_M_163 = 0b10100011, // APLL Input Clock Multiplier Setting x163
963 APLLFBD_APLLFBDIV_M_164 = 0b10100100, // APLL Input Clock Multiplier Setting x164
964 APLLFBD_APLLFBDIV_M_165 = 0b10100101, // APLL Input Clock Multiplier Setting x165
965 APLLFBD_APLLFBDIV_M_166 = 0b10100110, // APLL Input Clock Multiplier Setting x166
966 APLLFBD_APLLFBDIV_M_167 = 0b10100111, // APLL Input Clock Multiplier Setting x167
967 APLLFBD_APLLFBDIV_M_168 = 0b10101000, // APLL Input Clock Multiplier Setting x168
968 APLLFBD_APLLFBDIV_M_169 = 0b10101001, // APLL Input Clock Multiplier Setting x169
969 APLLFBD_APLLFBDIV_M_170 = 0b10101010, // APLL Input Clock Multiplier Setting x170
970 APLLFBD_APLLFBDIV_M_171 = 0b10101011, // APLL Input Clock Multiplier Setting x171
971 APLLFBD_APLLFBDIV_M_172 = 0b10101100, // APLL Input Clock Multiplier Setting x172
972 APLLFBD_APLLFBDIV_M_173 = 0b10101101, // APLL Input Clock Multiplier Setting x173
973 APLLFBD_APLLFBDIV_M_174 = 0b10101110, // APLL Input Clock Multiplier Setting x174
974 APLLFBD_APLLFBDIV_M_175 = 0b10101111, // APLL Input Clock Multiplier Setting x175
975 APLLFBD_APLLFBDIV_M_176 = 0b10110000, // APLL Input Clock Multiplier Setting x176
976 APLLFBD_APLLFBDIV_M_177 = 0b10110001, // APLL Input Clock Multiplier Setting x177
977 APLLFBD_APLLFBDIV_M_178 = 0b10110010, // APLL Input Clock Multiplier Setting x178
978 APLLFBD_APLLFBDIV_M_179 = 0b10110011, // APLL Input Clock Multiplier Setting x179
979 APLLFBD_APLLFBDIV_M_180 = 0b10110100, // APLL Input Clock Multiplier Setting x180
980 APLLFBD_APLLFBDIV_M_181 = 0b10110101, // APLL Input Clock Multiplier Setting x181
981 APLLFBD_APLLFBDIV_M_182 = 0b10110110, // APLL Input Clock Multiplier Setting x182
982 APLLFBD_APLLFBDIV_M_183 = 0b10110111, // APLL Input Clock Multiplier Setting x183
983 APLLFBD_APLLFBDIV_M_184 = 0b10111000, // APLL Input Clock Multiplier Setting x184
984 APLLFBD_APLLFBDIV_M_185 = 0b10111001, // APLL Input Clock Multiplier Setting x185
985 APLLFBD_APLLFBDIV_M_186 = 0b10111010, // APLL Input Clock Multiplier Setting x186
986 APLLFBD_APLLFBDIV_M_187 = 0b10111011, // APLL Input Clock Multiplier Setting x187
987 APLLFBD_APLLFBDIV_M_188 = 0b10111100, // APLL Input Clock Multiplier Setting x188
988 APLLFBD_APLLFBDIV_M_189 = 0b10111101, // APLL Input Clock Multiplier Setting x189
989 APLLFBD_APLLFBDIV_M_190 = 0b10111110, // APLL Input Clock Multiplier Setting x190
990 APLLFBD_APLLFBDIV_M_191 = 0b10111111, // APLL Input Clock Multiplier Setting x191
991 APLLFBD_APLLFBDIV_M_192 = 0b11000000, // APLL Input Clock Multiplier Setting x192
992 APLLFBD_APLLFBDIV_M_193 = 0b11000001, // APLL Input Clock Multiplier Setting x193
993 APLLFBD_APLLFBDIV_M_194 = 0b11000010, // APLL Input Clock Multiplier Setting x194
994 APLLFBD_APLLFBDIV_M_195 = 0b11000011, // APLL Input Clock Multiplier Setting x195
995 APLLFBD_APLLFBDIV_M_196 = 0b11000100, // APLL Input Clock Multiplier Setting x196
996 APLLFBD_APLLFBDIV_M_197 = 0b11000101, // APLL Input Clock Multiplier Setting x197
997 APLLFBD_APLLFBDIV_M_198 = 0b11000110, // APLL Input Clock Multiplier Setting x198
998 APLLFBD_APLLFBDIV_M_199 = 0b11000111, // APLL Input Clock Multiplier Setting x199
999 APLLFBD_APLLFBDIV_M_200 = 0b11001000 // APLL Input Clock Multiplier Setting x200
1000 };
1001 typedef enum APLLFBD_APLLFBDIV_e APLLFBD_APLLFBDIV_t; // APLL Feedback Divider bits (also denoted as ?M?, PLL multiplier)
1002
1003 struct APLLFBD_s {
1004 union {
1005 struct {
1006 volatile enum APLLFBD_APLLFBDIV_e APLLFBDIV : 8; // APLL Feedback Divider bits (also denoted as ?M?, PLL multiplier)
1007 volatile unsigned : 8; // reserved
1008 } __attribute__((packed)) bits;
1009 volatile uint16_t value;
1010 };
1011 };
1012 typedef struct APLLFBD_s APLLFBD_t; // APLL Feedback Divider bits
1013
1014 #else
1015 #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
1016 #endif
1017
1018 /* ===========================================================================
1019 * APLLDIV1: APLL OUTPUT DIVIDER REGISTER
1020 * ===========================================================================*/
1021
1022 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
1023
1024 #define REG_APLLDIV_VALID_DATA_WRITE_MASK 0x0377
1025 #define REG_APLLDIV_VALID_DATA_READ_MASK 0x0377
1026
1027 #define REG_APLLDIV_POST1DIV_N2_MASK 0b0000000001110000
1028 #define REG_APLLDIV_POST1DIV_N2(x) {((x << 4) & REG_APLLDIV_POST1DIV_N2_MASK)}
1029
1030 #define REG_APLLDIV_POST2DIV_N3_MASK 0b0000000000000111
1031 #define REG_APLLDIV_POST2DIV_N3(x) {(x & REG_APLLDIV_POST1DIV_N3_MASK)}
1032
1033 enum APLLDIV_POSTxDIV_e {
1034 APLLDIV_POST2DIV_N2N3_1 = 0b001, // PLL Output Divider Ratio bits 1:1
1035 APLLDIV_POST2DIV_N2N3_2 = 0b010, // PLL Output Divider Ratio bits 1:2
1036 APLLDIV_POST2DIV_N2N3_3 = 0b011, // PLL Output Divider Ratio bits 1:3
1037 APLLDIV_POST2DIV_N2N3_4 = 0b100, // PLL Output Divider Ratio bits 1:4
1038 APLLDIV_POST2DIV_N2N3_5 = 0b101, // PLL Output Divider Ratio bits 1:5
1039 APLLDIV_POST2DIV_N2N3_6 = 0b110, // PLL Output Divider Ratio bits 1:6
1040 APLLDIV_POST2DIV_N2N3_7 = 0b111 // PLL Output Divider Ratio bits 1:7
1041 }; // PLL Output Divider Ratio bits (also denoted as ?N2? and ?N3?, PLL divider)
1042 typedef enum APLLDIV_POSTxDIV_e APLLDIV_POSTxDIV_t; // PLL Output Divider Ratio bits (also denoted as ?N2? and ?N3?, PLL divider) data type
1043
1044 #define REG_APLLDIV_AVCODIV_FVCO_DIV_BY_1 0b0000001100000000
1045 #define REG_APLLDIV_AVCODIV_FVCO_DIV_BY_2 0b0000001000000000
1046 #define REG_APLLDIV_AVCODIV_FVCO_DIV_BY_3 0b0000000100000000
1047 #define REG_APLLDIV_AVCODIV_FVCO_DIV_BY_4 0b0000000000000000
1048
1049 enum APLLDIV_AVCODIV_e {
1050 APLLDIV_AVCODIV_FVCO_DIV_BY_1 = 0b11, // APLL AVCO Output Divider 1:1
1051 APLLDIV_AVCODIV_FVCO_DIV_BY_2 = 0b10, // APLL AVCO Output Divider 1:2
1052 APLLDIV_AVCODIV_FVCO_DIV_BY_3 = 0b01, // APLL AVCO Output Divider 1:3
1053 APLLDIV_AVCODIV_FVCO_DIV_BY_4 = 0b00 // APLL AVCO Output Divider 1:4
1054 }; // APLL AVCO Output Divider Select bits
1055 typedef enum APLLDIV_AVCODIV_e APLLDIV_AVCODIV_t; // APLL AVCO Output Divider Select bits data type
1056
1057 struct APLLDIV_s {
1058 union {
1059 struct {
1060 volatile enum APLLDIV_POSTxDIV_e APOST2DIV : 3;
1061 volatile unsigned : 1;
1062 volatile enum APLLDIV_POSTxDIV_e APOST1DIV : 3;
1063 volatile unsigned : 1;
1064 volatile enum APLLDIV_AVCODIV_e AVCODIV : 2;
1065 volatile unsigned : 6;
1066 } __attribute__((packed)) bits;
1067 volatile uint16_t value;
1068 };
1069 }; // APLL Output Divider Select bits
1070 typedef struct APLLDIV_s APLLDIV_t; // APLL Output Divider Select bits data type
1071
1072 #else
1073 #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
1074 #endif
1075
1076 /* ===========================================================================
1077 * OSCILLATOR CONFIGURATION OBJECT
1078 * ===========================================================================*/
1079
1080 #if defined (__P33SMPS_CH__) || defined (__P33SMPS_CK__)
1081
1082 struct OSC_CONFIG_s {
1083 volatile enum OSCCON_xOSC_TYPE_e osc_type;
1084 volatile enum CLKDIV_FRCDIVN_e frc_div;
1085 volatile enum OSCTUN_TUN_e frc_tune;
1086 volatile enum CLKDIV_PLLPRE_e N1;
1087 volatile enum PLLFBD_PLLFBDIV_e M;
1088 volatile enum PLLDIV_POSTxDIV_e N2;
1089 volatile enum PLLDIV_POSTxDIV_e N3;
1090 volatile enum PLLDIV_VCODIV_e VCODIV;
1091 };
1092 typedef struct OSC_CONFIG_s OSC_CONFIG_t;
1093
1094 struct AUXOSC_CONFIG_s {
1095 volatile enum ACLKCON_APLLPRE_e N1;
1096 volatile enum APLLFBD_APLLFBDIV_e M;
1097 volatile enum APLLDIV_POSTxDIV_e N2;
1098 volatile enum APLLDIV_POSTxDIV_e N3;
1099 volatile enum APLLDIV_AVCODIV_e AVCODIV;
1100 volatile enum ACLKCON_FRCSEL_e FRCSEL : 1;
1101 volatile enum ACLKCON_APLLCK_e APLLCK : 1;
1102 volatile enum ACLKCON_APLLEN_e APLLEN : 1;
1103 };
1104 typedef struct AUXOSC_CONFIG_s AUXOSC_CONFIG_t;
1105
1106 #else
1107 #pragma message "error: === selected device family is not supported by oscillator mcal library ==="
1108 #endif
1109
1110
1111 /* ***************************************************************************************
1112 * ERROR CODES
1113 * **************************************************************************************/
1114
1115 enum OSC_CFG_ERR_RESULT_e {
1116 OSCERR_FAILURE = 0x0000, // Global Clock Error
1117 OSCERR_SUCCESS = 0x0001, // Clock initialization was successfully performed
1118 OSCERR_CSF = 0x0002, // Clock switch-over failed
1119 OSCERR_RST = 0x0004, // Clock switch-over failed
1120 OSCERR_CSD = 0x0008, // Clock switching is disabled but desired clock differs from current clock
1121 OSCERR_PLL_LCK = 0x0010, // Primary PLL does not lock in
1122 OSCERR_APLL_LCK = 0x0020, // Auxiliary PLL does not lock in
1123 };
1124 typedef enum OSC_CFG_ERR_RESULT_e OSC_CFG_ERR_RESULT_t;
1125
1126
1127 /****************************************************************************************
1128 * GLOBAL VARIABLES AND DATA OBJECTS
1129 ***************************************************************************************/
1130
1131 extern volatile struct OSCILLATOR_SYSTEM_FREQUENCIES_s SystemFrequencies; // Global data object of type OSCILLATOR_SYSTEM_FREQUENCIES_t
1132
1133 /****************************************************************************************
1134 * GLOBAL FUNCTION CALL PROTOTYPES
1135 ***************************************************************************************/
1136
1137 extern volatile uint16_t p33c_Osc_Initialize(volatile struct OSC_CONFIG_s osc_config);
1138 extern volatile uint16_t p33c_OscFrc_Initialize(volatile enum CLKDIV_FRCDIVN_e frc_div, volatile enum OSCTUN_TUN_e frc_tun);
1139 extern volatile uint16_t p33c_OscAuxClk_Initialize(volatile struct AUXOSC_CONFIG_s aux_clock_config);
1140
1141 extern volatile uint16_t p33c_OscFrc_DefaultInitialize(volatile enum CPU_SPEED_DEFAULTS_e cpu_speed);
1142 extern volatile uint16_t p33c_OscAuxClk_DefaultInitialize(volatile enum AUX_PLL_DEFAULTS_e afpllo_frequency);
1143
1144 extern volatile uint16_t p33c_Osc_SetExtFrequency(volatile int32_t ext_osc_frequency);
1145 extern volatile uint16_t p33c_Osc_GetFrequencies(void);
1146
1147 #endif /* MCAL_P33SMPS_OSCILLATOR_H */
OSCILLATOR_SYSTEM_FREQUENCIES_s::tcy
volatile float tcy
Definition: p33c_osc.h:134
OSCTUN_s::TUN
enum OSCTUN_TUN_e TUN
Definition: p33c_osc.h:667
OSCILLATOR_SYSTEM_FREQUENCIES_s
Definition: p33c_osc.h:124
CLKDIV_s::unsigned
volatile unsigned
Definition: p33c_osc.h:352
P33C_OSC_CONFIG_s::CF
enum OSCCON_CF_e CF
Definition: p33c_osc.h:244
CLKDIV_s::PLLPRE
enum CLKDIV_PLLPRE_e PLLPRE
Definition: p33c_osc.h:351
P33C_OSC_CONFIG_s::value
volatile uint16_t value
Definition: p33c_osc.h:254
CLKDIV_s::FRCDIV
enum CLKDIV_FRCDIVN_e FRCDIV
Definition: p33c_osc.h:353
OSCTUN_s::unsigned
volatile unsigned
Definition: p33c_osc.h:668
P33C_OSC_CONFIG_s::LOCK
enum OSCCON_LOCK_e LOCK
Definition: p33c_osc.h:246
OSCILLATOR_SYSTEM_FREQUENCIES_s::fvco
volatile uint32_t fvco
Definition: p33c_osc.h:132
OSCTUN_s
Definition: p33c_osc.h:664
OSCILLATOR_SYSTEM_FREQUENCIES_s::fosc
volatile uint32_t fosc
Definition: p33c_osc.h:128
P33C_OSC_CONFIG_s::CLKLOCK
enum OSCCON_CLKLOCK_e CLKLOCK
Definition: p33c_osc.h:248
CLKDIV_s::DOZE
enum CLKDIV_DOZE_e DOZE
Definition: p33c_osc.h:355
CLKDIV_s::value
volatile uint16_t value
Definition: p33c_osc.h:358
P33C_OSC_CONFIG_s::COSC
enum OSCCON_xOSC_TYPE_e COSC
Definition: p33c_osc.h:251
OSCILLATOR_SYSTEM_FREQUENCIES_s::fpri
volatile uint32_t fpri
Definition: p33c_osc.h:126
OSCILLATOR_SYSTEM_FREQUENCIES_s::fclk
volatile uint32_t fclk
Definition: p33c_osc.h:127
OSCILLATOR_SYSTEM_FREQUENCIES_s::fpllo
volatile uint32_t fpllo
Definition: p33c_osc.h:131
CLKDIV_s::ROI
enum CLKDIV_ROI_e ROI
Definition: p33c_osc.h:356
OSCILLATOR_SYSTEM_FREQUENCIES_s::fp
volatile uint32_t fp
Definition: p33c_osc.h:130
P33C_OSC_CONFIG_s::NOSC
enum OSCCON_xOSC_TYPE_e NOSC
Definition: p33c_osc.h:249
OSCILLATOR_SYSTEM_FREQUENCIES_s::fcy
volatile uint32_t fcy
Definition: p33c_osc.h:129
OSCILLATOR_SYSTEM_FREQUENCIES_s::afpllo
volatile uint32_t afpllo
Definition: p33c_osc.h:135
OSCILLATOR_SYSTEM_FREQUENCIES_s::tp
volatile float tp
Definition: p33c_osc.h:133
P33C_OSC_CONFIG_s::unsigned
volatile unsigned
Definition: p33c_osc.h:242
OSCTUN_s::value
volatile uint16_t value
Definition: p33c_osc.h:670
CLKDIV_s::DOZEN
enum CLKDIV_DOZEN_e DOZEN
Definition: p33c_osc.h:354
OSCILLATOR_SYSTEM_FREQUENCIES_s::afvco
volatile uint32_t afvco
Definition: p33c_osc.h:136
CLKDIV_s
Definition: p33c_osc.h:348
P33C_OSC_CONFIG_s::OSWEN
enum OSCCON_OSWEN_e OSWEN
Definition: p33c_osc.h:241
P33C_OSC_CONFIG_s
Definition: p33c_osc.h:238
OSCILLATOR_SYSTEM_FREQUENCIES_s::frc
volatile uint32_t frc
Definition: p33c_osc.h:125