### B.5  MMX INSTRUCTION FORMATS AND ENCODINGS


MMX instructions, except the EMMS instruction, use a format similar to the 2-byte Intel Architecture integer format. Details of subfield encodings within these formats are presented below.

### B.5.1   Granularity Field (gg)


The granularity field (gg) indicates the size of the packed operands that the instruction is operating on. When this field is used, it is located in bits 1 and 0 of the second opcode byte. Table B-18 shows the encoding of the gg field.

### Table B-18.  Encoding of Granularity of Data Field (gg)


|**gg**|**Granularity of Data**|
|------|-----------------------|
|00|Packed Bytes|
|01|Packed Words|
|10|Packed Doublewords|
|11|Quadword|
### B.5.2   MMX Technology and General-Purpose Register Fields (mmxreg and reg)


When MMX technology registers (mmxreg) are used as operands, they are encoded in the ModR/M byte in the reg field (bits 5, 4, and 3) and/or the R/M field (bits 2, 1, and 0).

If an MMX instruction operates on a general-purpose register (reg), the register is encoded in the R/M field of the ModR/M byte.

### B.5.3   MMX Instruction Formats and Encodings Table


Table B-19 shows the formats and encodings of the integer instructions.

### Table B-19.  MMX Instruction Formats and Encodings


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|**EMMS - Empty MMX technology state**|0000 1111:01110111|
|**MOVD - Move doubleword**||
|reg to mmxreg|0000 1111:0110 1110: 11 mmxreg reg|
|reg from mmxreg|0000 1111:0111 1110: 11 mmxreg reg|
|mem to mmxreg|0000 1111:0110 1110: mod mmxreg r/m|
|mem from mmxreg|0000 1111:0111 1110: mod mmxreg r/m|
|**MOVQ - Move quadword**||
|mmxreg2 to mmxreg1|0000 1111:0110 1111: 11 mmxreg1 mmxreg2|
|mmxreg2 from mmxreg1|0000 1111:0111 1111: 11 mmxreg1 mmxreg2|
|mem to mmxreg|0000 1111:0110 1111: mod mmxreg r/m|
### Table B-19.  MMX Instruction Formats and Encodings (Contd.)


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|mem from mmxreg|0000 1111:0111 1111: mod mmxreg r/m|
|**PACKSSDW\footnote{1}  - Pack dword to word data (signed with ****saturation)**||
|mmxreg2 to mmxreg1|0000 1111:0110 1011: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:0110 1011: mod mmxreg r/m|
|**PACKSSWB\footnote{1}  - Pack word to byte data (signed with ****saturation)**||
|mmxreg2 to mmxreg1|0000 1111:0110 0011: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:0110 0011: mod mmxreg r/m|
|**PACKUSWB\footnote{1}  - Pack word to byte data (unsigned with ****saturation)**||
|mmxreg2 to mmxreg1|0000 1111:0110 0111: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:0110 0111: mod mmxreg r/m|
|**PADD - Add with wrap-around**||
|mmxreg2 to mmxreg1|0000 1111: 1111 11gg: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111: 1111 11gg: mod mmxreg r/m|
|**PADDS - Add signed with saturation**||
|mmxreg2 to mmxreg1|0000 1111: 1110 11gg: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111: 1110 11gg: mod mmxreg r/m|
|**PADDUS - Add unsigned with saturation**||
|mmxreg2 to mmxreg1|0000 1111: 1101 11gg: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111: 1101 11gg: mod mmxreg r/m|
|**PAND - Bitwise And**||
|mmxreg2 to mmxreg1|0000 1111:1101 1011: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:1101 1011: mod mmxreg r/m|
|**PANDN - Bitwise AndNot**||
|mmxreg2 to mmxreg1|0000 1111:1101 1111: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:1101 1111: mod mmxreg r/m|
|**PCMPEQ - Packed compare for equality**||
| mmxreg1 with mmxreg2|0000 1111:0111 01gg: 11 mmxreg1 mmxreg2|
|  mmxreg with memory|0000 1111:0111 01gg: mod mmxreg r/m|
|**PCMPGT - Packed compare greater (signed)**||
|mmxreg1 with mmxreg2|0000 1111:0110 01gg: 11 mmxreg1 mmxreg2|
|mmxreg with memory|0000 1111:0110 01gg: mod mmxreg r/m|
|**PMADDWD - Packed multiply add**||
|mmxreg2 to mmxreg1|0000 1111:1111 0101: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:1111 0101: mod mmxreg r/m|
|**PMULHUW - Packed multiplication, store high word ****(unsigned)**||
|   mmxreg2 to mmxreg1|0000 1111: 1110 0100: 11 mmxreg1 mmxreg2|
### Table B-19.  MMX Instruction Formats and Encodings (Contd.)


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|   memory to mmxreg |0000 1111: 1110 0100: mod mmxreg r/m|
|**PMULHW - Packed multiplication, store high word**||
|mmxreg2 to mmxreg1|0000 1111:1110 0101: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:1110 0101: mod mmxreg r/m|
|**PMULLW - Packed multiplication, store low word**||
|mmxreg2 to mmxreg1|0000 1111:1101 0101: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:1101 0101: mod mmxreg r/m|
|**POR - Bitwise Or**||
|mmxreg2 to mmxreg1|0000 1111:1110 1011: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:1110 1011: mod mmxreg r/m|
|**PSLL\footnote{2}  - Packed shift left logical**||
|mmxreg1 by mmxreg2|0000 1111:1111 00gg: 11 mmxreg1 mmxreg2|
|mmxreg by memory|0000 1111:1111 00gg: mod mmxreg r/m|
|mmxreg by immediate|0000 1111:0111 00gg: 11 110 mmxreg: imm8 data|
|**PSRA\footnote{2}  - Packed shift right arithmetic**||
|mmxreg1 by mmxreg2|0000 1111:1110 00gg: 11 mmxreg1 mmxreg2|
|mmxreg by memory|0000 1111:1110 00gg: mod mmxreg r/m|
|mmxreg by immediate|0000 1111:0111 00gg: 11 100 mmxreg: imm8 data|
|**PSRL\footnote{2}  - Packed shift right logical**||
|mmxreg1 by mmxreg2|0000 1111:1101 00gg: 11 mmxreg1 mmxreg2|
|   mmxreg by memory|0000 1111:1101 00gg: mod mmxreg r/m|
|mmxreg by immediate|0000 1111:0111 00gg: 11 010 mmxreg: imm8 data|
|**PSUB - Subtract with wrap-around**||
|mmxreg2 from mmxreg1|0000 1111:1111 10gg: 11 mmxreg1 mmxreg2|
|memory from mmxreg|0000 1111:1111 10gg: mod mmxreg r/m|
|**PSUBS - Subtract signed with saturation**||
|mmxreg2 from mmxreg1|0000 1111:1110 10gg: 11 mmxreg1 mmxreg2|
|memory from mmxreg|0000 1111:1110 10gg: mod mmxreg r/m|
|**PSUBUS - Subtract unsigned with saturation**||
|mmxreg2 from mmxreg1|0000 1111:1101 10gg: 11 mmxreg1 mmxreg2|
|memory from mmxreg|0000 1111:1101 10gg: mod mmxreg r/m|
|**PUNPCKH - Unpack high data to next larger type**||
|mmxreg2 to mmxreg1|0000 1111:0110 10gg: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:0110 10gg: mod mmxreg r/m|
|**PUNPCKL - Unpack low data to next larger type**||
|mmxreg2 to mmxreg1|0000 1111:0110 00gg: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:0110 00gg: mod mmxreg r/m|
### Table B-19.  MMX Instruction Formats and Encodings (Contd.)


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|**PXOR - Bitwise Xor**||
|mmxreg2 to mmxreg1|0000 1111:1110 1111: 11 mmxreg1 mmxreg2|
|memory to mmxreg|0000 1111:1110 1111: mod mmxreg r/m|
### NOTES:


1.The pack instructions perform saturation from signed packed data of one type to signed or unsigned data of the next smaller type.

2.The format of the shift instructions has one additional format to support shifting by immediate shift-counts. The shift operations are not supported equally for all data types.

### B.6  PROCESSOR EXTENDED STATE INSTRUCTION FORMATS AND ENCODINGS 


TableB-20 shows the formats and encodings for several instructions that relate to processor extended state management.

  

### Table B-20.  Formats and Encodings of XSAVE/XRSTOR/XGETBV/XSETBV Instructions


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|**XGETBV - Get Value of Extended Control Register**|0000 1111:0000 0001: 1101 0000|
|**XRSTOR - Restore Processor Extended States**\footnote{1}|0000 1111:1010 1110: mod\footnote{A}  101 r/m|
|**XSAVE - Save Processor Extended States**\footnote{1}|0000 1111:1010 1110: mod\footnote{A}  100 r/m|
|**XSETBV - Set Extended Control Register**|0000 1111:0000 0001: 1101 0001|
### NOTES:


1.  For XSAVE and XRSTOR, "mod = 11" is reserved.

### B.7  P6 FAMILY INSTRUCTION FORMATS AND ENCODINGS 


TableB-20 shows the formats and encodings for several instructions that were introduced into the IA-32 architec-ture in the P6 family processors.

  

### Table B-21.  Formats and Encodings of P6 Family Instructions 


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|**CMOVcc - Conditional Move**||
|register2 to  register1|0000 1111: 0100 tttn : 11 reg1 reg2|
|memory to register  |0000 1111 : 0100 tttn : mod reg r/m|
|**FCMOVcc - Conditional Move on EFLAG Register Condition ****Codes**||
|move if below (B)|11011 010 : 11 000 ST(i)|
|move if equal (E)|11011 010 : 11 001 ST(i)|
|move if below or equal (BE)|11011 010 : 11 010 ST(i)|
|move if unordered (U)|11011 010 : 11 011 ST(i)|
|move if not below (NB)|11011 011 : 11 000 ST(i)|
|move if not equal (NE)|11011 011 : 11 001 ST(i)|
### Table B-21.  Formats and Encodings of P6 Family Instructions  (Contd.)


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|move if not below or equal (NBE)|11011 011 : 11 010 ST(i)|
|move if not unordered (NU)|11011 011 : 11 011 ST(i)|
|FCOMI** - **Compare Real and Set EFLAGS|11011 011 : 11 110 ST(i)|
|**FXRSTOR - Restore x87 FPU, MMX, SSE, and SSE2 State**\footnote{1}|0000 1111:1010 1110: mod\footnote{A}  001 r/m|
|**FXSAVE - Save x87 FPU, MMX, SSE, and SSE2 State**\footnote{1}|0000 1111:1010 1110: mod\footnote{A}  000 r/m|
|**SYSENTER - Fast System Call**|0000 1111:0011 0100|
|**SYSEXIT - Fast Return from Fast System Call**|0000 1111:0011 0101|
### NOTES:


1.  For  FXSAVE and FXRSTOR, "mod = 11" is reserved.

### B.8  SSE INSTRUCTION FORMATS AND ENCODINGS 


The SSE instructions use the ModR/M format and are preceded by the 0FH prefix byte. In general, operations are not duplicated to provide two directions (that is, separate load and store variants).

The following three tables (Tables B-22, B-23, and B-24) show the formats and encodings for the SSE SIMD floating-point, SIMD integer, and cacheability and memory ordering instructions, respectively. Some SSE instruc-tions require a mandatory prefix (66H, F2H, F3H) as part of the two-byte opcode. Mandatory prefixes are included in the tables.

### Table B-22.  Formats and Encodings of SSE Floating-Point Instructions 


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|**ADDPS--Add Packed Single-Precision Floating-Point ****Values**||
|   xmmreg2 to xmmreg1|0000 1111:0101 1000:11 xmmreg1 xmmreg2 |
|   mem to xmmreg|0000 1111:0101 1000:  mod xmmreg r/m|
|**ADDSS--Add Scalar Single-Precision Floating-Point ****Values**||
|   xmmreg2 to xmmreg1|1111 0011:0000 1111:01011000:11 xmmreg1 xmmreg2|
|   mem to xmmreg|1111 0011:0000 1111:01011000: mod xmmreg r/m|
|**ANDNPS--Bitwise Logical AND NOT of Packed Single-****Precision Floating-Point Values**||
|  xmmreg2 to xmmreg1|0000 1111:0101 0101:11 xmmreg1 xmmreg2|
|   mem to xmmreg|0000 1111:0101 0101:  mod xmmreg r/m|
|**ANDPS--Bitwise Logical AND of Packed Single-****Precision Floating-Point Values**||
|  xmmreg2 to xmmreg1|0000 1111:0101 0100:11 xmmreg1 xmmreg2|
|  mem to xmmreg|0000 1111:0101 0100:  mod xmmreg r/m|
|**CMPPS--Compare Packed Single-Precision Floating-****Point Values**||
|   xmmreg2 to xmmreg1, imm8|0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8|
|   mem to xmmreg, imm8|0000 1111:1100 0010:  mod xmmreg r/m: imm8|
|**CMPSS--Compare Scalar Single-Precision Floating-****Point Values**||
### Table B-22.  Formats and Encodings of SSE Floating-Point Instructions  (Contd.)


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|   xmmreg2 to xmmreg1, imm8|1111 0011:0000 1111:1100 0010:11 xmmreg1 xmmreg2: imm8|
|   mem to xmmreg, imm8|1111 0011:0000 1111:1100 0010: mod xmmreg r/m: imm8|
|**COMISS--Compare Scalar Ordered Single-Precision ****Floating-Point Values and Set EFLAGS**||
|   xmmreg2 to xmmreg1|0000 1111:0010 1111:11 xmmreg1 xmmreg2|
|   mem to xmmreg|0000 1111:0010 1111:  mod xmmreg r/m|
|**CVTPI2PS--Convert Packed Doubleword Integers to ****Packed Single-Precision Floating-Point Values**||
|  mmreg to xmmreg|0000 1111:0010 1010:11 xmmreg1 mmreg1|
|  mem to xmmreg|0000 1111:0010 1010:  mod xmmreg r/m|
|**CVTPS2PI--Convert Packed Single-Precision Floating-****Point Values to Packed Doubleword Integers**||
|  xmmreg to mmreg|0000 1111:0010 1101:11 mmreg1 xmmreg1|
|  mem to mmreg|0000 1111:0010 1101:  mod mmreg r/m|
|**CVTSI2SS--Convert Doubleword Integer to Scalar ****Single-Precision Floating-Point Value**||
|  r32 to xmmreg1|1111 0011:0000 1111:00101010:11 xmmreg1 r32|
|  mem to xmmreg|1111 0011:0000 1111:00101010: mod xmmreg r/m|
|**CVTSS2SI--Convert Scalar Single-Precision Floating-****Point Value to Doubleword Integer**||
|  xmmreg to r32|1111 0011:0000 1111:0010 1101:11 r32 xmmreg|
|  mem to r32|1111 0011:0000 1111:0010 1101: mod r32 r/m|
|**CVTTPS2PI--Convert with Truncation Packed Single-****Precision Floating-Point Values to Packed Doubleword ****Integers**||
|  xmmreg to mmreg|0000 1111:0010 1100:11 mmreg1 xmmreg1|
|  mem to mmreg|0000 1111:0010 1100:  mod mmreg r/m|
|**CVTTSS2SI--Convert with Truncation Scalar Single-****Precision Floating-Point Value to Doubleword Integer**||
|  xmmreg to r32|1111 0011:0000 1111:0010 1100:11 r32 xmmreg1|
|  mem to r32|1111 0011:0000 1111:0010 1100: mod r32 r/m|
|**DIVPS--Divide Packed Single-Precision Floating-Point ****Values**||
|  xmmreg2 to xmmreg1|0000 1111:0101 1110:11 xmmreg1 xmmreg2|
|  mem to xmmreg|0000 1111:0101 1110:  mod xmmreg r/m|
|**DIVSS--Divide Scalar Single-Precision Floating-Point ****Values**||
|  xmmreg2 to xmmreg1|1111 0011:0000 1111:0101 1110:11 xmmreg1 xmmreg2|
|  mem to xmmreg|1111 0011:0000 1111:0101 1110: mod xmmreg r/m|
|**LDMXCSR--Load  MXCSR Register State**||
|  m32 to MXCSR|0000 1111:1010 1110:mod\footnote{A}  010 mem|
|**MAXPS--Return Maximum Packed Single-Precision ****Floating-Point Values**||
### Table B-22.  Formats and Encodings of SSE Floating-Point Instructions  (Contd.)


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|  xmmreg2 to xmmreg1|0000 1111:0101 1111:11 xmmreg1 xmmreg2|
|  mem to xmmreg|0000 1111:0101 1111: mod xmmreg r/m|
|**MAXSS--Return Maximum Scalar Double-Precision ****Floating-Point Value**||
|  xmmreg2 to xmmreg1|1111 0011:0000 1111:0101 1111:11 xmmreg1 xmmreg2|
|  mem to xmmreg|1111 0011:0000 1111:0101 1111: mod xmmreg r/m|
|**MINPS--Return Minimum Packed Double-Precision ****Floating-Point ****Values**||
|  xmmreg2 to xmmreg1|0000 1111:0101 1101:11 xmmreg1 xmmreg2|
|  mem to xmmreg|0000 1111:0101 1101: mod xmmreg r/m|
|**MINSS--Return Minimum Scalar Double-Precision ****Floating-Point Value**||
|  xmmreg2 to xmmreg1|1111 0011:0000 1111:0101 1101:11 xmmreg1 xmmreg2|
|  mem to xmmreg|1111 0011:0000 1111:0101 1101: mod xmmreg r/m|
|**MOVAPS--Move Aligned Packed ****Single-Precision Floating-Point Values**||
|  xmmreg2 to xmmreg1|0000 1111:0010 1000:11 xmmreg2 xmmreg1|
|  mem to xmmreg1|0000 1111:0010 1000: mod xmmreg r/m|
|  xmmreg1 to xmmreg2|0000 1111:0010 1001:11 xmmreg1 xmmreg2|
|  xmmreg1 to mem|0000 1111:0010 1001: mod xmmreg r/m|
|**MOVHLPS--Move Packed Single-Precision Floating-****Point Values High to Low**||
|  xmmreg2 to xmmreg1|0000 1111:0001 0010:11 xmmreg1 xmmreg2|
|**MOVHPS--Move High Packed Single-Precision ****Floating-Point Values**||
|  mem to xmmreg|0000 1111:0001 0110: mod xmmreg r/m|
|  xmmreg to mem|0000 1111:0001 0111: mod xmmreg r/m|
|**MOVLHPS--Move Packed Single-Precision Floating-****Point Values Low to High**||
|  xmmreg2 to xmmreg1|0000 1111:00010110:11 xmmreg1 xmmreg2|
|**MOVLPS--Move Low Packed Single-Precision Floating-****Point Values**||
|  mem to xmmreg|0000 1111:0001 0010: mod xmmreg r/m|
|  xmmreg to mem|0000 1111:0001 0011: mod xmmreg r/m|
|**MOVMSKPS--Extract Packed Single-Precision Floating-****Point Sign Mask**||
|  xmmreg to r32|0000 1111:0101 0000:11 r32 xmmreg|
|**MOVSS--Move Scalar Single-Precision Floating-Point ****Values**||
|  xmmreg2 to xmmreg1|1111 0011:0000 1111:0001 0000:11 xmmreg2 xmmreg1|
|  mem to xmmreg1|1111 0011:0000 1111:0001 0000: mod xmmreg r/m|
### Table B-22.  Formats and Encodings of SSE Floating-Point Instructions  (Contd.)


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|  xmmreg1 to xmmreg2|1111 0011:0000 1111:0001 0001:11 xmmreg1 xmmreg2|
|  xmmreg1 to mem|1111 0011:0000 1111:0001 0001: mod xmmreg r/m|
|**MOVUPS--Move Unaligned Packed Single-Precision ****Floating-Point Values**||
|   xmmreg2 to xmmreg1|0000 1111:0001 0000:11 xmmreg2 xmmreg1|
|  mem to xmmreg1|0000 1111:0001 0000: mod xmmreg r/m|
|   xmmreg1 to xmmreg2|0000 1111:0001 0001:11 xmmreg1 xmmreg2|
|  xmmreg1 to mem|0000 1111:0001 0001: mod xmmreg r/m|
|**MULPS--Multiply Packed Single-Precision Floating-****Point Values**||
|   xmmreg2 to xmmreg1|0000 1111:0101 1001:11 xmmreg1 xmmreg2|
|   mem to xmmreg|0000 1111:0101 1001: mod xmmreg r/m|
|**MULSS--Multiply Scalar Single-Precision Floating-Point ****Values**||
|  xmmreg2 to xmmreg1|1111 0011:0000 1111:0101 1001:11 xmmreg1 xmmreg2|
|  mem to xmmreg|1111 0011:0000 1111:0101 1001: mod xmmreg r/m|
|**ORPS--Bitwise Logical OR of Single-Precision Floating-****Point Values**||
|  xmmreg2 to xmmreg1|0000 1111:0101 0110:11 xmmreg1 xmmreg2|
|   mem to xmmreg|0000 1111:0101 0110: mod xmmreg r/m|
|**RCPPS--Compute Reciprocals of Packed Single-****Precision Floating-Point Values**||
|  xmmreg2 to xmmreg1|0000 1111:0101 0011:11 xmmreg1 xmmreg2|
|  mem to xmmreg|0000 1111:0101 0011: mod xmmreg r/m|
|**RCPSS--Compute Reciprocals of Scalar Single-****Precision Floating-Point Value**||
|  xmmreg2 to xmmreg1|1111 0011:0000 1111:01010011:11 xmmreg1 xmmreg2|
|   mem to xmmreg|1111 0011:0000 1111:01010011: mod xmmreg r/m|
|**RSQRTPS--Compute Reciprocals of Square Roots of ****Packed Single-Precision Floating-Point Values**||
|  xmmreg2 to xmmreg1|0000 1111:0101 0010:11 xmmreg1 xmmreg2|
|  mem to xmmreg|0000 1111:0101 0010: mode xmmreg r/m|
|**RSQRTSS--Compute Reciprocals of Square Roots of ****Scalar Single-Precision Floating-Point Value**||
|   xmmreg2 to xmmreg1|1111 0011:0000 1111:0101 0010:11 xmmreg1 xmmreg2|
|   mem to xmmreg|1111 0011:0000 1111:0101 0010: mod xmmreg r/m|
|**SHUFPS--Shuffle Packed Single-Precision Floating-****Point Values**||
|  xmmreg2 to xmmreg1, imm8|0000 1111:1100 0110:11 xmmreg1 xmmreg2: imm8|
|  mem to xmmreg, imm8|0000 1111:1100 0110: mod xmmreg r/m: imm8|
|**SQRTPS--Compute Square Roots of Packed Single-****Precision Floating-Point Values**||
### Table B-22.  Formats and Encodings of SSE Floating-Point Instructions  (Contd.)


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|  xmmreg2 to xmmreg1|0000 1111:0101 0001:11 xmmreg1 xmmreg2|
|  mem to xmmreg|0000 1111:0101 0001: mod xmmreg r/m|
|**SQRTSS--Compute Square Root of Scalar Single-****Precision Floating-Point Value**||
|  xmmreg2 to xmmreg1|1111 0011:0000 1111:0101 0001:11 xmmreg1 xmmreg2|
|  mem to xmmreg|1111 0011:0000 1111:0101 0001:mod xmmreg r/m|
|**STMXCSR--Store MXCSR Register State**||
|   MXCSR to mem|0000 1111:1010 1110:mod\footnote{A}  011 mem|
|**SUBPS--Subtract Packed Single-Precision Floating-****Point Values**||
|  xmmreg2 to xmmreg1|0000 1111:0101 1100:11 xmmreg1 xmmreg2|
|  mem to xmmreg|0000 1111:0101 1100:mod xmmreg r/m|
|**SUBSS--Subtract Scalar Single-Precision Floating-****Point Values**||
|  xmmreg2 to xmmreg1|1111 0011:0000 1111:0101 1100:11 xmmreg1 xmmreg2|
|  mem to xmmreg|1111 0011:0000 1111:0101 1100:mod xmmreg r/m|
|**UCOMISS--Unordered Compare Scalar Ordered Single-****Precision Floating-Point Values and Set EFLAGS**||
|  xmmreg2 to xmmreg1|0000 1111:0010 1110:11 xmmreg1 xmmreg2|
|  mem to xmmreg|0000 1111:0010 1110: mod xmmreg r/m|
|**UNPCKHPS--Unpack and Interleave High Packed ****Single-Precision Floating-Point Values**||
|  xmmreg2 to xmmreg1|0000 1111:0001 0101:11 xmmreg1 xmmreg2|
|  mem to xmmreg|0000 1111:0001 0101: mod xmmreg r/m|
|**UNPCKLPS--Unpack and Interleave Low Packed ****Single-Precision Floating-Point Values**||
|  xmmreg2 to xmmreg1|0000 1111:0001 0100:11 xmmreg1 xmmreg2|
|  mem to xmmreg|0000 1111:0001 0100: mod xmmreg r/m|
|**XORPS--Bitwise Logical XOR of Single-Precision ****Floating-Point Values**||
|   xmmreg2 to xmmreg1|0000 1111:0101 0111:11 xmmreg1 xmmreg2|
|   mem to xmmreg|0000 1111:0101 0111: mod xmmreg r/m|
### Table B-23.  Formats and Encodings of SSE Integer Instructions


|**Instruction and Format**|**Encoding**|
|--------------------------|------------|
|**PAVGB/PAVGW--Average Packed Integers**||
|   mmreg2 to mmreg1|0000 1111:1110 0000:11 mmreg1 mmreg2|
||0000 1111:1110 0011:11 mmreg1 mmreg2|
|  mem to mmreg|0000 1111:1110 0000: mod mmreg r/m|
||0000 1111:1110 0011: mod mmreg r/m|
|**PEXTRW--Extract Word**||
|  mmreg to reg32, imm8|0000 1111:1100 0101:11 r32 mmreg: imm8|
|**PINSRW--Insert Word**||
|  reg32 to mmreg, imm8|0000 1111:1100 0100:11 mmreg r32: imm8|
|  m16 to mmreg, imm8|0000 1111:1100 0100: mod mmreg r/m: imm8|
|**PMAXSW--Maximum of Packed Signed Word Integers**||
|  mmreg2 to mmreg1|0000 1111:1110 1110:11 mmreg1 mmreg2|
|  mem to mmreg|0000 1111:1110 1110: mod mmreg r/m|
|**PMAXUB--Maximum of Packed Unsigned Byte Integers**||
|  mmreg2 to mmreg1|0000 1111:1101 1110:11 mmreg1 mmreg2|
|  mem to mmreg|0000 1111:1101 1110: mod mmreg r/m|
|**PMINSW--Minimum of Packed Signed Word Integers**||
|   mmreg2 to mmreg1|0000 1111:1110 1010:11 mmreg1 mmreg2|
|  mem to mmreg|0000 1111:1110 1010: mod mmreg r/m|
|**PMINUB--Minimum of Packed Unsigned Byte Integers**||
|   mmreg2 to mmreg1|0000 1111:1101 1010:11 mmreg1 mmreg2|
|  mem to mmreg|0000 1111:1101 1010: mod mmreg r/m|
|**PMOVMSKB--Move Byte Mask To Integer**||
|   mmreg to reg32|0000 1111:1101 0111:11 r32 mmreg|
|**PMULHUW--Multiply Packed Unsigned Integers and Store High ****Result**||
|  mmreg2 to mmreg1|0000 1111:1110 0100:11 mmreg1 mmreg2|
|  mem to mmreg|0000 1111:1110 0100: mod mmreg r/m|
|**PSADBW--Compute Sum of Absolute Differences**||
|  mmreg2 to mmreg1|0000 1111:1111 0110:11 mmreg1 mmreg2|
|  mem to mmreg|0000 1111:1111 0110: mod mmreg r/m|
|**PSHUFW--Shuffle Packed Words**||
|   mmreg2 to mmreg1, imm8|0000 1111:0111 0000:11 mmreg1 mmreg2: imm8|
|   mem to mmreg, imm8|0000 1111:0111 0000: mod mmreg r/m: imm8|
