make[2]: Entering directory '/tmp/build-dir'
ncelab: *W,CUSRCH: Resolved design unit 'dummyram' at 'u_dummyrams' to 'dummysoc.dummyram:v' through a global search of all libraries.
ncelab: *W,CUVWSP (../verilog/placeholder.v,313|24): 10 output ports were not connected
ncelab: *W,CUNOTB: component instance is not fully bound (some.long:placeholder:blah:r1) [File:freaking_gbit_astral.vhd, Line:310].
