
---------- Begin Simulation Statistics ----------
simSeconds                                   0.001050                       # Number of seconds simulated (Second)
simTicks                                   1050271677                       # Number of ticks simulated (Tick)
finalTick                                  1050271677                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq                                  1000000000000                       # The number of ticks per simulated second ((Tick/Second))
hostSeconds                                      1.71                       # Real time elapsed on the host (Second)
hostTickRate                                613837596                       # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory                                    1181216                       # Number of bytes of host memory used (Byte)
simInsts                                      1753641                       # Number of instructions simulated (Count)
simOps                                        2308506                       # Number of ops (including micro ops) simulated (Count)
hostInstRate                                  1024864                       # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate                                    1349127                       # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data       710420                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total       710420                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data       710420                       # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total       710420                       # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data          286                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total          286                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data          286                       # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total          286                       # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandMissLatency::processor.cores.core.data     14387931                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMissLatency::total     14387931                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::processor.cores.core.data     14387931                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::total     14387931                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data       710706                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total       710706                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data       710706                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total       710706                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data     0.000402                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total     0.000402                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data     0.000402                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total     0.000402                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::processor.cores.core.data 50307.451049                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::total 50307.451049                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::processor.cores.core.data 50307.451049                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total 50307.451049                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.writebacks::writebacks            2                       # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.writebacks::total            2                       # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::processor.cores.core.data           11                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::total           11                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::processor.cores.core.data           11                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::total           11                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::processor.cores.core.data          275                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::total          275                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher           77                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::processor.cores.core.data          275                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::total          352                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::processor.cores.core.data     14176143                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::total     14176143                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher      4534370                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::processor.cores.core.data     14176143                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::total     18710513                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::processor.cores.core.data     0.000387                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::total     0.000387                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher          inf                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::processor.cores.core.data     0.000387                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::total     0.000495                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::processor.cores.core.data 51549.610909                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::total 51549.610909                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 58887.922078                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::processor.cores.core.data 51549.610909                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::total 53154.866477                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.replacements            2                       # number of replacements (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher           77                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::total           77                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher      4534370                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::total      4534370                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::total          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 58887.922078                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::total 58887.922078                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data       583500                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total       583500                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data          121                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total          121                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::processor.cores.core.data      5968692                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::total      5968692                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data       583621                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total       583621                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data     0.000207                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total     0.000207                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::processor.cores.core.data 49328.033058                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::total 49328.033058                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::processor.cores.core.data            2                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::total            2                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::processor.cores.core.data          119                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::total          119                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::processor.cores.core.data      5921739                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::total      5921739                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::processor.cores.core.data     0.000204                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::total     0.000204                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::processor.cores.core.data 49762.512605                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::total 49762.512605                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data       126920                       # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total       126920                       # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data          165                       # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total          165                       # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::processor.cores.core.data      8419239                       # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::total      8419239                       # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data       127085                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total       127085                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data     0.001298                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total     0.001298                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::processor.cores.core.data 51025.690909                       # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::total 51025.690909                       # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::processor.cores.core.data            9                       # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::total            9                       # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::processor.cores.core.data          156                       # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::total          156                       # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::processor.cores.core.data      8254404                       # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::total      8254404                       # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::processor.cores.core.data     0.001228                       # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::total     0.001228                       # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::processor.cores.core.data 52912.846154                       # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::total 52912.846154                       # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses          275                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued          106                       # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUnused            2                       # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful           55                       # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy     0.518868                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage     0.166667                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache            8                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR           21                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate           29                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified          106                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand            0                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage           10                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage            0                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse   325.798671                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs       710772                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs          352                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs  2019.238636                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick       127539                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher    73.159023                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data   252.639648                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher     0.142889                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data     0.493437                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total     0.636326                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1022           75                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024          275                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::2           16                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::3           59                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0           10                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::2           52                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::3          213                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1022     0.146484                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024     0.537109                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses      5686000                       # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses      5686000                       # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst      2324445                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total      2324445                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst      2324445                       # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total      2324445                       # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst          518                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total          518                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst          518                       # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total          518                       # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandMissLatency::processor.cores.core.inst     25274700                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMissLatency::total     25274700                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::processor.cores.core.inst     25274700                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::total     25274700                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst      2324963                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total      2324963                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst      2324963                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total      2324963                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst     0.000223                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total     0.000223                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst     0.000223                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total     0.000223                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMissLatency::processor.cores.core.inst 48792.857143                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMissLatency::total 48792.857143                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::processor.cores.core.inst 48792.857143                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::total 48792.857143                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.writebacks::writebacks           71                       # number of writebacks (Count)
board.cache_hierarchy.l1icaches.writebacks::total           71                       # number of writebacks (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::processor.cores.core.inst          518                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::total          518                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::processor.cores.core.inst          518                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::total          518                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::processor.cores.core.inst     25102206                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::total     25102206                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::processor.cores.core.inst     25102206                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::total     25102206                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissRate::processor.cores.core.inst     0.000223                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMshrMissRate::total     0.000223                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::processor.cores.core.inst     0.000223                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::total     0.000223                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::processor.cores.core.inst 48459.857143                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::total 48459.857143                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::processor.cores.core.inst 48459.857143                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::total 48459.857143                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.replacements           71                       # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst      2324445                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total      2324445                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst          518                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total          518                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::processor.cores.core.inst     25274700                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::total     25274700                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst      2324963                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total      2324963                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst     0.000223                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total     0.000223                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::processor.cores.core.inst 48792.857143                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::total 48792.857143                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::processor.cores.core.inst          518                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::total          518                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::processor.cores.core.inst     25102206                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::total     25102206                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::processor.cores.core.inst     0.000223                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::total     0.000223                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::processor.cores.core.inst 48459.857143                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::total 48459.857143                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses          518                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued            0                       # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful            0                       # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy          nan                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage            0                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache            0                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR            0                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate            0                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified            0                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand            0                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage            0                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage            0                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse   401.285299                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs      2324963                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs          518                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs  4488.345560                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick        69597                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst   401.285299                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst     0.783760                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total     0.783760                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024          447                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0           50                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::2          100                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::3          297                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024     0.873047                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses     18600222                       # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses     18600222                       # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp          714                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackClean           73                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq          156                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp          156                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq          714                       # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port         1107                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::total         1107                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port          706                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::total          706                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total         1813                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port        37696                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::total        37696                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port        22656                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::total        22656                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total        60352                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops                 0                       # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic            0                       # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples          870                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows            0      0.00%      0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0          870    100.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total          870                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy       340970                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy       439058                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy       294541                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests          943                       # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests           73                       # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops            0                       # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock                            333                       # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage             1                       # Voltage in Volts (Volt)
board.memory.mem_ctrl.avgPriority_writebacks::samples        73.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l1dcaches.prefetcher::samples        77.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples       518.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples       275.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000018750                       # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.002053911898                       # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds            3                       # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds            3                       # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState           2067                       # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState            45                       # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs                    870                       # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs                    73                       # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts                  870                       # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts                  73                       # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ                 0                       # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts                0                       # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen                  1.38                       # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen                 24.25                       # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry                    0                       # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry                    0                       # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6              870                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6              73                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0                794                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1                 23                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2                 20                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3                 18                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4                 15                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17                 4                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18                 4                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19                 4                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20                 4                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21                 4                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22                 4                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23                 4                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24                 4                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25                 3                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26                 3                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27                 3                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28                 3                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29                 3                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30                 3                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31                 3                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32                 3                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdPerTurnAround::samples            3                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::mean   284.666667                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::gmean   121.371759                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::stdev   408.230735                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::32-63            2     66.67%     66.67% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::736-767            1     33.33%    100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::total            3                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.wrPerTurnAround::samples            3                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::mean           16                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::gmean    16.000000                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::16            3    100.00%    100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::total            3                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.bytesReadWrQ                  0                       # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys              55680                       # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys            4672                       # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys         53014854.36515298                       # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys         4448372.83753583                       # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap               1050228054                       # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap               1113709.50                       # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l1dcaches.prefetcher         4928                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst        33152                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data        17600                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorWriteBytes::writebacks         3072                       # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l1dcaches.prefetcher 4692119.294387103058                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 31565166.162240512669                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 16757568.908525368199                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorWriteRate::writebacks 2924957.482215336990                       # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l1dcaches.prefetcher           77                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst          518                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data          275                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorWriteAccesses::writebacks           73                       # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l1dcaches.prefetcher      2698670                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst     12750702                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data      7621783                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorWriteTotalLat::writebacks  20160659689                       # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l1dcaches.prefetcher     35047.66                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst     24615.25                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data     27715.57                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorWriteAvgLat::writebacks 276173420.40                       # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l1dcaches.prefetcher         4928                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst        33152                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data        17600                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total        55680                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst        33152                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total        33152                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l1dcaches.prefetcher           77                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst          518                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data          275                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total          870                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l1dcaches.prefetcher      4692119                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst     31565166                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data     16757569                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total     53014854                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst     31565166                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total     31565166                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l1dcaches.prefetcher      4692119                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst     31565166                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data     16757569                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total     53014854                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts             870                       # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts             48                       # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0           97                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1           70                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2           34                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3           20                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4           30                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5            4                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6            5                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7           45                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8           85                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9           73                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10          120                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11           72                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12           10                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13           13                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14           56                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15          136                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0            3                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1           11                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2            6                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4           13                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7            1                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10           13                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11            1                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat            6758655                       # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat          4350000                       # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat      23071155                       # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat            7768.57                       # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat          5000.00                       # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat      26518.57                       # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits            670                       # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits            39                       # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate        77.01                       # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate        81.25                       # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples          199                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean   283.658291                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean   174.890953                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev   300.972370                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127           72     36.18%     36.18% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255           51     25.63%     61.81% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383           25     12.56%     74.37% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511           13      6.53%     80.90% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639            9      4.52%     85.43% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767            5      2.51%     87.94% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895            3      1.51%     89.45% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023            2      1.01%     90.45% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151           19      9.55%    100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total          199                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesRead            55680                       # Total bytes read (Byte)
board.memory.mem_ctrl.dram.bytesWritten          3072                       # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW          53.014854                       # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW           2.924957                       # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW            12800.00                       # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil               0.44                       # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead           0.41                       # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite          0.02                       # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate          77.23                       # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy       528360                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy       265650                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy      2177700                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy       177480                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 82361760.000000                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy     39628110                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy    369933600                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy    495072660                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower   471.375808                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE    961399653                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF     34840000                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT     54032024                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy       963900                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy       489555                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy      4034100                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy        73080                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 82361760.000000                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy     65267280                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy    348342720                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy    501532395                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower   477.526345                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE    904930687                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF     34840000                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT    110500990                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles          3153969                       # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.numWorkItemsStarted            0                       # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted            0                       # Number of work items this cpu completed (Count)
board.processor.cores.core.exec_context.thread_0.numInsts      1753641                       # Number of instructions committed (Count)
board.processor.cores.core.exec_context.thread_0.numOps      2308506                       # Number of ops (including micro ops) committed (Count)
board.processor.cores.core.exec_context.thread_0.numIntAluAccesses      2297376                       # Number of integer alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numFpAluAccesses         1465                       # Number of float alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numVecAluAccesses            0                       # Number of vector alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numCallsReturns        12490                       # Number of times a function call or return occured (Count)
board.processor.cores.core.exec_context.thread_0.numCondCtrlInsts        50635                       # Number of instructions that are conditional controls (Count)
board.processor.cores.core.exec_context.thread_0.numIntInsts      2297376                       # Number of integer instructions (Count)
board.processor.cores.core.exec_context.thread_0.numFpInsts         1465                       # Number of float instructions (Count)
board.processor.cores.core.exec_context.thread_0.numVecInsts            0                       # Number of vector instructions (Count)
board.processor.cores.core.exec_context.thread_0.numIntRegReads      3860134                       # Number of times the integer registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numIntRegWrites      2054055                       # Number of times the integer registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numFpRegReads         1822                       # Number of times the floating registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numFpRegWrites          891                       # Number of times the floating registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numVecRegReads            0                       # Number of times the vector registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numVecRegWrites            0                       # Number of times the vector registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numVecPredRegReads            0                       # Number of times the predicate registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numVecPredRegWrites            0                       # Number of times the predicate registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numCCRegReads       520852                       # Number of times the CC registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numCCRegWrites      1333953                       # Number of times the CC registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numMiscRegReads       854201                       # Number of times the Misc registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numMiscRegWrites            0                       # Number of times the Misc registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numMemRefs       710705                       # Number of memory refs (Count)
board.processor.cores.core.exec_context.thread_0.numLoadInsts       583618                       # Number of load instructions (Count)
board.processor.cores.core.exec_context.thread_0.numStoreInsts       127087                       # Number of store instructions (Count)
board.processor.cores.core.exec_context.thread_0.numIdleCycles     0.003003                       # Number of idle cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.numBusyCycles 3153968.996997                       # Number of busy cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.notIdleFraction     1.000000                       # Percentage of non-idle cycles (Ratio)
board.processor.cores.core.exec_context.thread_0.idleFraction     0.000000                       # Percentage of idle cycles (Ratio)
board.processor.cores.core.exec_context.thread_0.numBranches        65715                       # Number of branches fetched (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::No_OpClass         6337      0.27%      0.27% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IntAlu      1538710     66.65%     66.93% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IntMult        52025      2.25%     69.18% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IntDiv           63      0.00%     69.18% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatAdd          154      0.01%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatCmp            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatCvt            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMult            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMultAcc            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatDiv            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMisc            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatSqrt            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAdd            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAddAcc            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAlu          136      0.01%     69.20% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdCmp            0      0.00%     69.20% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdCvt           86      0.00%     69.20% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdMisc          310      0.01%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdMult            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdMultAcc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShift            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShiftAcc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdDiv            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSqrt            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatAdd            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatAlu            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatCmp            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatCvt            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatDiv            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatMisc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatMult            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatMultAcc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatSqrt            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdReduceAdd            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdReduceAlu            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdReduceCmp            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatReduceAdd            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatReduceCmp            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAes            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAesMix            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha1Hash            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha1Hash2            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha256Hash            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha256Hash2            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShaSigma2            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShaSigma3            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdPredAlu            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::MemRead       583520     25.28%     94.49% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::MemWrite       126579      5.48%     99.97% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMemRead           98      0.00%     99.98% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMemWrite          508      0.02%    100.00% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IprAccess            0      0.00%    100.00% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::InstPrefetch            0      0.00%    100.00% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::total      2308526                       # Class of executed instruction. (Count)
board.processor.cores.core.interrupts.clk_domain.clock         5328                       # Clock period in ticks (Tick)
board.processor.cores.core.mmu.dtb.rdAccesses       583622                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses       127088                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses           13                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses           14                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses            0                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses      2324963                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses            0                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses           50                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON   1050271677                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.thread_0.numInsts            0                       # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps            0                       # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs            0                       # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls           16                       # Number of system calls (Count)
board.workload.inst.arm                             0                       # number of arm instructions executed (Count)
board.workload.inst.quiesce                         0                       # number of quiesce instructions executed (Count)

---------- End Simulation Statistics   ----------
