
---------- Begin Simulation Statistics ----------
simSeconds                                   0.000959                       # Number of seconds simulated (Second)
simTicks                                    958982391                       # Number of ticks simulated (Tick)
finalTick                                   958982391                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq                                  1000000000000                       # The number of ticks per simulated second ((Tick/Second))
hostSeconds                                      1.07                       # Real time elapsed on the host (Second)
hostTickRate                                895411131                       # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory                                    1181212                       # Number of bytes of host memory used (Byte)
simInsts                                      1753641                       # Number of instructions simulated (Count)
simOps                                        2308506                       # Number of ops (including micro ops) simulated (Count)
hostInstRate                                  1637236                       # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate                                    2155238                       # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data       710365                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total       710365                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data       710365                       # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total       710365                       # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data          341                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total          341                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data          341                       # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total          341                       # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data       710706                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total       710706                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data       710706                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total       710706                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data     0.000480                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total     0.000480                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data     0.000480                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total     0.000480                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data       583498                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total       583498                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data          123                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total          123                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data       583621                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total       583621                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data     0.000211                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total     0.000211                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data       126867                       # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total       126867                       # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data          218                       # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total          218                       # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data       127085                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total       127085                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data     0.001715                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total     0.001715                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses            0                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued            0                       # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful            0                       # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy          nan                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage          nan                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache            0                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR            0                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate            0                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified            0                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand            0                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage            0                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage            0                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse   320.381534                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs       710706                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs          341                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs  2084.181818                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick         1332                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data   320.381534                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data     0.625745                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total     0.625745                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024          341                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0           10                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::2          331                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024     0.666016                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses      5685989                       # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses      5685989                       # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst      2324445                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total      2324445                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst      2324445                       # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total      2324445                       # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst          518                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total          518                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst          518                       # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total          518                       # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst      2324963                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total      2324963                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst      2324963                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total      2324963                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst     0.000223                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total     0.000223                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst     0.000223                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total     0.000223                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.writebacks::writebacks           71                       # number of writebacks (Count)
board.cache_hierarchy.l1icaches.writebacks::total           71                       # number of writebacks (Count)
board.cache_hierarchy.l1icaches.replacements           71                       # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst      2324445                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total      2324445                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst          518                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total          518                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst      2324963                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total      2324963                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst     0.000223                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total     0.000223                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses            0                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued            0                       # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful            0                       # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy          nan                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage          nan                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache            0                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR            0                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate            0                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified            0                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand            0                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage            0                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage            0                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse   407.041620                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs      2324963                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs          518                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs  4488.345560                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst   407.041620                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst     0.795003                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total     0.795003                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024          447                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0           50                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::2          397                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024     0.873047                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses     18600222                       # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses     18600222                       # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp          641                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackClean           71                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq          218                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp          218                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq          641                       # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port         1107                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::total         1107                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port          682                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::total          682                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total         1789                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port        37696                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::total        37696                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port        21824                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::total        21824                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total        59520                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops                 0                       # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic            0                       # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples          859                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows            0      0.00%      0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0          859    100.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total          859                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.snoop_filter.totRequests          930                       # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests           71                       # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops            0                       # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock                            333                       # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage             1                       # Voltage in Volts (Volt)
board.memory.mem_ctrl.priorityMinLatency 0.000000000000                       # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.000000000000                       # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds            0                       # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds            0                       # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState              0                       # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState             0                       # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs                      0                       # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs                     0                       # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts                    0                       # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts                   0                       # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ                 0                       # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts                0                       # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen                  0.00                       # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen                  0.00                       # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry                    0                       # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry                    0                       # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9                  0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.bytesReadWrQ                  0                       # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys                  0                       # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys               0                       # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys           0.00000000                       # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys           0.00000000                       # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap                        0                       # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap                      nan                       # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst        33152                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data        21824                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total        54976                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst        33152                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total        33152                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst          518                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data          341                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total          859                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst     34569978                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data     22757456                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total     57327434                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst     34569978                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total     34569978                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst     34569978                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data     22757456                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total     57327434                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts               0                       # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts              0                       # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat                  0                       # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat                0                       # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat             0                       # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat                nan                       # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat              nan                       # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat           nan                       # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits              0                       # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits             0                       # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate          nan                       # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate          nan                       # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesRead                0                       # Total bytes read (Byte)
board.memory.mem_ctrl.dram.bytesWritten             0                       # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW                  0                       # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW                  0                       # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW            12800.00                       # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil               0.00                       # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead           0.00                       # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite          0.00                       # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate            nan                       # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy            0                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy            0                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy            0                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy            0                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy            0                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy            0                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy    368249280                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy    368249280                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower   384.000044                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE    958982391                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy            0                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy            0                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy            0                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy            0                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy            0                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy            0                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy    368249280                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy    368249280                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower   384.000044                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE    958982391                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles          2879828                       # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.numWorkItemsStarted            0                       # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted            0                       # Number of work items this cpu completed (Count)
board.processor.cores.core.exec_context.thread_0.numInsts      1753641                       # Number of instructions committed (Count)
board.processor.cores.core.exec_context.thread_0.numOps      2308506                       # Number of ops (including micro ops) committed (Count)
board.processor.cores.core.exec_context.thread_0.numIntAluAccesses      2297376                       # Number of integer alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numFpAluAccesses         1465                       # Number of float alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numVecAluAccesses            0                       # Number of vector alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numCallsReturns        12490                       # Number of times a function call or return occured (Count)
board.processor.cores.core.exec_context.thread_0.numCondCtrlInsts        50635                       # Number of instructions that are conditional controls (Count)
board.processor.cores.core.exec_context.thread_0.numIntInsts      2297376                       # Number of integer instructions (Count)
board.processor.cores.core.exec_context.thread_0.numFpInsts         1465                       # Number of float instructions (Count)
board.processor.cores.core.exec_context.thread_0.numVecInsts            0                       # Number of vector instructions (Count)
board.processor.cores.core.exec_context.thread_0.numIntRegReads      3860134                       # Number of times the integer registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numIntRegWrites      2054055                       # Number of times the integer registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numFpRegReads         1822                       # Number of times the floating registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numFpRegWrites          891                       # Number of times the floating registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numVecRegReads            0                       # Number of times the vector registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numVecRegWrites            0                       # Number of times the vector registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numVecPredRegReads            0                       # Number of times the predicate registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numVecPredRegWrites            0                       # Number of times the predicate registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numCCRegReads       520852                       # Number of times the CC registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numCCRegWrites      1333953                       # Number of times the CC registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numMiscRegReads       854201                       # Number of times the Misc registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numMiscRegWrites            0                       # Number of times the Misc registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numMemRefs       710705                       # Number of memory refs (Count)
board.processor.cores.core.exec_context.thread_0.numLoadInsts       583618                       # Number of load instructions (Count)
board.processor.cores.core.exec_context.thread_0.numStoreInsts       127087                       # Number of store instructions (Count)
board.processor.cores.core.exec_context.thread_0.numIdleCycles     0.003003                       # Number of idle cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.numBusyCycles 2879827.996997                       # Number of busy cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.notIdleFraction     1.000000                       # Percentage of non-idle cycles (Ratio)
board.processor.cores.core.exec_context.thread_0.idleFraction     0.000000                       # Percentage of idle cycles (Ratio)
board.processor.cores.core.exec_context.thread_0.numBranches        65715                       # Number of branches fetched (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::No_OpClass         6337      0.27%      0.27% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IntAlu      1538710     66.65%     66.93% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IntMult        52025      2.25%     69.18% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IntDiv           63      0.00%     69.18% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatAdd          154      0.01%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatCmp            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatCvt            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMult            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMultAcc            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatDiv            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMisc            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatSqrt            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAdd            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAddAcc            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAlu          136      0.01%     69.20% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdCmp            0      0.00%     69.20% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdCvt           86      0.00%     69.20% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdMisc          310      0.01%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdMult            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdMultAcc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShift            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShiftAcc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdDiv            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSqrt            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatAdd            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatAlu            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatCmp            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatCvt            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatDiv            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatMisc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatMult            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatMultAcc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatSqrt            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdReduceAdd            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdReduceAlu            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdReduceCmp            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatReduceAdd            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatReduceCmp            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAes            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAesMix            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha1Hash            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha1Hash2            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha256Hash            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha256Hash2            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShaSigma2            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShaSigma3            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdPredAlu            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::MemRead       583520     25.28%     94.49% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::MemWrite       126579      5.48%     99.97% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMemRead           98      0.00%     99.98% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMemWrite          508      0.02%    100.00% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IprAccess            0      0.00%    100.00% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::InstPrefetch            0      0.00%    100.00% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::total      2308526                       # Class of executed instruction. (Count)
board.processor.cores.core.interrupts.clk_domain.clock         5328                       # Clock period in ticks (Tick)
board.processor.cores.core.mmu.dtb.rdAccesses       583622                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses       127088                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses           13                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses           14                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses            0                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses      2324963                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses            0                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses           50                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON    958982391                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.thread_0.numInsts            0                       # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps            0                       # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs            0                       # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls           16                       # Number of system calls (Count)
board.workload.inst.arm                             0                       # number of arm instructions executed (Count)
board.workload.inst.quiesce                         0                       # number of quiesce instructions executed (Count)

---------- End Simulation Statistics   ----------
