
---------- Begin Simulation Statistics ----------
simSeconds                                   0.001798                       # Number of seconds simulated (Second)
simTicks                                   1797545322                       # Number of ticks simulated (Tick)
finalTick                                  1797545322                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq                                  1000000000000                       # The number of ticks per simulated second ((Tick/Second))
hostSeconds                                      1.96                       # Real time elapsed on the host (Second)
hostTickRate                                918370947                       # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory                                    1180192                       # Number of bytes of host memory used (Byte)
simInsts                                      1753641                       # Number of instructions simulated (Count)
simOps                                        2308506                       # Number of ops (including micro ops) simulated (Count)
hostInstRate                                   895897                       # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate                                    1179357                       # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data       683861                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total       683861                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data       683861                       # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total       683861                       # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data        26845                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total        26845                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data        26845                       # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total        26845                       # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandMissLatency::processor.cores.core.data    733697235                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMissLatency::total    733697235                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::processor.cores.core.data    733697235                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::total    733697235                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data       710706                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total       710706                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data       710706                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total       710706                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data     0.037772                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total     0.037772                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data     0.037772                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total     0.037772                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::processor.cores.core.data 27330.871112                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::total 27330.871112                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::processor.cores.core.data 27330.871112                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total 27330.871112                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.writebacks::writebacks        58944                       # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.writebacks::total        58944                       # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::processor.cores.core.data          977                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::total          977                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::processor.cores.core.data          977                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::total          977                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::processor.cores.core.data        25868                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::total        25868                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher        33092                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::processor.cores.core.data        25868                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::total        58960                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::processor.cores.core.data    692119854                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::total    692119854                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher   1043479785                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::processor.cores.core.data    692119854                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::total   1735599639                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::processor.cores.core.data     0.036398                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::total     0.036398                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher          inf                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::processor.cores.core.data     0.036398                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::total     0.082960                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::processor.cores.core.data 26755.831684                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::total 26755.831684                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 31532.690227                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::processor.cores.core.data 26755.831684                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::total 29436.900254                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.replacements        58944                       # number of replacements (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher        33092                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::total        33092                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher   1043479785                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::total   1043479785                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::total          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 31532.690227                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::total 31532.690227                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data       557367                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total       557367                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data        26254                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total        26254                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::processor.cores.core.data    703097865                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::total    703097865                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data       583621                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total       583621                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data     0.044985                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total     0.044985                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::processor.cores.core.data 26780.599718                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::total 26780.599718                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::processor.cores.core.data          969                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::total          969                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::processor.cores.core.data        25285                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::total        25285                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::processor.cores.core.data    661882122                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::total    661882122                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::processor.cores.core.data     0.043324                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::total     0.043324                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::processor.cores.core.data 26176.868578                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::total 26176.868578                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data       126494                       # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total       126494                       # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data          591                       # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total          591                       # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::processor.cores.core.data     30599370                       # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::total     30599370                       # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data       127085                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total       127085                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data     0.004650                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total     0.004650                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::processor.cores.core.data 51775.583756                       # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::total 51775.583756                       # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::processor.cores.core.data            8                       # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::total            8                       # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::processor.cores.core.data          583                       # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::total          583                       # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::processor.cores.core.data     30237732                       # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::total     30237732                       # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::processor.cores.core.data     0.004587                       # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::total     0.004587                       # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::processor.cores.core.data 51865.749571                       # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::total 51865.749571                       # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses        25868                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued        39852                       # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUnused        12499                       # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful        19612                       # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy     0.492121                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage     0.431223                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache         5642                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR         1118                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate         6760                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified        39852                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand            0                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage         3520                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage            0                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse    15.993987                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs       742821                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs        58960                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs    12.598728                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick       127539                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher     6.571463                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data     9.422524                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher     0.410716                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data     0.588908                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total     0.999624                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1022            4                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024           12                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::0            4                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0           12                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1022     0.250000                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024     0.750000                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses      5744608                       # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses      5744608                       # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst      2323746                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total      2323746                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst      2323746                       # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total      2323746                       # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst         1217                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total         1217                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst         1217                       # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total         1217                       # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandMissLatency::processor.cores.core.inst     62499438                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMissLatency::total     62499438                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::processor.cores.core.inst     62499438                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::total     62499438                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst      2324963                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total      2324963                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst      2324963                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total      2324963                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst     0.000523                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total     0.000523                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst     0.000523                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total     0.000523                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMissLatency::processor.cores.core.inst 51355.331142                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMissLatency::total 51355.331142                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::processor.cores.core.inst 51355.331142                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::total 51355.331142                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.writebacks::writebacks         1201                       # number of writebacks (Count)
board.cache_hierarchy.l1icaches.writebacks::total         1201                       # number of writebacks (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::processor.cores.core.inst         1217                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::total         1217                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::processor.cores.core.inst         1217                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::total         1217                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::processor.cores.core.inst     62094177                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::total     62094177                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::processor.cores.core.inst     62094177                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::total     62094177                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissRate::processor.cores.core.inst     0.000523                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMshrMissRate::total     0.000523                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::processor.cores.core.inst     0.000523                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::total     0.000523                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::processor.cores.core.inst 51022.331142                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::total 51022.331142                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::processor.cores.core.inst 51022.331142                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::total 51022.331142                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.replacements         1201                       # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst      2323746                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total      2323746                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst         1217                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total         1217                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::processor.cores.core.inst     62499438                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::total     62499438                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst      2324963                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total      2324963                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst     0.000523                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total     0.000523                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::processor.cores.core.inst 51355.331142                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::total 51355.331142                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::processor.cores.core.inst         1217                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::total         1217                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::processor.cores.core.inst     62094177                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::total     62094177                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::processor.cores.core.inst     0.000523                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::total     0.000523                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::processor.cores.core.inst 51022.331142                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::total 51022.331142                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses         1217                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued            0                       # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful            0                       # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy          nan                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage            0                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache            0                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR            0                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate            0                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified            0                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand            0                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage            0                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage            0                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse    15.990420                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs      2324963                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs         1217                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs  1910.405094                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick        69597                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst    15.990420                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst     0.999401                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total     0.999401                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024           16                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0           16                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024            1                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses     18600921                       # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses     18600921                       # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp        59594                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackDirty         2793                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackClean        57352                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq          583                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp          583                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq        59594                       # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port         3635                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::total         3635                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port       176864                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::total       176864                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total       180499                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port       154752                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::total       154752                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port      7545856                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::total      7545856                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total      7700608                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops                 0                       # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic            0                       # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples        60177                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows            0      0.00%      0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0        60177    100.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total        60177                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy     60387475                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy      1044541                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy     49895811                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests       120322                       # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests        60145                       # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops            0                       # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock                            333                       # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage             1                       # Voltage in Volts (Volt)
board.memory.mem_ctrl.avgPriority_writebacks::samples     28554.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l1dcaches.prefetcher::samples     11048.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples      1079.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples      7243.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000018750                       # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.000043219188                       # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds         1636                       # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds         1636                       # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState          90683                       # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState         26987                       # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs                  60177                       # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs                 60145                       # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts                60177                       # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts               60145                       # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ             40807                       # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts            31591                       # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen                  1.69                       # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen                 26.51                       # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry                    0                       # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry                    0                       # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6            60177                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6           60145                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0              11654                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1               3854                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2               2232                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3               1139                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4                435                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5                 48                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6                  6                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7                  1                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8                  1                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9                  0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15               576                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16               697                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17              1061                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18              1318                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19              1487                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20              1675                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21              1784                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22              1856                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23              1832                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24              1796                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25              1766                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26              1785                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27              2129                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28              1931                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29              1790                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30              1708                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31              1662                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32              1646                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33                25                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34                 9                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35                 4                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdPerTurnAround::samples         1636                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::mean    11.835575                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::gmean    11.415972                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::stdev     3.209959                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::2-3            3      0.18%      0.18% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::4-5           21      1.28%      1.47% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::6-7           78      4.77%      6.23% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::8-9          252     15.40%     21.64% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::10-11          433     26.47%     48.11% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::12-13          399     24.39%     72.49% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::14-15          271     16.56%     89.06% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::16-17          124      7.58%     96.64% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::18-19           35      2.14%     98.78% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::20-21           12      0.73%     99.51% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::22-23            7      0.43%     99.94% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::58-59            1      0.06%    100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::total         1636                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.wrPerTurnAround::samples         1636                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::mean    17.438264                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::gmean    17.349397                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::stdev     1.818486                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::16          870     53.18%     53.18% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::17           57      3.48%     56.66% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::18          267     16.32%     72.98% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::19          205     12.53%     85.51% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::20          123      7.52%     93.03% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::21           56      3.42%     96.45% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::22           37      2.26%     98.72% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::23           16      0.98%     99.69% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::24            4      0.24%     99.94% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::25            1      0.06%    100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::total         1636                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.bytesReadWrQ            2611648                       # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys            3851328                       # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys         3849280                       # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys         2142548481.45631337                       # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys         2141409149.96078181                       # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap               1797544323                       # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap                 14939.45                       # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l1dcaches.prefetcher       707072                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst        69056                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data       463552                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorWriteBytes::writebacks      1825856                       # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l1dcaches.prefetcher 393354198.832267343998                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 38416833.864954419434                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 257880563.191719055176                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorWriteRate::writebacks 1015749632.375611424446                       # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l1dcaches.prefetcher        33092                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst         1217                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data        25868                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorWriteAccesses::writebacks        60145                       # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l1dcaches.prefetcher    460150069                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst     34414981                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data    258758305                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorWriteTotalLat::writebacks  46068811885                       # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l1dcaches.prefetcher     13905.18                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst     28278.54                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data     10003.03                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorWriteAvgLat::writebacks    765962.46                       # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l1dcaches.prefetcher      2117888                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst        77888                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data      1655552                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total      3851328                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst        77888                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total        77888                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::writebacks       178752                       # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::total       178752                       # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l1dcaches.prefetcher        33092                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst         1217                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data        25868                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total        60177                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::writebacks         2793                       # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::total         2793                       # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l1dcaches.prefetcher   1178211183                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst     43330201                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data    921007098                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total   2142548481                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst     43330201                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total     43330201                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::writebacks     99442277                       # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::total     99442277                       # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::writebacks     99442277                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l1dcaches.prefetcher   1178211183                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst     43330201                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data    921007098                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total   2241990759                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts           19370                       # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts          28529                       # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0          246                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1          120                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2           88                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3           43                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4           38                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5            4                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6           27                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7         1133                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8        15697                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9         1111                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10          294                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11          117                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12           15                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13           28                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14          155                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15          254                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0          254                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1          130                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2           96                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3           51                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4           39                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5            5                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6           36                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7         2571                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8        22803                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9         1633                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10          307                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11          139                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12           16                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13           27                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14          185                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15          237                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat          390135855                       # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat         96850000                       # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat     753323355                       # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat           20141.24                       # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat          5000.00                       # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat      38891.24                       # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits          17692                       # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits         26399                       # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate        91.34                       # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate        92.53                       # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples         3798                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean   806.369668                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean   645.608912                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev   348.266848                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127          260      6.85%      6.85% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255          289      7.61%     14.45% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383          153      4.03%     18.48% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511          131      3.45%     21.93% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639          130      3.42%     25.36% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767          104      2.74%     28.09% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895          110      2.90%     30.99% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023           98      2.58%     33.57% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151         2523     66.43%    100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total         3798                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesRead          1239680                       # Total bytes read (Byte)
board.memory.mem_ctrl.dram.bytesWritten       1825856                       # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW         689.651596                       # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW        1015.749632                       # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW            12800.00                       # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil              13.32                       # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead           5.39                       # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite          7.94                       # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate          92.05                       # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy      4262580                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy      2250435                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy     12130860                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy     16610040                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 141367200.000000                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy    719411250                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy     84437760                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy    980470125                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower   545.449460                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE    212061204                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF     59800000                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT   1525684118                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy     22926540                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy     12162975                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy    126170940                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy    132311340                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 141367200.000000                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy    804348660                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy     12911520                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy   1252199175                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower   696.616191                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE     26715115                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF     59800000                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT   1711030207                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles          5398034                       # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.numWorkItemsStarted            0                       # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted            0                       # Number of work items this cpu completed (Count)
board.processor.cores.core.exec_context.thread_0.numInsts      1753641                       # Number of instructions committed (Count)
board.processor.cores.core.exec_context.thread_0.numOps      2308506                       # Number of ops (including micro ops) committed (Count)
board.processor.cores.core.exec_context.thread_0.numIntAluAccesses      2297376                       # Number of integer alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numFpAluAccesses         1465                       # Number of float alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numVecAluAccesses            0                       # Number of vector alu accesses (Count)
board.processor.cores.core.exec_context.thread_0.numCallsReturns        12490                       # Number of times a function call or return occured (Count)
board.processor.cores.core.exec_context.thread_0.numCondCtrlInsts        50635                       # Number of instructions that are conditional controls (Count)
board.processor.cores.core.exec_context.thread_0.numIntInsts      2297376                       # Number of integer instructions (Count)
board.processor.cores.core.exec_context.thread_0.numFpInsts         1465                       # Number of float instructions (Count)
board.processor.cores.core.exec_context.thread_0.numVecInsts            0                       # Number of vector instructions (Count)
board.processor.cores.core.exec_context.thread_0.numIntRegReads      3860134                       # Number of times the integer registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numIntRegWrites      2054055                       # Number of times the integer registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numFpRegReads         1822                       # Number of times the floating registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numFpRegWrites          891                       # Number of times the floating registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numVecRegReads            0                       # Number of times the vector registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numVecRegWrites            0                       # Number of times the vector registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numVecPredRegReads            0                       # Number of times the predicate registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numVecPredRegWrites            0                       # Number of times the predicate registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numCCRegReads       520852                       # Number of times the CC registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numCCRegWrites      1333953                       # Number of times the CC registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numMiscRegReads       854201                       # Number of times the Misc registers were read (Count)
board.processor.cores.core.exec_context.thread_0.numMiscRegWrites            0                       # Number of times the Misc registers were written (Count)
board.processor.cores.core.exec_context.thread_0.numMemRefs       710705                       # Number of memory refs (Count)
board.processor.cores.core.exec_context.thread_0.numLoadInsts       583618                       # Number of load instructions (Count)
board.processor.cores.core.exec_context.thread_0.numStoreInsts       127087                       # Number of store instructions (Count)
board.processor.cores.core.exec_context.thread_0.numIdleCycles     0.003003                       # Number of idle cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.numBusyCycles 5398033.996997                       # Number of busy cycles (Cycle)
board.processor.cores.core.exec_context.thread_0.notIdleFraction     1.000000                       # Percentage of non-idle cycles (Ratio)
board.processor.cores.core.exec_context.thread_0.idleFraction     0.000000                       # Percentage of idle cycles (Ratio)
board.processor.cores.core.exec_context.thread_0.numBranches        65715                       # Number of branches fetched (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::No_OpClass         6337      0.27%      0.27% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IntAlu      1538710     66.65%     66.93% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IntMult        52025      2.25%     69.18% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IntDiv           63      0.00%     69.18% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatAdd          154      0.01%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatCmp            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatCvt            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMult            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMultAcc            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatDiv            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMisc            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatSqrt            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAdd            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAddAcc            0      0.00%     69.19% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAlu          136      0.01%     69.20% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdCmp            0      0.00%     69.20% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdCvt           86      0.00%     69.20% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdMisc          310      0.01%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdMult            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdMultAcc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShift            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShiftAcc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdDiv            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSqrt            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatAdd            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatAlu            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatCmp            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatCvt            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatDiv            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatMisc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatMult            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatMultAcc            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatSqrt            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdReduceAdd            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdReduceAlu            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdReduceCmp            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatReduceAdd            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdFloatReduceCmp            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAes            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdAesMix            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha1Hash            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha1Hash2            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha256Hash            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdSha256Hash2            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShaSigma2            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdShaSigma3            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::SimdPredAlu            0      0.00%     69.21% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::MemRead       583520     25.28%     94.49% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::MemWrite       126579      5.48%     99.97% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMemRead           98      0.00%     99.98% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::FloatMemWrite          508      0.02%    100.00% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::IprAccess            0      0.00%    100.00% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::InstPrefetch            0      0.00%    100.00% # Class of executed instruction. (Count)
board.processor.cores.core.exec_context.thread_0.statExecutedInstType::total      2308526                       # Class of executed instruction. (Count)
board.processor.cores.core.interrupts.clk_domain.clock         5328                       # Clock period in ticks (Tick)
board.processor.cores.core.mmu.dtb.rdAccesses       583622                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses       127088                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses           13                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses           14                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses            0                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses      2324963                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses            0                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses           50                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON   1797545322                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.thread_0.numInsts            0                       # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps            0                       # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs            0                       # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls           16                       # Number of system calls (Count)
board.workload.inst.arm                             0                       # number of arm instructions executed (Count)
board.workload.inst.quiesce                         0                       # number of quiesce instructions executed (Count)

---------- End Simulation Statistics   ----------
