
---------- Begin Simulation Statistics ----------
simSeconds                                   0.000418                       # Number of seconds simulated (Second)
simTicks                                    417884697                       # Number of ticks simulated (Tick)
finalTick                                   417884697                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq                                  1000000000000                       # The number of ticks per simulated second ((Tick/Second))
hostSeconds                                      4.88                       # Real time elapsed on the host (Second)
hostTickRate                                 85668478                       # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory                                    1184540                       # Number of bytes of host memory used (Byte)
simInsts                                      1753641                       # Number of instructions simulated (Count)
simOps                                        2308506                       # Number of ops (including micro ops) simulated (Count)
hostInstRate                                   359497                       # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate                                     473244                       # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data       449739                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total       449739                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data       449739                       # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total       449739                       # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data          469                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total          469                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data          469                       # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total          469                       # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandMissLatency::processor.cores.core.data     24246396                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMissLatency::total     24246396                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::processor.cores.core.data     24246396                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::total     24246396                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data       450208                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total       450208                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data       450208                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total       450208                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data     0.001042                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total     0.001042                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data     0.001042                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total     0.001042                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::processor.cores.core.data 51698.072495                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::total 51698.072495                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::processor.cores.core.data 51698.072495                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total 51698.072495                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.writebacks::writebacks            4                       # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.writebacks::total            4                       # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::processor.cores.core.data          209                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::total          209                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::processor.cores.core.data          209                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::total          209                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::processor.cores.core.data          260                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::total          260                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher          104                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::processor.cores.core.data          260                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::total          364                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::processor.cores.core.data     15419565                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::total     15419565                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher      6333141                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::processor.cores.core.data     15419565                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::total     21752706                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::processor.cores.core.data     0.000578                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::total     0.000578                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher          inf                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::processor.cores.core.data     0.000578                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::total     0.000809                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::processor.cores.core.data 59306.019231                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::total 59306.019231                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 60895.586538                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::processor.cores.core.data 59306.019231                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::total 59760.181319                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.replacements            4                       # number of replacements (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher          104                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::total          104                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher      6333141                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::total      6333141                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::total          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 60895.586538                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::total 60895.586538                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data       322835                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total       322835                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data          288                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total          288                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::processor.cores.core.data     16622361                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::total     16622361                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data       323123                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total       323123                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data     0.000891                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total     0.000891                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::processor.cores.core.data 57716.531250                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::total 57716.531250                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::processor.cores.core.data          159                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::total          159                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::processor.cores.core.data          129                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::total          129                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::processor.cores.core.data      8476848                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::total      8476848                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::processor.cores.core.data     0.000399                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::total     0.000399                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::processor.cores.core.data        65712                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::total        65712                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data       126904                       # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total       126904                       # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data          181                       # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total          181                       # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::processor.cores.core.data      7624035                       # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::total      7624035                       # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data       127085                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total       127085                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data     0.001424                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total     0.001424                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::processor.cores.core.data 42121.740331                       # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::total 42121.740331                       # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::processor.cores.core.data           50                       # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::total           50                       # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::processor.cores.core.data          131                       # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::total          131                       # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::processor.cores.core.data      6942717                       # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::total      6942717                       # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::processor.cores.core.data     0.001031                       # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::total     0.001031                       # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::processor.cores.core.data 52997.839695                       # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::total 52997.839695                       # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses          260                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued          309                       # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUnused            2                       # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful           41                       # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy     0.132686                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage     0.136213                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache           20                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR          185                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate          205                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified          327                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit           13                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand            1                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage           13                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage            0                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse   329.823850                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs       450103                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs          364                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs  1236.546703                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick       128205                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher    98.937201                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data   230.886649                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher     0.193237                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data     0.450950                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total     0.644187                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1022          101                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024          259                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1022::2          101                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0           12                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::1            2                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::2          245                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1022     0.197266                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024     0.505859                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses      3602028                       # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses      3602028                       # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst       172880                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total       172880                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst       172880                       # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total       172880                       # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst          797                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total          797                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst          797                       # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total          797                       # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandMissLatency::processor.cores.core.inst     41088537                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMissLatency::total     41088537                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::processor.cores.core.inst     41088537                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::total     41088537                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst       173677                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total       173677                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst       173677                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total       173677                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst     0.004589                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total     0.004589                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst     0.004589                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total     0.004589                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMissLatency::processor.cores.core.inst 51553.998745                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMissLatency::total 51553.998745                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::processor.cores.core.inst 51553.998745                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::total 51553.998745                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.writebacks::writebacks          130                       # number of writebacks (Count)
board.cache_hierarchy.l1icaches.writebacks::total          130                       # number of writebacks (Count)
board.cache_hierarchy.l1icaches.demandMshrHits::processor.cores.core.inst          186                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1icaches.demandMshrHits::total          186                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1icaches.overallMshrHits::processor.cores.core.inst          186                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1icaches.overallMshrHits::total          186                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::processor.cores.core.inst          611                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::total          611                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::processor.cores.core.inst          611                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::total          611                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::processor.cores.core.inst     32403897                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::total     32403897                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::processor.cores.core.inst     32403897                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::total     32403897                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissRate::processor.cores.core.inst     0.003518                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMshrMissRate::total     0.003518                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::processor.cores.core.inst     0.003518                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::total     0.003518                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::processor.cores.core.inst 53034.201309                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::total 53034.201309                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::processor.cores.core.inst 53034.201309                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::total 53034.201309                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.replacements          130                       # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst       172880                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total       172880                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst          797                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total          797                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::processor.cores.core.inst     41088537                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::total     41088537                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst       173677                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total       173677                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst     0.004589                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total     0.004589                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::processor.cores.core.inst 51553.998745                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::total 51553.998745                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.mshrHits::processor.cores.core.inst          186                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrHits::total          186                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::processor.cores.core.inst          611                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::total          611                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::processor.cores.core.inst     32403897                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::total     32403897                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::processor.cores.core.inst     0.003518                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::total     0.003518                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::processor.cores.core.inst 53034.201309                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::total 53034.201309                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses          611                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued            0                       # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful            0                       # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy          nan                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage            0                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache            0                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR            0                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate            0                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified            0                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand            0                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage            0                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage            0                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse   442.664556                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs       173491                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs          611                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs   283.945990                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick        69597                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst   442.664556                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst     0.864579                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total     0.864579                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024          481                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0           49                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::1           11                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::2          421                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024     0.939453                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses      1390027                       # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses      1390027                       # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp          844                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackDirty            1                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackClean          133                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq          131                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp          131                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq          844                       # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port         1352                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::total         1352                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port          732                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::total          732                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total         2084                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port        47424                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::total        47424                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port        23552                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::total        23552                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total        70976                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops                 0                       # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic            0                       # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples          975                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows            0      0.00%      0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0          975    100.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total          975                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy       427781                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy       511687                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy       301515                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests         1109                       # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests          134                       # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops            0                       # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock                            333                       # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage             1                       # Voltage in Volts (Volt)
board.memory.mem_ctrl.avgPriority_writebacks::samples       134.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l1dcaches.prefetcher::samples       104.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples       611.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples       260.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000018750                       # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.000638205288                       # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds            7                       # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds            7                       # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState           2088                       # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState           105                       # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs                    975                       # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs                   134                       # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts                  975                       # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts                 134                       # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ                 0                       # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts                0                       # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen                  2.36                       # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen                 22.19                       # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry                    0                       # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry                    0                       # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6              975                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6             134                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0                494                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1                263                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2                114                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3                 58                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4                 26                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5                  6                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6                  3                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7                  3                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8                  2                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9                  3                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10                 2                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11                 1                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17                 7                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18                 8                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19                 8                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20                 8                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21                 8                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22                 8                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23                 7                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24                 7                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25                 7                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26                 7                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27                 7                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28                 7                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29                 7                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30                 7                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31                 7                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32                 7                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdPerTurnAround::samples            7                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::mean   138.285714                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::gmean    48.363300                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::stdev   282.243816                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::0-31            4     57.14%     57.14% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::32-63            2     28.57%     85.71% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::768-799            1     14.29%    100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::total            7                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.wrPerTurnAround::samples            7                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::mean           16                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::gmean    16.000000                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::16            7    100.00%    100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::total            7                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.bytesReadWrQ                  0                       # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys              62400                       # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys            8576                       # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys         149323486.71289104                       # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys         20522407.40464349                       # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap                417876372                       # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap                376804.66                       # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l1dcaches.prefetcher         6656                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst        39104                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data        16640                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorWriteBytes::writebacks         7168                       # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l1dcaches.prefetcher 15927838.582708377391                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 93576051.673411712050                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 39819596.456770941615                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorWriteRate::writebacks 17153056.935224406421                       # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l1dcaches.prefetcher          104                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst          611                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data          260                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorWriteAccesses::writebacks          134                       # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l1dcaches.prefetcher      3852028                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst     17836714                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data      9224778                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorWriteTotalLat::writebacks   9243063011                       # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l1dcaches.prefetcher     37038.73                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst     29192.66                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data     35479.92                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorWriteAvgLat::writebacks  68978082.17                       # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l1dcaches.prefetcher         6656                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst        39104                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data        16640                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total        62400                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst        39104                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total        39104                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::writebacks           64                       # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::total           64                       # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l1dcaches.prefetcher          104                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst          611                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data          260                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total          975                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::writebacks            1                       # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::total            1                       # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l1dcaches.prefetcher     15927839                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst     93576052                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data     39819596                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total    149323487                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst     93576052                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total     93576052                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::writebacks       153152                       # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::total       153152                       # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::writebacks       153152                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l1dcaches.prefetcher     15927839                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst     93576052                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data     39819596                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total    149476639                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts             975                       # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts            112                       # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0          109                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1           91                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2           37                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3           30                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4           31                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5            6                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6            6                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7           48                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8           93                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9           74                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10          134                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11           79                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12           10                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13           20                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14           64                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15          143                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0            8                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1           25                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2           13                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3            2                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4           14                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6            1                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7            3                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8            1                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10           28                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11            5                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12            0                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13            6                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14            5                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15            1                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat           12632270                       # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat          4875000                       # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat      30913520                       # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat           12956.17                       # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat          5000.00                       # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat      31706.17                       # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits            754                       # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits            80                       # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate        77.33                       # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate        71.43                       # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples          245                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean   280.032653                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean   173.485786                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev   298.094933                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127           85     34.69%     34.69% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255           70     28.57%     63.27% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383           30     12.24%     75.51% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511           16      6.53%     82.04% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639            6      2.45%     84.49% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767           10      4.08%     88.57% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895            4      1.63%     90.20% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023            4      1.63%     91.84% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151           20      8.16%    100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total          245                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesRead            62400                       # Total bytes read (Byte)
board.memory.mem_ctrl.dram.bytesWritten          7168                       # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW         149.323487                       # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW          17.153057                       # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW            12800.00                       # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil               1.30                       # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead           1.17                       # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite          0.13                       # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate          76.72                       # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy       742560                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy       387090                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy      2556120                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy       344520                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 32575920.000000                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy     30620400                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy    134682240                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy    201908850                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower   483.168806                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE    349891080                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF     13780000                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT     54213617                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy      1063860                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy       542685                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy      4405380                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy       240120                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 32575920.000000                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy     50462100                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy    117973440                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy    207263505                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower   495.982520                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE    306237257                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF     13780000                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT     97867440                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles          1254910                       # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.numWorkItemsStarted            0                       # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted            0                       # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded         2381885                       # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.nonSpecInstsAdded            6                       # Number of non-speculative instructions added to the IQ (Count)
board.processor.cores.core.instsIssued        2344004                       # Number of instructions issued (Count)
board.processor.cores.core.squashedInstsIssued          353                       # Number of squashed instructions issued (Count)
board.processor.cores.core.squashedInstsExamined        73371                       # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.cores.core.squashedOperandsExamined       188693                       # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.cores.core.squashedNonSpecRemoved            6                       # Number of squashed non-spec instructions that were removed (Count)
board.processor.cores.core.numIssuedDist::samples      1208981                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean     1.938826                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev     1.272368                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows            0      0.00%      0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0        89328      7.39%      7.39% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1       419049     34.66%     42.05% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2       379608     31.40%     73.45% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::3       199726     16.52%     89.97% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::4        73774      6.10%     96.07% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::5        23888      1.98%     98.05% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::6        15466      1.28%     99.33% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::7         5907      0.49%     99.82% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::8         2235      0.18%    100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows            0      0.00%    100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value            0                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value            8                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total      1208981                       # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu         2193     86.82%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc            0      0.00%     86.82% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu           12      0.48%     87.29% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp            0      0.00%     87.29% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt            1      0.04%     87.33% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc            3      0.12%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu            0      0.00%     87.45% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead          165      6.53%     93.98% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite          125      4.95%     98.93% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead            9      0.36%     99.29% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite           18      0.71%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass         7784      0.33%      0.33% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu      1562713     66.67%     67.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult        52442      2.24%     69.24% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv           77      0.00%     69.24% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd          171      0.01%     69.25% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp            0      0.00%     69.25% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt            0      0.00%     69.25% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult            0      0.00%     69.25% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc            0      0.00%     69.25% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv            0      0.00%     69.25% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc            0      0.00%     69.25% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt            0      0.00%     69.25% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd            0      0.00%     69.25% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc            0      0.00%     69.25% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu          219      0.01%     69.26% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp            0      0.00%     69.26% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt           88      0.00%     69.26% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc          322      0.01%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu            0      0.00%     69.28% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead       590344     25.19%     94.46% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite       129039      5.51%     99.97% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead          181      0.01%     99.97% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite          624      0.03%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total      2344004                       # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate         1.867866                       # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy                2526                       # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate        0.001078                       # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads      5896238                       # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites      2453117                       # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses      2339793                       # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads         3624                       # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites         2194                       # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses         1706                       # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads            0                       # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites            0                       # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses            0                       # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses      2336920                       # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses         1826                       # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses            0                       # Number of vector alu accesses (Count)
board.processor.cores.core.numInsts           2342303                       # Number of executed instructions (Count)
board.processor.cores.core.numLoadInsts        590197                       # Number of load instructions executed (Count)
board.processor.cores.core.numSquashedInsts         1695                       # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp                   0                       # Number of swp insts executed (Count)
board.processor.cores.core.numNop                   0                       # Number of nop insts executed (Count)
board.processor.cores.core.numRefs             719499                       # Number of memory reference insts executed (Count)
board.processor.cores.core.numBranches          67935                       # Number of branches executed (Count)
board.processor.cores.core.numStoreInsts       129302                       # Number of stores executed (Count)
board.processor.cores.core.numRate           1.866511                       # Inst execution rate ((Count/Cycle))
board.processor.cores.core.timesIdled             390                       # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.cores.core.idleCycles           45929                       # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.cores.core.committedInsts      1753641                       # Number of Instructions Simulated (Count)
board.processor.cores.core.committedOps       2308506                       # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.cpi               0.715603                       # CPI: Cycles Per Instruction ((Cycle/Count))
board.processor.cores.core.totalCpi          0.715603                       # CPI: Total CPI of All Threads ((Cycle/Count))
board.processor.cores.core.ipc               1.397424                       # IPC: Instructions Per Cycle ((Count/Cycle))
board.processor.cores.core.totalIpc          1.397424                       # IPC: Total IPC of All Threads ((Count/Cycle))
board.processor.cores.core.intRegfileReads      3893453                       # Number of integer regfile reads (Count)
board.processor.cores.core.intRegfileWrites      2080924                       # Number of integer regfile writes (Count)
board.processor.cores.core.fpRegfileReads         2110                       # Number of floating regfile reads (Count)
board.processor.cores.core.fpRegfileWrites         1041                       # Number of floating regfile writes (Count)
board.processor.cores.core.ccRegfileReads       525354                       # number of cc regfile reads (Count)
board.processor.cores.core.ccRegfileWrites      1338645                       # number of cc regfile writes (Count)
board.processor.cores.core.miscRegfileReads       870092                       # number of misc regfile reads (Count)
board.processor.cores.core.MemDepUnit__0.insertedLoads       595973                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores       131295                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads       164190                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores        54741                       # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads            0                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores            0                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads            0                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores            0                       # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads            0                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores            0                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads            0                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores            0                       # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads            0                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores            0                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads            0                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores            0                       # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups        73907                       # Number of BP lookups (Count)
board.processor.cores.core.branchPred.condPredicted        56015                       # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condIncorrect         3258                       # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.BTBLookups        63361                       # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBHits        62322                       # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio     0.983602                       # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.RASUsed         6932                       # Number of times the RAS was used to get a target. (Count)
board.processor.cores.core.branchPred.RASIncorrect            0                       # Number of incorrect RAS predictions. (Count)
board.processor.cores.core.branchPred.indirectLookups          646                       # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits           57                       # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses          589                       # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted          134                       # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.commit.commitSquashedInsts        72901                       # The number of squashed insts skipped by commit (Count)
board.processor.cores.core.commit.branchMispredicts         3131                       # The number of times a branch was mispredicted (Count)
board.processor.cores.core.commit.numCommittedDist::samples      1197793                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean     1.927300                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev     2.084745                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows            0      0.00%      0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0       207676     17.34%     17.34% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1       515004     43.00%     60.33% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2       216253     18.05%     78.39% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::3        87728      7.32%     85.71% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::4        37019      3.09%     88.80% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::5        12217      1.02%     89.82% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::6        42047      3.51%     93.33% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::7         2423      0.20%     93.54% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::8        77426      6.46%    100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows            0      0.00%    100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value            0                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value            8                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total      1197793                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.instsCommitted      1753641                       # Number of instructions committed (Count)
board.processor.cores.core.commit.opsCommitted      2308506                       # Number of ops (including micro ops) committed (Count)
board.processor.cores.core.commit.memRefs       710701                       # Number of memory references committed (Count)
board.processor.cores.core.commit.loads        583617                       # Number of loads committed (Count)
board.processor.cores.core.commit.amos              0                       # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars            0                       # Number of memory barriers committed (Count)
board.processor.cores.core.commit.branches        65715                       # Number of branches committed (Count)
board.processor.cores.core.commit.vectorInstructions            0                       # Number of committed Vector instructions. (Count)
board.processor.cores.core.commit.floating         1464                       # Number of committed floating point instructions. (Count)
board.processor.cores.core.commit.integer      2297372                       # Number of committed integer instructions. (Count)
board.processor.cores.core.commit.functionCalls         6247                       # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass         6337      0.27%      0.27% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu      1538694     66.65%     66.93% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult        52025      2.25%     69.18% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv           63      0.00%     69.18% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd          154      0.01%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu          136      0.01%     69.20% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp            0      0.00%     69.20% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt           86      0.00%     69.20% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc          310      0.01%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead       583519     25.28%     94.49% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite       126577      5.48%     99.97% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead           98      0.00%     99.98% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite          507      0.02%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total      2308506                       # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples        77426                       # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.decode.idleCycles       116188                       # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.blockedCycles       786342                       # Number of cycles decode is blocked (Cycle)
board.processor.cores.core.decode.runCycles        48924                       # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.unblockCycles       254335                       # Number of cycles decode is unblocking (Cycle)
board.processor.cores.core.decode.squashCycles         3192                       # Number of cycles decode is squashing (Cycle)
board.processor.cores.core.decode.branchResolved        60004                       # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.branchMispred          291                       # Number of times decode detected a branch misprediction (Count)
board.processor.cores.core.decode.decodedInsts      2406366                       # Number of instructions handled by decode (Count)
board.processor.cores.core.decode.squashedInsts         1474                       # Number of squashed instructions handled by decode (Count)
board.processor.cores.core.fetch.icacheStallCycles        21744                       # Number of cycles fetch is stalled on an Icache miss (Cycle)
board.processor.cores.core.fetch.insts        1901221                       # Number of instructions fetch has processed (Count)
board.processor.cores.core.fetch.branches        73907                       # Number of branches that fetch encountered (Count)
board.processor.cores.core.fetch.predictedBranches        69311                       # Number of branches that fetch has predicted taken (Count)
board.processor.cores.core.fetch.cycles       1182546                       # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles         6956                       # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.miscStallCycles          174                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
board.processor.cores.core.fetch.pendingTrapStallCycles         1039                       # Number of stall cycles due to pending traps (Cycle)
board.processor.cores.core.fetch.cacheLines       173677                       # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.icacheSquashes          396                       # Number of outstanding Icache misses that were squashed (Count)
board.processor.cores.core.fetch.nisnDist::samples      1208981                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean     2.075509                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev     3.110641                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows            0      0.00%      0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0       757109     62.62%     62.62% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1        49955      4.13%     66.76% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2        25824      2.14%     68.89% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::3        50394      4.17%     73.06% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::4        24822      2.05%     75.11% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::5        58722      4.86%     79.97% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::6        20666      1.71%     81.68% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::7        32340      2.67%     84.35% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::8       189149     15.65%    100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows            0      0.00%    100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value            0                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value            8                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total      1208981                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.branchRate     0.058894                       # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetch.rate        1.515026                       # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.iew.idleCycles            0                       # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles         3192                       # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles         9419                       # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles          124                       # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts      2381891                       # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts           80                       # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts       595973                       # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts       131295                       # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts            3                       # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents           12                       # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents          105                       # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents           54                       # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect         2398                       # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect          928                       # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts         3326                       # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit      2342123                       # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount      2341499                       # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst      1965839                       # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst      3558341                       # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate        1.865870                       # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout      0.552459                       # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock         5328                       # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads       267010                       # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads        12356                       # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation           54                       # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores         4211                       # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads            7                       # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache            0                       # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.lsq0.loadToUse::samples       583617                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::mean     2.143279                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::stdev     3.237210                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::0-9       583456     99.97%     99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::10-19            5      0.00%     99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::20-29            2      0.00%     99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::30-39            1      0.00%     99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::70-79            2      0.00%     99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::80-89            2      0.00%     99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::90-99            2      0.00%     99.97% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::100-109            2      0.00%     99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::110-119            5      0.00%     99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::120-129            3      0.00%     99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::130-139           29      0.00%     99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::140-149           10      0.00%     99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::150-159            7      0.00%     99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::160-169            3      0.00%     99.98% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::170-179           22      0.00%     99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::180-189            3      0.00%     99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::190-199            4      0.00%     99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::200-209            3      0.00%     99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::210-219           20      0.00%     99.99% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::220-229           10      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::230-239            4      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::240-249            2      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::250-259            1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::260-269            1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::270-279            2      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::280-289            1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::290-299            1      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::overflows           14      0.00%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::min_value            2                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::max_value          453                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::total       583617                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.mmu.dtb.rdAccesses       590206                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses       129304                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses           81                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses           28                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses            0                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses       173857                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses            0                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses          236                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON    417884697                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.squashCycles         3192                       # Number of cycles rename is squashing (Cycle)
board.processor.cores.core.rename.idleCycles       201266                       # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.blockCycles        45843                       # Number of cycles rename is blocking (Cycle)
board.processor.cores.core.rename.serializeStallCycles           29                       # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles       217618                       # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.unblockCycles       741033                       # Number of cycles rename is unblocking (Cycle)
board.processor.cores.core.rename.renamedInsts      2388991                       # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.ROBFullEvents          795                       # Number of times rename has blocked due to ROB full (Count)
board.processor.cores.core.rename.IQFullEvents       520682                       # Number of times rename has blocked due to IQ full (Count)
board.processor.cores.core.rename.LQFullEvents       407786                       # Number of times rename has blocked due to LQ full (Count)
board.processor.cores.core.rename.SQFullEvents         3530                       # Number of times rename has blocked due to SQ full (Count)
board.processor.cores.core.rename.renamedOperands      5637194                       # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups      9201681                       # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups      3984437                       # Number of integer rename lookups (Count)
board.processor.cores.core.rename.fpLookups         2231                       # Number of floating rename lookups (Count)
board.processor.cores.core.rename.committedMaps      5466916                       # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.undoneMaps       170258                       # Number of HB maps that are undone due to squashing (Count)
board.processor.cores.core.rename.serializing            3                       # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing            3                       # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts      1319983                       # count of insts added to the skid buffer (Count)
board.processor.cores.core.rob.reads          3501527                       # The number of ROB reads (Count)
board.processor.cores.core.rob.writes         4774046                       # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts      1753641                       # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps      2308506                       # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs            0                       # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls           16                       # Number of system calls (Count)
board.workload.inst.arm                             0                       # number of arm instructions executed (Count)
board.workload.inst.quiesce                         0                       # number of quiesce instructions executed (Count)

---------- End Simulation Statistics   ----------
