
---------- Begin Simulation Statistics ----------
simSeconds                                   0.000999                       # Number of seconds simulated (Second)
simTicks                                    998991009                       # Number of ticks simulated (Tick)
finalTick                                   998991009                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset) (Tick)
simFreq                                  1000000000000                       # The number of ticks per simulated second ((Tick/Second))
hostSeconds                                      6.34                       # Real time elapsed on the host (Second)
hostTickRate                                157479340                       # The number of ticks simulated per host second (ticks/s) ((Tick/Second))
hostMemory                                    1183520                       # Number of bytes of host memory used (Byte)
simInsts                                      1753641                       # Number of instructions simulated (Count)
simOps                                        2308506                       # Number of ops (including micro ops) simulated (Count)
hostInstRate                                   276436                       # Simulator instruction rate (inst/s) ((Count/Second))
hostOpRate                                     363902                       # Simulator op (including micro ops) rate (op/s) ((Count/Second))
board.cache_hierarchy.dptw_caches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.dptw_caches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.dptw_caches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.dptw_caches.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.dptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.dptw_caches.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.dptw_caches.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.dptw_caches.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.dptw_caches.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.dptw_caches.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.dptw_caches.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.dptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.iptw_caches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.iptw_caches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.iptw_caches.replacements            0                       # number of replacements (Count)
board.cache_hierarchy.iptw_caches.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.iptw_caches.tags.tagsInUse            0                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.iptw_caches.tags.totalRefs            0                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.sampledRefs            0                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.iptw_caches.tags.avgRefs          nan                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.iptw_caches.tags.warmupTick            0                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.iptw_caches.tags.tagAccesses            0                       # Number of tag accesses (Count)
board.cache_hierarchy.iptw_caches.tags.dataAccesses            0                       # Number of data accesses (Count)
board.cache_hierarchy.iptw_caches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.demandHits::processor.cores.core.data       425634                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.demandHits::total       425634                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::processor.cores.core.data       425634                       # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.overallHits::total       425634                       # number of overall hits (Count)
board.cache_hierarchy.l1dcaches.demandMisses::processor.cores.core.data        29618                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.demandMisses::total        29618                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::processor.cores.core.data        29618                       # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.overallMisses::total        29618                       # number of overall misses (Count)
board.cache_hierarchy.l1dcaches.demandMissLatency::processor.cores.core.data    716151465                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMissLatency::total    716151465                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::processor.cores.core.data    716151465                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMissLatency::total    716151465                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandAccesses::processor.cores.core.data       455252                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandAccesses::total       455252                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::processor.cores.core.data       455252                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.overallAccesses::total       455252                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1dcaches.demandMissRate::processor.cores.core.data     0.065058                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMissRate::total     0.065058                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::processor.cores.core.data     0.065058                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMissRate::total     0.065058                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::processor.cores.core.data 24179.602438                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMissLatency::total 24179.602438                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::processor.cores.core.data 24179.602438                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMissLatency::total 24179.602438                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1dcaches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1dcaches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1dcaches.writebacks::writebacks        51169                       # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.writebacks::total        51169                       # number of writebacks (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::processor.cores.core.data         1612                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrHits::total         1612                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::processor.cores.core.data         1612                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.overallMshrHits::total         1612                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::processor.cores.core.data        28006                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMisses::total        28006                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::cache_hierarchy.l1dcaches.prefetcher        23179                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::processor.cores.core.data        28006                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.overallMshrMisses::total        51185                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::processor.cores.core.data    643583772                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissLatency::total    643583772                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher    648563632                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::processor.cores.core.data    643583772                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.overallMshrMissLatency::total   1292147404                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::processor.cores.core.data     0.061518                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandMshrMissRate::total     0.061518                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::cache_hierarchy.l1dcaches.prefetcher          inf                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::processor.cores.core.data     0.061518                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.overallMshrMissRate::total     0.112432                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::processor.cores.core.data 22980.210383                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.demandAvgMshrMissLatency::total 22980.210383                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 27980.656284                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::processor.cores.core.data 22980.210383                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.overallAvgMshrMissLatency::total 25244.649878                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.replacements        51169                       # number of replacements (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::cache_hierarchy.l1dcaches.prefetcher        23179                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMisses::total        23179                       # number of HardPFReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::cache_hierarchy.l1dcaches.prefetcher    648563632                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissLatency::total    648563632                       # number of HardPFReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::cache_hierarchy.l1dcaches.prefetcher          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.mshrMissRate::total          inf                       # mshr miss rate for HardPFReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::cache_hierarchy.l1dcaches.prefetcher 27980.656284                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.HardPFReq.avgMshrMissLatency::total 27980.656284                       # average HardPFReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.hits::processor.cores.core.data       299175                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.hits::total       299175                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::processor.cores.core.data        28992                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.misses::total        28992                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::processor.cores.core.data    683793189                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.missLatency::total    683793189                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::processor.cores.core.data       328167                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.accesses::total       328167                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::processor.cores.core.data     0.088345                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.missRate::total     0.088345                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::processor.cores.core.data 23585.581850                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMissLatency::total 23585.581850                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::processor.cores.core.data         1560                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrHits::total         1560                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::processor.cores.core.data        27432                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMisses::total        27432                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::processor.cores.core.data    612170883                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissLatency::total    612170883                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::processor.cores.core.data     0.083592                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.mshrMissRate::total     0.083592                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::processor.cores.core.data 22315.940617                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.ReadReq.avgMshrMissLatency::total 22315.940617                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.hits::processor.cores.core.data       126459                       # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.hits::total       126459                       # number of WriteReq hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::processor.cores.core.data          626                       # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.misses::total          626                       # number of WriteReq misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::processor.cores.core.data     32358276                       # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.missLatency::total     32358276                       # number of WriteReq miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::processor.cores.core.data       127085                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.accesses::total       127085                       # number of WriteReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::processor.cores.core.data     0.004926                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.missRate::total     0.004926                       # miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::processor.cores.core.data 51690.536741                       # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMissLatency::total 51690.536741                       # average WriteReq miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::processor.cores.core.data           52                       # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrHits::total           52                       # number of WriteReq MSHR hits (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::processor.cores.core.data          574                       # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMisses::total          574                       # number of WriteReq MSHR misses (Count)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::processor.cores.core.data     31412889                       # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissLatency::total     31412889                       # number of WriteReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::processor.cores.core.data     0.004517                       # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.mshrMissRate::total     0.004517                       # mshr miss rate for WriteReq accesses (Ratio)
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::processor.cores.core.data 54726.287456                       # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.WriteReq.avgMshrMissLatency::total 54726.287456                       # average WriteReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1dcaches.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.prefetcher.demandMshrMisses        28006                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIssued        26715                       # number of hwpf issued (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUnused         5258                       # number of HardPF blocks evicted w/o reference (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUseful        16834                       # number of useful prefetch (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1dcaches.prefetcher.accuracy     0.630133                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.coverage     0.375424                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInCache         2701                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInMSHR          835                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfLate         3536                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfIdentified        26786                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfBufferHit           53                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedDemand            1                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfSpanPage         1346                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.pfUsefulSpanPage            0                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1dcaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1dcaches.tags.tagsInUse    15.994411                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1dcaches.tags.totalRefs       476819                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.sampledRefs        51185                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1dcaches.tags.avgRefs     9.315600                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1dcaches.tags.warmupTick       128205                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1dcaches.tags.occupancies::cache_hierarchy.l1dcaches.prefetcher     5.352412                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.occupancies::processor.cores.core.data    10.641999                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::cache_hierarchy.l1dcaches.prefetcher     0.334526                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::processor.cores.core.data     0.665125                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.avgOccs::total     0.999651                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1dcaches.tags.occupanciesTaskId::1024           16                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1dcaches.tags.ageTaskId_1024::0           16                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1dcaches.tags.ratioOccsTaskId::1024            1                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1dcaches.tags.tagAccesses      3693201                       # Number of tag accesses (Count)
board.cache_hierarchy.l1dcaches.tags.dataAccesses      3693201                       # Number of data accesses (Count)
board.cache_hierarchy.l1dcaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.demandHits::processor.cores.core.inst       170575                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.demandHits::total       170575                       # number of demand (read+write) hits (Count)
board.cache_hierarchy.l1icaches.overallHits::processor.cores.core.inst       170575                       # number of overall hits (Count)
board.cache_hierarchy.l1icaches.overallHits::total       170575                       # number of overall hits (Count)
board.cache_hierarchy.l1icaches.demandMisses::processor.cores.core.inst         1775                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.demandMisses::total         1775                       # number of demand (read+write) misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::processor.cores.core.inst         1775                       # number of overall misses (Count)
board.cache_hierarchy.l1icaches.overallMisses::total         1775                       # number of overall misses (Count)
board.cache_hierarchy.l1icaches.demandMissLatency::processor.cores.core.inst     99333900                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMissLatency::total     99333900                       # number of demand (read+write) miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::processor.cores.core.inst     99333900                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMissLatency::total     99333900                       # number of overall miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandAccesses::processor.cores.core.inst       172350                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandAccesses::total       172350                       # number of demand (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::processor.cores.core.inst       172350                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.overallAccesses::total       172350                       # number of overall (read+write) accesses (Count)
board.cache_hierarchy.l1icaches.demandMissRate::processor.cores.core.inst     0.010299                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMissRate::total     0.010299                       # miss rate for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::processor.cores.core.inst     0.010299                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMissRate::total     0.010299                       # miss rate for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMissLatency::processor.cores.core.inst 55962.760563                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMissLatency::total 55962.760563                       # average overall miss latency in ticks ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::processor.cores.core.inst 55962.760563                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMissLatency::total 55962.760563                       # average overall miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.blockedCycles::no_mshrs            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCycles::no_targets            0                       # number of cycles access was blocked (Cycle)
board.cache_hierarchy.l1icaches.blockedCauses::no_mshrs            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.blockedCauses::no_targets            0                       # number of times access was blocked (Count)
board.cache_hierarchy.l1icaches.avgBlocked::no_mshrs          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.avgBlocked::no_targets          nan                       # average number of cycles each access was blocked ((Cycle/Count))
board.cache_hierarchy.l1icaches.writebacks::writebacks         1497                       # number of writebacks (Count)
board.cache_hierarchy.l1icaches.writebacks::total         1497                       # number of writebacks (Count)
board.cache_hierarchy.l1icaches.demandMshrHits::processor.cores.core.inst          262                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1icaches.demandMshrHits::total          262                       # number of demand (read+write) MSHR hits (Count)
board.cache_hierarchy.l1icaches.overallMshrHits::processor.cores.core.inst          262                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1icaches.overallMshrHits::total          262                       # number of overall MSHR hits (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::processor.cores.core.inst         1513                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMisses::total         1513                       # number of demand (read+write) MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::processor.cores.core.inst         1513                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.overallMshrMisses::total         1513                       # number of overall MSHR misses (Count)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::processor.cores.core.inst     86598981                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissLatency::total     86598981                       # number of demand (read+write) MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::processor.cores.core.inst     86598981                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.overallMshrMissLatency::total     86598981                       # number of overall MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.demandMshrMissRate::processor.cores.core.inst     0.008779                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.demandMshrMissRate::total     0.008779                       # mshr miss ratio for demand accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::processor.cores.core.inst     0.008779                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.overallMshrMissRate::total     0.008779                       # mshr miss ratio for overall accesses (Ratio)
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::processor.cores.core.inst 57236.603437                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.demandAvgMshrMissLatency::total 57236.603437                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::processor.cores.core.inst 57236.603437                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.overallAvgMshrMissLatency::total 57236.603437                       # average overall mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.replacements         1497                       # number of replacements (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::processor.cores.core.inst       170575                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.hits::total       170575                       # number of ReadReq hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::processor.cores.core.inst         1775                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.misses::total         1775                       # number of ReadReq misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::processor.cores.core.inst     99333900                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.missLatency::total     99333900                       # number of ReadReq miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.accesses::processor.cores.core.inst       172350                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.accesses::total       172350                       # number of ReadReq accesses(hits+misses) (Count)
board.cache_hierarchy.l1icaches.ReadReq.missRate::processor.cores.core.inst     0.010299                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.missRate::total     0.010299                       # miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::processor.cores.core.inst 55962.760563                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMissLatency::total 55962.760563                       # average ReadReq miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.mshrHits::processor.cores.core.inst          262                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrHits::total          262                       # number of ReadReq MSHR hits (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::processor.cores.core.inst         1513                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMisses::total         1513                       # number of ReadReq MSHR misses (Count)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::processor.cores.core.inst     86598981                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissLatency::total     86598981                       # number of ReadReq MSHR miss ticks (Tick)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::processor.cores.core.inst     0.008779                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.mshrMissRate::total     0.008779                       # mshr miss rate for ReadReq accesses (Ratio)
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::processor.cores.core.inst 57236.603437                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.ReadReq.avgMshrMissLatency::total 57236.603437                       # average ReadReq mshr miss latency ((Tick/Count))
board.cache_hierarchy.l1icaches.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.prefetcher.demandMshrMisses         1513                       # demands not covered by prefetchs (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIssued            0                       # number of hwpf issued (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUseful            0                       # number of useful prefetch (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulButMiss            0                       # number of hit on prefetch but cache block is not in an usable state (Count)
board.cache_hierarchy.l1icaches.prefetcher.accuracy          nan                       # accuracy of the prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.coverage            0                       # coverage brought by this prefetcher (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInCache            0                       # number of prefetches hitting in cache (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInMSHR            0                       # number of prefetches hitting in a MSHR (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfHitInWB            0                       # number of prefetches hit in the Write Buffer (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfLate            0                       # number of late prefetches (hitting in cache, MSHR or WB) (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfIdentified            0                       # number of prefetch candidates identified (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedDemand            0                       # number of prefetches dropped due to a demand for the same address (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfSpanPage            0                       # number of prefetches that crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.pfUsefulSpanPage            0                       # number of prefetches that is useful and crossed the page (Count)
board.cache_hierarchy.l1icaches.prefetcher.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.l1icaches.tags.tagsInUse    15.993835                       # Average ticks per tags in use ((Tick/Count))
board.cache_hierarchy.l1icaches.tags.totalRefs       172088                       # Total number of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.sampledRefs         1513                       # Sample count of references to valid blocks. (Count)
board.cache_hierarchy.l1icaches.tags.avgRefs   113.739590                       # Average number of references to valid blocks. ((Count/Count))
board.cache_hierarchy.l1icaches.tags.warmupTick        69597                       # The tick when the warmup percentage was hit. (Tick)
board.cache_hierarchy.l1icaches.tags.occupancies::processor.cores.core.inst    15.993835                       # Average occupied blocks per tick, per requestor ((Count/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::processor.cores.core.inst     0.999615                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.avgOccs::total     0.999615                       # Average percentage of cache occupancy ((Ratio/Tick))
board.cache_hierarchy.l1icaches.tags.occupanciesTaskId::1024           16                       # Occupied blocks per task id (Count)
board.cache_hierarchy.l1icaches.tags.ageTaskId_1024::0           16                       # Occupied blocks per task id, per block age (Count)
board.cache_hierarchy.l1icaches.tags.ratioOccsTaskId::1024            1                       # Ratio of occupied blocks and all blocks, per task id (Ratio)
board.cache_hierarchy.l1icaches.tags.tagAccesses      1380313                       # Number of tag accesses (Count)
board.cache_hierarchy.l1icaches.tags.dataAccesses      1380313                       # Number of data accesses (Count)
board.cache_hierarchy.l1icaches.tags.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.transDist::ReadResp        52124                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackDirty         2808                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::WritebackClean        49858                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExReq          574                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadExResp          574                       # Transaction distribution (Count)
board.cache_hierarchy.membus.transDist::ReadSharedReq        52124                       # Transaction distribution (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port         4523                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1icaches.mem_side_port::total         4523                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port       153539                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount_board.cache_hierarchy.l1dcaches.mem_side_port::total       153539                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktCount::total       158062                       # Packet count per connected requestor and responder (Count)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::board.memory.mem_ctrl.port       192640                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1icaches.mem_side_port::total       192640                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::board.memory.mem_ctrl.port      6550656                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize_board.cache_hierarchy.l1dcaches.mem_side_port::total      6550656                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.pktSize::total      6743296                       # Cumulative packet size per connected requestor and responder (Byte)
board.cache_hierarchy.membus.snoops                 0                       # Total snoops (Count)
board.cache_hierarchy.membus.snoopTraffic            0                       # Total snoop traffic (Byte)
board.cache_hierarchy.membus.snoopFanout::samples        52698                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::mean            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::stdev            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::underflows            0      0.00%      0.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::0        52698    100.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::1            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::2            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::3            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::4            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::overflows            0      0.00%    100.00% # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::min_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::max_value            0                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.snoopFanout::total        52698                       # Request fanout histogram (Count)
board.cache_hierarchy.membus.badaddr_responder.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.cache_hierarchy.membus.reqLayer0.occupancy     52815303                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.reqLayer0.utilization          0.1                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer1.occupancy      1292910                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer1.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.respLayer2.occupancy     43864688                       # Layer occupancy (ticks) (Tick)
board.cache_hierarchy.membus.respLayer2.utilization          0.0                       # Layer utilization (Ratio)
board.cache_hierarchy.membus.snoop_filter.totRequests       105364                       # Total number of requests made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleRequests        52666                       # Number of requests hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiRequests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.totSnoops            0                       # Total number of snoops made to the snoop filter. (Count)
board.cache_hierarchy.membus.snoop_filter.hitSingleSnoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data. (Count)
board.cache_hierarchy.membus.snoop_filter.hitMultiSnoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. (Count)
board.clk_domain.clock                            333                       # Clock period in ticks (Tick)
board.clk_domain.voltage_domain.voltage             1                       # Voltage in Volts (Volt)
board.memory.mem_ctrl.avgPriority_writebacks::samples     17303.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_cache_hierarchy.l1dcaches.prefetcher::samples      5650.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.inst::samples      1335.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.avgPriority_processor.cores.core.data::samples      4805.00                       # Average QoS priority value for accepted requests (Count)
board.memory.mem_ctrl.priorityMinLatency 0.000000018750                       # per QoS priority minimum request to response latency (Second)
board.memory.mem_ctrl.priorityMaxLatency 0.000025828248                       # per QoS priority maximum request to response latency (Second)
board.memory.mem_ctrl.numReadWriteTurnArounds         1046                       # Number of turnarounds from READ to WRITE (Count)
board.memory.mem_ctrl.numWriteReadTurnArounds         1046                       # Number of turnarounds from WRITE to READ (Count)
board.memory.mem_ctrl.numStayReadState          69194                       # Number of times bus staying in READ state (Count)
board.memory.mem_ctrl.numStayWriteState         16302                       # Number of times bus staying in WRITE state (Count)
board.memory.mem_ctrl.readReqs                  52698                       # Number of read requests accepted (Count)
board.memory.mem_ctrl.writeReqs                 52666                       # Number of write requests accepted (Count)
board.memory.mem_ctrl.readBursts                52698                       # Number of controller read bursts, including those serviced by the write queue (Count)
board.memory.mem_ctrl.writeBursts               52666                       # Number of controller write bursts, including those merged in the write queue (Count)
board.memory.mem_ctrl.servicedByWrQ             40908                       # Number of controller read bursts serviced by the write queue (Count)
board.memory.mem_ctrl.mergedWrBursts            35363                       # Number of controller write bursts merged with an existing one (Count)
board.memory.mem_ctrl.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write (Count)
board.memory.mem_ctrl.avgRdQLen                  1.65                       # Average read queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.avgWrQLen                 27.30                       # Average write queue length when enqueuing ((Count/Tick))
board.memory.mem_ctrl.numRdRetry                    0                       # Number of times read queue was full causing retry (Count)
board.memory.mem_ctrl.numWrRetry                    0                       # Number of times write queue was full causing retry (Count)
board.memory.mem_ctrl.readPktSize::0                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::1                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::2                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::3                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::4                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::5                0                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.readPktSize::6            52698                       # Read request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::0               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::1               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::2               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::3               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::4               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::5               0                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.writePktSize::6           52666                       # Write request sizes (log2) (Count)
board.memory.mem_ctrl.rdQLenPdf::0               6435                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::1               2634                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::2               1386                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::3                792                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::4                386                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::5                 96                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::6                 29                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::7                 13                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::8                  5                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::9                  5                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::10                 4                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::11                 3                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::12                 1                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::13                 1                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::14                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::15                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::16                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::17                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::18                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::19                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::20                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::21                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::22                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::23                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::24                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::25                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::26                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::27                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::28                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::29                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::30                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdQLenPdf::31                 0                       # What read queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::0                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::1                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::2                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::3                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::4                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::5                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::6                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::7                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::8                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::9                  1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::10                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::11                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::12                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::13                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::14                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::15                73                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::16               118                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::17               354                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::18               605                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::19               807                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::20               973                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::21              1075                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::22              1213                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::23              1253                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::24              1254                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::25              1240                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::26              1276                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::27              1387                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::28              1261                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::29              1155                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::30              1079                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::31              1068                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::32              1061                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::33                15                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::34                12                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::35                 4                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::36                 3                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::37                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::38                 1                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::39                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::40                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::41                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::42                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::43                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::44                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::45                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::46                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::47                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::48                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::49                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::50                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::51                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::52                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::53                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::54                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::55                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::56                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::57                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::58                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::59                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::60                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::61                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::62                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.wrQLenPdf::63                 0                       # What write queue length does an incoming req see (Count)
board.memory.mem_ctrl.rdPerTurnAround::samples         1046                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::mean    11.267686                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::gmean    10.661369                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::stdev     3.783754                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::2-3            9      0.86%      0.86% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::4-5           20      1.91%      2.77% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::6-7          117     11.19%     13.96% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::8-9          206     19.69%     33.65% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::10-11          220     21.03%     54.68% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::12-13          215     20.55%     75.24% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::14-15          139     13.29%     88.53% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::16-17           72      6.88%     95.41% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::18-19           33      3.15%     98.57% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::20-21           10      0.96%     99.52% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::22-23            3      0.29%     99.81% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::24-25            1      0.10%     99.90% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::58-59            1      0.10%    100.00% # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.rdPerTurnAround::total         1046                       # Reads before turning the bus around for writes (Count)
board.memory.mem_ctrl.wrPerTurnAround::samples         1046                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::mean    16.518164                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::gmean    16.469045                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::stdev     1.369229                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::16          876     83.75%     83.75% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::17           30      2.87%     86.62% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::18           39      3.73%     90.34% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::19           33      3.15%     93.50% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::20           32      3.06%     96.56% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::21           21      2.01%     98.57% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::22           10      0.96%     99.52% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::23            2      0.19%     99.71% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::25            2      0.19%     99.90% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::26            1      0.10%    100.00% # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.wrPerTurnAround::total         1046                       # Writes before turning the bus around for reads (Count)
board.memory.mem_ctrl.bytesReadWrQ            2618112                       # Total number of bytes read from write queue (Byte)
board.memory.mem_ctrl.bytesReadSys            3372672                       # Total read bytes from the system interface side (Byte)
board.memory.mem_ctrl.bytesWrittenSys         3370624                       # Total written bytes from the system interface side (Byte)
board.memory.mem_ctrl.avgRdBWSys         3376078432.75394249                       # Average system read bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.avgWrBWSys         3374028364.25327635                       # Average system write bandwidth in Byte/s ((Byte/Second))
board.memory.mem_ctrl.totGap                998987679                       # Total gap between requests (Tick)
board.memory.mem_ctrl.avgGap                  9481.30                       # Average gap between requests ((Tick/Count))
board.memory.mem_ctrl.requestorReadBytes::cache_hierarchy.l1dcaches.prefetcher       361600                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.inst        85440                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorReadBytes::processor.cores.core.data       307520                       # Per-requestor bytes read from memory (Byte)
board.memory.mem_ctrl.requestorWriteBytes::writebacks      1105792                       # Per-requestor bytes write to memory (Byte)
board.memory.mem_ctrl.requestorReadRate::cache_hierarchy.l1dcaches.prefetcher 361965219.648938775063                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.inst 85526295.262182876468                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadRate::processor.cores.core.data 307830598.303212523460                       # Per-requestor bytes read from memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorWriteRate::writebacks 1106908861.078648567200                       # Per-requestor bytes write to memory rate ((Byte/Second))
board.memory.mem_ctrl.requestorReadAccesses::cache_hierarchy.l1dcaches.prefetcher        23179                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.inst         1513                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadAccesses::processor.cores.core.data        28006                       # Per-requestor read serviced memory accesses (Count)
board.memory.mem_ctrl.requestorWriteAccesses::writebacks        52666                       # Per-requestor write serviced memory accesses (Count)
board.memory.mem_ctrl.requestorReadTotalLat::cache_hierarchy.l1dcaches.prefetcher    257602983                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.inst     52214143                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadTotalLat::processor.cores.core.data    203896325                       # Per-requestor read total memory access latency (Tick)
board.memory.mem_ctrl.requestorWriteTotalLat::writebacks  26671821325                       # Per-requestor write total memory access latency (Tick)
board.memory.mem_ctrl.requestorReadAvgLat::cache_hierarchy.l1dcaches.prefetcher     11113.64                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.inst     34510.34                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorReadAvgLat::processor.cores.core.data      7280.45                       # Per-requestor read average memory access latency ((Tick/Count))
board.memory.mem_ctrl.requestorWriteAvgLat::writebacks    506433.40                       # Per-requestor write average memory access latency ((Tick/Count))
board.memory.mem_ctrl.dram.bytesRead::cache_hierarchy.l1dcaches.prefetcher      1483456                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.inst        96832                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::processor.cores.core.data      1792384                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesRead::total      3372672                       # Number of bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::processor.cores.core.inst        96832                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesInstRead::total        96832                       # Number of instructions bytes read from this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::writebacks       179712                       # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.bytesWritten::total       179712                       # Number of bytes written to this memory (Byte)
board.memory.mem_ctrl.dram.numReads::cache_hierarchy.l1dcaches.prefetcher        23179                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.inst         1513                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::processor.cores.core.data        28006                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numReads::total        52698                       # Number of read requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::writebacks         2808                       # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.numWrites::total         2808                       # Number of write requests responded to by this memory (Count)
board.memory.mem_ctrl.dram.bwRead::cache_hierarchy.l1dcaches.prefetcher   1484954306                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.inst     96929801                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::processor.cores.core.data   1794194326                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwRead::total   3376078433                       # Total read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::processor.cores.core.inst     96929801                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwInstRead::total     96929801                       # Instruction read bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::writebacks    179893511                       # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwWrite::total    179893511                       # Write bandwidth from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::writebacks    179893511                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::cache_hierarchy.l1dcaches.prefetcher   1484954306                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.inst     96929801                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::processor.cores.core.data   1794194326                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.bwTotal::total   3555971944                       # Total bandwidth to/from this memory ((Byte/Second))
board.memory.mem_ctrl.dram.readBursts           11790                       # Number of DRAM read bursts (Count)
board.memory.mem_ctrl.dram.writeBursts          17278                       # Number of DRAM write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::0          293                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::1          161                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::2          101                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::3           79                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::4           39                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::5            6                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::6           33                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::7          668                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::8         8736                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::9          701                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::10          327                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::11          133                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::12           20                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::13           39                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::14          195                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankRdBursts::15          259                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::0          305                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::1          167                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::2          111                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::3           86                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::4           40                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::5            7                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::6           34                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::7         1528                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::8        12806                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::9         1127                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::10          348                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::11          159                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::12           24                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::13           40                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::14          241                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.perBankWrBursts::15          255                       # Per bank write bursts (Count)
board.memory.mem_ctrl.dram.totQLat          292650951                       # Total ticks spent queuing (Tick)
board.memory.mem_ctrl.dram.totBusLat         58950000                       # Total ticks spent in databus transfers (Tick)
board.memory.mem_ctrl.dram.totMemAccLat     513713451                       # Total ticks spent from burst creation until serviced by the DRAM (Tick)
board.memory.mem_ctrl.dram.avgQLat           24821.96                       # Average queueing delay per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgBusLat          5000.00                       # Average bus latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.avgMemAccLat      43571.96                       # Average memory access latency per DRAM burst ((Tick/Count))
board.memory.mem_ctrl.dram.readRowHits          10536                       # Number of row buffer hits during reads (Count)
board.memory.mem_ctrl.dram.writeRowHits         15959                       # Number of row buffer hits during writes (Count)
board.memory.mem_ctrl.dram.readRowHitRate        89.36                       # Row buffer hit rate for reads (Ratio)
board.memory.mem_ctrl.dram.writeRowHitRate        92.37                       # Row buffer hit rate for writes (Ratio)
board.memory.mem_ctrl.dram.bytesPerActivate::samples         2566                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::mean   724.651598                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::gmean   533.527008                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::stdev   386.517688                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::0-127          267     10.41%     10.41% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::128-255          261     10.17%     20.58% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::256-383          154      6.00%     26.58% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::384-511          122      4.75%     31.33% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::512-639          107      4.17%     35.50% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::640-767           61      2.38%     37.88% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::768-895           67      2.61%     40.49% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::896-1023           59      2.30%     42.79% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::1024-1151         1468     57.21%    100.00% # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesPerActivate::total         2566                       # Bytes accessed per row activation (Byte)
board.memory.mem_ctrl.dram.bytesRead           754560                       # Total bytes read (Byte)
board.memory.mem_ctrl.dram.bytesWritten       1105792                       # Total bytes written (Byte)
board.memory.mem_ctrl.dram.avgRdBW         755.322113                       # Average DRAM read bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.avgWrBW        1106.908861                       # Average DRAM write bandwidth in MiBytes/s ((Byte/Second))
board.memory.mem_ctrl.dram.peakBW            12800.00                       # Theoretical peak bandwidth in MiByte/s ((Byte/Second))
board.memory.mem_ctrl.dram.busUtil              14.55                       # Data bus utilization in percentage (Ratio)
board.memory.mem_ctrl.dram.busUtilRead           5.90                       # Data bus utilization in percentage for reads (Ratio)
board.memory.mem_ctrl.dram.busUtilWrite          8.65                       # Data bus utilization in percentage for writes (Ratio)
board.memory.mem_ctrl.dram.pageHitRate          91.15                       # Row buffer hit rate, read and write combined (Ratio)
board.memory.mem_ctrl.dram.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.memory.mem_ctrl.dram.rank0.actEnergy      3684240                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preEnergy      1950630                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.readEnergy      9853200                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.writeEnergy     11891160                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.refreshEnergy 78673920.000000                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actBackEnergy    397991100                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.preBackEnergy     48462240                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.totalEnergy    552506490                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank0.averagePower   553.064527                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank0.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::IDLE    121856795                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::REF     33280000                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT    843854214                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank0.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.actEnergy     14686980                       # Energy for activate commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preEnergy      7787340                       # Energy for precharge commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.readEnergy     74327400                       # Energy for read commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.writeEnergy     78300000                       # Energy for write commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.refreshEnergy 78673920.000000                       # Energy for refresh commands per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actBackEnergy    446056920                       # Energy for active background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.preBackEnergy      7985760                       # Energy for precharge background per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.totalEnergy    707818320                       # Total energy per rank (pJ) (Joule)
board.memory.mem_ctrl.dram.rank1.averagePower   708.533224                       # Core power per rank (mW) (Watt)
board.memory.mem_ctrl.dram.rank1.totalIdleTime            0                       # Total Idle time Per DRAM Rank (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::IDLE     16828797                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::REF     33280000                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::SREF            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::PRE_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT    948882212                       # Time in different power states (Tick)
board.memory.mem_ctrl.dram.rank1.pwrStateTime::ACT_PDN            0                       # Time in different power states (Tick)
board.memory.mem_ctrl.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.numCycles          2999974                       # Number of cpu cycles simulated (Cycle)
board.processor.cores.core.numWorkItemsStarted            0                       # Number of work items this cpu started (Count)
board.processor.cores.core.numWorkItemsCompleted            0                       # Number of work items this cpu completed (Count)
board.processor.cores.core.instsAdded         2376259                       # Number of instructions added to the IQ (excludes non-spec) (Count)
board.processor.cores.core.nonSpecInstsAdded            2                       # Number of non-speculative instructions added to the IQ (Count)
board.processor.cores.core.instsIssued        2345799                       # Number of instructions issued (Count)
board.processor.cores.core.squashedInstsIssued           83                       # Number of squashed instructions issued (Count)
board.processor.cores.core.squashedInstsExamined        67749                       # Number of squashed instructions iterated over during squash; mainly for profiling (Count)
board.processor.cores.core.squashedOperandsExamined       157623                       # Number of squashed operands that are examined and possibly removed from graph (Count)
board.processor.cores.core.squashedNonSpecRemoved            2                       # Number of squashed non-spec instructions that were removed (Count)
board.processor.cores.core.numIssuedDist::samples      2857201                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::mean     0.821013                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::stdev     1.193207                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::underflows            0      0.00%      0.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::0      1575312     55.13%     55.13% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::1       680200     23.81%     78.94% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::2       327171     11.45%     90.39% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::3       158244      5.54%     95.93% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::4        72015      2.52%     98.45% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::5        26383      0.92%     99.37% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::6        10880      0.38%     99.76% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::7         4698      0.16%     99.92% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::8         2298      0.08%    100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::overflows            0      0.00%    100.00% # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::min_value            0                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::max_value            8                       # Number of insts issued each cycle (Count)
board.processor.cores.core.numIssuedDist::total      2857201                       # Number of insts issued each cycle (Count)
board.processor.cores.core.statFuBusy::No_OpClass            0      0.00%      0.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntAlu         1749      7.80%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntMult            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IntDiv            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatAdd            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCmp            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatCvt            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMult            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMultAcc            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatDiv            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMisc            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatSqrt            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAdd            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAddAcc            0      0.00%      7.80% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAlu           10      0.04%      7.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCmp            0      0.00%      7.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdCvt            1      0.00%      7.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMisc            2      0.01%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMult            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdMultAcc            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShift            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShiftAcc            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdDiv            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSqrt            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAdd            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatAlu            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCmp            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatCvt            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatDiv            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMisc            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMult            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatMultAcc            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatSqrt            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAdd            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceAlu            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdReduceCmp            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceAdd            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdFloatReduceCmp            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAes            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdAesMix            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha1Hash2            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdSha256Hash2            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma2            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdShaSigma3            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::SimdPredAlu            0      0.00%      7.85% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemRead         4934     21.99%     29.84% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::MemWrite        15725     70.09%     99.93% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemRead            3      0.01%     99.95% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::FloatMemWrite           12      0.05%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::IprAccess            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statFuBusy::InstPrefetch            0      0.00%    100.00% # attempts to use FU when none available (Count)
board.processor.cores.core.statIssuedInstType_0::No_OpClass         7607      0.32%      0.32% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntAlu      1562754     66.62%     66.94% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntMult        52439      2.24%     69.18% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IntDiv           72      0.00%     69.18% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatAdd          162      0.01%     69.19% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCmp            0      0.00%     69.19% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatCvt            0      0.00%     69.19% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMult            0      0.00%     69.19% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMultAcc            0      0.00%     69.19% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatDiv            0      0.00%     69.19% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMisc            0      0.00%     69.19% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatSqrt            0      0.00%     69.19% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAdd            0      0.00%     69.19% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAddAcc            0      0.00%     69.19% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAlu          196      0.01%     69.20% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCmp            0      0.00%     69.20% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdCvt           88      0.00%     69.20% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMisc          318      0.01%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMult            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdMultAcc            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShift            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShiftAcc            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdDiv            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSqrt            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAdd            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatAlu            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCmp            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatCvt            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatDiv            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMisc            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMult            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatMultAcc            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatSqrt            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAdd            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceAlu            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdReduceCmp            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceAdd            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdFloatReduceCmp            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAes            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdAesMix            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha1Hash2            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdSha256Hash2            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma2            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdShaSigma3            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::SimdPredAlu            0      0.00%     69.21% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemRead       592382     25.25%     94.47% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::MemWrite       129074      5.50%     99.97% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemRead          119      0.01%     99.97% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::FloatMemWrite          588      0.03%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::IprAccess            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::InstPrefetch            0      0.00%    100.00% # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.statIssuedInstType_0::total      2345799                       # Number of instructions issued per FU type, per thread (Count)
board.processor.cores.core.issueRate         0.781940                       # Inst issue rate ((Count/Cycle))
board.processor.cores.core.fuBusy               22436                       # FU busy when requested (Count)
board.processor.cores.core.fuBusyRate        0.009564                       # FU busy rate (busy events/executed inst) ((Count/Count))
board.processor.cores.core.intInstQueueReads      7567998                       # Number of integer instruction queue reads (Count)
board.processor.cores.core.intInstQueueWrites      2442243                       # Number of integer instruction queue writes (Count)
board.processor.cores.core.intInstQueueWakeupAccesses      2339205                       # Number of integer instruction queue wakeup accesses (Count)
board.processor.cores.core.fpInstQueueReads         3320                       # Number of floating instruction queue reads (Count)
board.processor.cores.core.fpInstQueueWrites         1848                       # Number of floating instruction queue writes (Count)
board.processor.cores.core.fpInstQueueWakeupAccesses         1619                       # Number of floating instruction queue wakeup accesses (Count)
board.processor.cores.core.vecInstQueueReads            0                       # Number of vector instruction queue reads (Count)
board.processor.cores.core.vecInstQueueWrites            0                       # Number of vector instruction queue writes (Count)
board.processor.cores.core.vecInstQueueWakeupAccesses            0                       # Number of vector instruction queue wakeup accesses (Count)
board.processor.cores.core.intAluAccesses      2358954                       # Number of integer alu accesses (Count)
board.processor.cores.core.fpAluAccesses         1674                       # Number of floating point alu accesses (Count)
board.processor.cores.core.vecAluAccesses            0                       # Number of vector alu accesses (Count)
board.processor.cores.core.numInsts           2342362                       # Number of executed instructions (Count)
board.processor.cores.core.numLoadInsts        590231                       # Number of load instructions executed (Count)
board.processor.cores.core.numSquashedInsts         3437                       # Number of squashed instructions skipped in execute (Count)
board.processor.cores.core.numSwp                   0                       # Number of swp insts executed (Count)
board.processor.cores.core.numNop                   0                       # Number of nop insts executed (Count)
board.processor.cores.core.numRefs             719740                       # Number of memory reference insts executed (Count)
board.processor.cores.core.numBranches          67904                       # Number of branches executed (Count)
board.processor.cores.core.numStoreInsts       129509                       # Number of stores executed (Count)
board.processor.cores.core.numRate           0.780794                       # Inst execution rate ((Count/Cycle))
board.processor.cores.core.timesIdled            1258                       # Number of times that the entire CPU went into an idle state and unscheduled itself (Count)
board.processor.cores.core.idleCycles          142773                       # Total number of cycles that the CPU has spent unscheduled due to idling (Cycle)
board.processor.cores.core.committedInsts      1753641                       # Number of Instructions Simulated (Count)
board.processor.cores.core.committedOps       2308506                       # Number of Ops (including micro ops) Simulated (Count)
board.processor.cores.core.cpi               1.710712                       # CPI: Cycles Per Instruction ((Cycle/Count))
board.processor.cores.core.totalCpi          1.710712                       # CPI: Total CPI of All Threads ((Cycle/Count))
board.processor.cores.core.ipc               0.584552                       # IPC: Instructions Per Cycle ((Count/Cycle))
board.processor.cores.core.totalIpc          0.584552                       # IPC: Total IPC of All Threads ((Count/Cycle))
board.processor.cores.core.intRegfileReads      3894266                       # Number of integer regfile reads (Count)
board.processor.cores.core.intRegfileWrites      2080282                       # Number of integer regfile writes (Count)
board.processor.cores.core.fpRegfileReads         2033                       # Number of floating regfile reads (Count)
board.processor.cores.core.fpRegfileWrites          972                       # Number of floating regfile writes (Count)
board.processor.cores.core.ccRegfileReads       525444                       # number of cc regfile reads (Count)
board.processor.cores.core.ccRegfileWrites      1339116                       # number of cc regfile writes (Count)
board.processor.cores.core.miscRegfileReads       870065                       # number of misc regfile reads (Count)
board.processor.cores.core.MemDepUnit__0.insertedLoads       596993                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.insertedStores       131349                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingLoads       228708                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__0.conflictingStores        56617                       # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__1.insertedLoads            0                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.insertedStores            0                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingLoads            0                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__1.conflictingStores            0                       # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__2.insertedLoads            0                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.insertedStores            0                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingLoads            0                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__2.conflictingStores            0                       # Number of conflicting stores. (Count)
board.processor.cores.core.MemDepUnit__3.insertedLoads            0                       # Number of loads inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.insertedStores            0                       # Number of stores inserted to the mem dependence unit. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingLoads            0                       # Number of conflicting loads. (Count)
board.processor.cores.core.MemDepUnit__3.conflictingStores            0                       # Number of conflicting stores. (Count)
board.processor.cores.core.branchPred.lookups        72531                       # Number of BP lookups (Count)
board.processor.cores.core.branchPred.condPredicted        55156                       # Number of conditional branches predicted (Count)
board.processor.cores.core.branchPred.condIncorrect         3263                       # Number of conditional branches incorrect (Count)
board.processor.cores.core.branchPred.BTBLookups        62667                       # Number of BTB lookups (Count)
board.processor.cores.core.branchPred.BTBHits        61740                       # Number of BTB hits (Count)
board.processor.cores.core.branchPred.BTBHitRatio     0.985208                       # BTB Hit Ratio (Ratio)
board.processor.cores.core.branchPred.RASUsed         6885                       # Number of times the RAS was used to get a target. (Count)
board.processor.cores.core.branchPred.RASIncorrect            1                       # Number of incorrect RAS predictions. (Count)
board.processor.cores.core.branchPred.indirectLookups          424                       # Number of indirect predictor lookups. (Count)
board.processor.cores.core.branchPred.indirectHits           47                       # Number of indirect target hits. (Count)
board.processor.cores.core.branchPred.indirectMisses          377                       # Number of indirect misses. (Count)
board.processor.cores.core.branchPred.indirectMispredicted          132                       # Number of mispredicted indirect branches. (Count)
board.processor.cores.core.commit.commitSquashedInsts        67393                       # The number of squashed insts skipped by commit (Count)
board.processor.cores.core.commit.branchMispredicts         3253                       # The number of times a branch was mispredicted (Count)
board.processor.cores.core.commit.numCommittedDist::samples      2846795                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::mean     0.810914                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::stdev     1.653936                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::underflows            0      0.00%      0.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::0      1860839     65.37%     65.37% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::1       507517     17.83%     83.19% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::2       216539      7.61%     90.80% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::3        90416      3.18%     93.98% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::4        39342      1.38%     95.36% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::5        12331      0.43%     95.79% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::6        39533      1.39%     97.18% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::7         1782      0.06%     97.24% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::8        78496      2.76%    100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::overflows            0      0.00%    100.00% # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::min_value            0                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::max_value            8                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.numCommittedDist::total      2846795                       # Number of insts commited each cycle (Count)
board.processor.cores.core.commit.instsCommitted      1753641                       # Number of instructions committed (Count)
board.processor.cores.core.commit.opsCommitted      2308506                       # Number of ops (including micro ops) committed (Count)
board.processor.cores.core.commit.memRefs       710701                       # Number of memory references committed (Count)
board.processor.cores.core.commit.loads        583617                       # Number of loads committed (Count)
board.processor.cores.core.commit.amos              0                       # Number of atomic instructions committed (Count)
board.processor.cores.core.commit.membars            0                       # Number of memory barriers committed (Count)
board.processor.cores.core.commit.branches        65715                       # Number of branches committed (Count)
board.processor.cores.core.commit.vectorInstructions            0                       # Number of committed Vector instructions. (Count)
board.processor.cores.core.commit.floating         1464                       # Number of committed floating point instructions. (Count)
board.processor.cores.core.commit.integer      2297372                       # Number of committed integer instructions. (Count)
board.processor.cores.core.commit.functionCalls         6247                       # Number of function calls committed. (Count)
board.processor.cores.core.commit.committedInstType_0::No_OpClass         6337      0.27%      0.27% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntAlu      1538694     66.65%     66.93% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntMult        52025      2.25%     69.18% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IntDiv           63      0.00%     69.18% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatAdd          154      0.01%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCmp            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatCvt            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMult            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMultAcc            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatDiv            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMisc            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatSqrt            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAdd            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAddAcc            0      0.00%     69.19% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAlu          136      0.01%     69.20% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCmp            0      0.00%     69.20% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdCvt           86      0.00%     69.20% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMisc          310      0.01%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMult            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdMultAcc            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShift            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShiftAcc            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdDiv            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSqrt            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAdd            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatAlu            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCmp            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatCvt            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatDiv            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMisc            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMult            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatMultAcc            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatSqrt            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAdd            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceAlu            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdReduceCmp            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceAdd            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdFloatReduceCmp            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAes            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdAesMix            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha1Hash2            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdSha256Hash2            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma2            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdShaSigma3            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::SimdPredAlu            0      0.00%     69.21% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemRead       583519     25.28%     94.49% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::MemWrite       126577      5.48%     99.97% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemRead           98      0.00%     99.98% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::FloatMemWrite          507      0.02%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::IprAccess            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction (Count)
board.processor.cores.core.commit.committedInstType_0::total      2308506                       # Class of committed instruction (Count)
board.processor.cores.core.commit.commitEligibleSamples        78496                       # number cycles where commit BW limit reached (Cycle)
board.processor.cores.core.decode.idleCycles       152253                       # Number of cycles decode is idle (Cycle)
board.processor.cores.core.decode.blockedCycles      2396798                       # Number of cycles decode is blocked (Cycle)
board.processor.cores.core.decode.runCycles        50689                       # Number of cycles decode is running (Cycle)
board.processor.cores.core.decode.unblockCycles       254117                       # Number of cycles decode is unblocking (Cycle)
board.processor.cores.core.decode.squashCycles         3344                       # Number of cycles decode is squashing (Cycle)
board.processor.cores.core.decode.branchResolved        59739                       # Number of times decode resolved a branch (Count)
board.processor.cores.core.decode.branchMispred          286                       # Number of times decode detected a branch misprediction (Count)
board.processor.cores.core.decode.decodedInsts      2406336                       # Number of instructions handled by decode (Count)
board.processor.cores.core.decode.squashedInsts         1448                       # Number of squashed instructions handled by decode (Count)
board.processor.cores.core.fetch.icacheStallCycles        62189                       # Number of cycles fetch is stalled on an Icache miss (Cycle)
board.processor.cores.core.fetch.insts        1890909                       # Number of instructions fetch has processed (Count)
board.processor.cores.core.fetch.branches        72531                       # Number of branches that fetch encountered (Count)
board.processor.cores.core.fetch.predictedBranches        68672                       # Number of branches that fetch has predicted taken (Count)
board.processor.cores.core.fetch.cycles       2789396                       # Number of cycles fetch has run and was not squashing or blocked (Cycle)
board.processor.cores.core.fetch.squashCycles         7252                       # Number of cycles fetch has spent squashing (Cycle)
board.processor.cores.core.fetch.miscStallCycles          286                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs (Cycle)
board.processor.cores.core.fetch.pendingTrapStallCycles         1704                       # Number of stall cycles due to pending traps (Cycle)
board.processor.cores.core.fetch.cacheLines       172350                       # Number of cache lines fetched (Count)
board.processor.cores.core.fetch.icacheSquashes          608                       # Number of outstanding Icache misses that were squashed (Count)
board.processor.cores.core.fetch.nisnDist::samples      2857201                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::mean     0.872887                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::stdev     2.267398                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::underflows            0      0.00%      0.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::0      2420500     84.72%     84.72% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::1        28007      0.98%     85.70% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::2        43396      1.52%     87.21% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::3        29170      1.02%     88.24% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::4        40650      1.42%     89.66% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::5        46851      1.64%     91.30% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::6        40340      1.41%     92.71% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::7        13485      0.47%     93.18% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::8       194802      6.82%    100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::overflows            0      0.00%    100.00% # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::min_value            0                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::max_value            8                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.nisnDist::total      2857201                       # Number of instructions fetched each cycle (Total) (Count)
board.processor.cores.core.fetch.branchRate     0.024177                       # Number of branch fetches per cycle (Ratio)
board.processor.cores.core.fetch.rate        0.630308                       # Number of inst fetches per cycle ((Count/Cycle))
board.processor.cores.core.iew.idleCycles            0                       # Number of cycles IEW is idle (Cycle)
board.processor.cores.core.iew.squashCycles         3344                       # Number of cycles IEW is squashing (Cycle)
board.processor.cores.core.iew.blockCycles       152756                       # Number of cycles IEW is blocking (Cycle)
board.processor.cores.core.iew.unblockCycles       930889                       # Number of cycles IEW is unblocking (Cycle)
board.processor.cores.core.iew.dispatchedInsts      2376261                       # Number of instructions dispatched to IQ (Count)
board.processor.cores.core.iew.dispSquashedInsts           95                       # Number of squashed instructions skipped by dispatch (Count)
board.processor.cores.core.iew.dispLoadInsts       596993                       # Number of dispatched load instructions (Count)
board.processor.cores.core.iew.dispStoreInsts       131349                       # Number of dispatched store instructions (Count)
board.processor.cores.core.iew.dispNonSpecInsts            2                       # Number of dispatched non-speculative instructions (Count)
board.processor.cores.core.iew.iqFullEvents         1481                       # Number of times the IQ has become full, causing a stall (Count)
board.processor.cores.core.iew.lsqFullEvents       927412                       # Number of times the LSQ has become full, causing a stall (Count)
board.processor.cores.core.iew.memOrderViolationEvents           83                       # Number of memory order violations (Count)
board.processor.cores.core.iew.predictedTakenIncorrect         2400                       # Number of branches that were predicted taken incorrectly (Count)
board.processor.cores.core.iew.predictedNotTakenIncorrect         1012                       # Number of branches that were predicted not taken incorrectly (Count)
board.processor.cores.core.iew.branchMispredicts         3412                       # Number of branch mispredicts detected at execute (Count)
board.processor.cores.core.iew.instsToCommit      2341485                       # Cumulative count of insts sent to commit (Count)
board.processor.cores.core.iew.writebackCount      2340824                       # Cumulative count of insts written-back (Count)
board.processor.cores.core.iew.producerInst      1908634                       # Number of instructions producing a value (Count)
board.processor.cores.core.iew.consumerInst      3403159                       # Number of instructions consuming a value (Count)
board.processor.cores.core.iew.wbRate        0.780281                       # Insts written-back per cycle ((Count/Cycle))
board.processor.cores.core.iew.wbFanout      0.560842                       # Average fanout of values written-back ((Count/Count))
board.processor.cores.core.interrupts.clk_domain.clock         5328                       # Clock period in ticks (Tick)
board.processor.cores.core.lsq0.forwLoads       261987                       # Number of loads that had data forwarded from stores (Count)
board.processor.cores.core.lsq0.squashedLoads        13376                       # Number of loads squashed (Count)
board.processor.cores.core.lsq0.ignoredResponses           11                       # Number of memory responses ignored because the instruction is squashed (Count)
board.processor.cores.core.lsq0.memOrderViolation           83                       # Number of memory ordering violations (Count)
board.processor.cores.core.lsq0.squashedStores         4265                       # Number of stores squashed (Count)
board.processor.cores.core.lsq0.rescheduledLoads            0                       # Number of loads that were rescheduled (Count)
board.processor.cores.core.lsq0.blockedByCache            0                       # Number of times an access to memory failed due to the cache being blocked (Count)
board.processor.cores.core.lsq0.loadToUse::samples       583617                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::mean     5.503136                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::stdev    23.968468                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::0-9       555037     95.10%     95.10% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::10-19          193      0.03%     95.14% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::20-29           27      0.00%     95.14% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::30-39          230      0.04%     95.18% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::40-49        23190      3.97%     99.15% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::50-59           28      0.00%     99.16% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::60-69          335      0.06%     99.22% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::70-79           26      0.00%     99.22% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::80-89           32      0.01%     99.23% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::90-99           10      0.00%     99.23% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::100-109           18      0.00%     99.23% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::110-119            2      0.00%     99.23% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::120-129           14      0.00%     99.23% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::130-139         2745      0.47%     99.70% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::140-149          162      0.03%     99.73% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::150-159           26      0.00%     99.74% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::160-169           12      0.00%     99.74% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::170-179          207      0.04%     99.77% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::180-189           40      0.01%     99.78% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::190-199           26      0.00%     99.78% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::200-209           15      0.00%     99.79% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::210-219           79      0.01%     99.80% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::220-229           50      0.01%     99.81% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::230-239           44      0.01%     99.82% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::240-249           21      0.00%     99.82% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::250-259           12      0.00%     99.82% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::260-269           19      0.00%     99.83% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::270-279           15      0.00%     99.83% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::280-289           24      0.00%     99.83% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::290-299           55      0.01%     99.84% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::overflows          923      0.16%    100.00% # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::min_value            2                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::max_value         1523                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.lsq0.loadToUse::total       583617                       # Distribution of cycle latency between the first time a load is issued and its completion (Unspecified)
board.processor.cores.core.mmu.dtb.rdAccesses       590239                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrAccesses       129510                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.dtb.rdMisses           99                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.dtb.wrMisses           28                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.dtb.walker.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.mmu.itb.rdAccesses            0                       # TLB accesses on read requests (Count)
board.processor.cores.core.mmu.itb.wrAccesses       172642                       # TLB accesses on write requests (Count)
board.processor.cores.core.mmu.itb.rdMisses            0                       # TLB misses on read requests (Count)
board.processor.cores.core.mmu.itb.wrMisses          349                       # TLB misses on write requests (Count)
board.processor.cores.core.mmu.itb.walker.power_state.pwrStateResidencyTicks::UNDEFINED    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.power_state.pwrStateResidencyTicks::ON    998991009                       # Cumulative time (in ticks) in various power states (Tick)
board.processor.cores.core.rename.squashCycles         3344                       # Number of cycles rename is squashing (Cycle)
board.processor.cores.core.rename.idleCycles       233322                       # Number of cycles rename is idle (Cycle)
board.processor.cores.core.rename.blockCycles      1437084                       # Number of cycles rename is blocking (Cycle)
board.processor.cores.core.rename.serializeStallCycles          177                       # count of cycles rename stalled for serializing inst (Cycle)
board.processor.cores.core.rename.runCycles       210777                       # Number of cycles rename is running (Cycle)
board.processor.cores.core.rename.unblockCycles       972497                       # Number of cycles rename is unblocking (Cycle)
board.processor.cores.core.rename.renamedInsts      2386644                       # Number of instructions processed by rename (Count)
board.processor.cores.core.rename.ROBFullEvents          754                       # Number of times rename has blocked due to ROB full (Count)
board.processor.cores.core.rename.IQFullEvents       847507                       # Number of times rename has blocked due to IQ full (Count)
board.processor.cores.core.rename.LQFullEvents       217102                       # Number of times rename has blocked due to LQ full (Count)
board.processor.cores.core.rename.SQFullEvents        10610                       # Number of times rename has blocked due to SQ full (Count)
board.processor.cores.core.rename.renamedOperands      5622413                       # Number of destination operands rename has renamed (Count)
board.processor.cores.core.rename.lookups      9181704                       # Number of register rename lookups that rename has made (Count)
board.processor.cores.core.rename.intLookups      3976171                       # Number of integer rename lookups (Count)
board.processor.cores.core.rename.fpLookups         2062                       # Number of floating rename lookups (Count)
board.processor.cores.core.rename.committedMaps      5466916                       # Number of HB maps that are committed (Count)
board.processor.cores.core.rename.undoneMaps       155488                       # Number of HB maps that are undone due to squashing (Count)
board.processor.cores.core.rename.serializing            4                       # count of serializing insts renamed (Count)
board.processor.cores.core.rename.tempSerializing            4                       # count of temporary serializing insts renamed (Count)
board.processor.cores.core.rename.skidInsts      1442939                       # count of insts added to the skid buffer (Count)
board.processor.cores.core.rob.reads          5143951                       # The number of ROB reads (Count)
board.processor.cores.core.rob.writes         4762225                       # The number of ROB writes (Count)
board.processor.cores.core.thread_0.numInsts      1753641                       # Number of Instructions committed (Count)
board.processor.cores.core.thread_0.numOps      2308506                       # Number of Ops committed (Count)
board.processor.cores.core.thread_0.numMemRefs            0                       # Number of Memory References (Count)
board.processor.cores.core.workload.numSyscalls           16                       # Number of system calls (Count)
board.workload.inst.arm                             0                       # number of arm instructions executed (Count)
board.workload.inst.quiesce                         0                       # number of quiesce instructions executed (Count)

---------- End Simulation Statistics   ----------
