# -*- coding: utf-8 -*-
# Copyright (c) 2015 Jason Power
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# met: redistributions of source code must retain the above copyright
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# neither the name of the copyright holders nor the names of its
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# this software without specific prior written permission.
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import m5
from m5.objects import *

system = System()

system.clk_domain = SrcClockDomain()
system.clk_domain.clock = "1GHz"
system.clk_domain.voltage_domain = VoltageDomain()

system.mem_mode = "timing"
system.mem_ranges = [AddrRange("512MB")]

system.cpu = TimingSimpleCPU()

system.membus = SystemXBar()

system.cpu.icache_port = system.membus.cpu_side_ports
system.cpu.dcache_port = system.membus.cpu_side_ports

system.cpu.createInterruptController()

if m5.defines.buildEnv['TARGET_ISA'] == "x86":
    system.cpu.interrupts[0].pio = system.membus.mem_side_ports
    system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
    system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports

system.comm_monitor = CommMonitor()
system.comm_monitor.cpu_side_port = system.membus.mem_side_ports
system.comm_monitor.trace = MemTraceProbe(trace_file=f"mem_trace",
                                        trace_compress=True)

system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
system.mem_ctrl.port = system.comm_monitor.mem_side_port

system.system_port = system.membus.cpu_side_ports

isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()

thispath = os.path.dirname(os.path.realpath(__file__))

binary = "gem5/tests/test-progs/hello/bin/x86/linux/hello"

system.workload = SEWorkload.init_compatible(binary)

process = Process()
process.cmd = [binary]
system.cpu.workload = process
system.cpu.createThreads()

root = Root(full_system = False, system = system)

m5.instantiate()

print("Beginning simulation!")
exit_event = m5.simulate()
print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
