Retro Rocket Kernel BASIC-Powered Operating System

Data Structures | Macros | Functions | Variables
pci.h File Reference
`#include <kernel.h>`

## Data Structures
struct | pci_subclass
union | pci_dev_t

## Macros
#define | PCI_CONFIG_ADDRESS 0xCF8
#define | PCI_CONFIG_DATA 0xCFC
#define | PCI_VENDOR_ID 0x00
#define | PCI_DEVICE_ID 0x02
#define | PCI_COMMAND 0x04
#define | PCI_STATUS 0x06
#define | PCI_REVISION_ID 0x08
#define | PCI_PROG_IF 0x09
#define | PCI_SUBCLASS 0x0a
#define | PCI_CLASS 0x0b
#define | PCI_CACHE_LINE_SIZE 0x0c
#define | PCI_LATENCY_TIMER 0x0d
#define | PCI_HEADER_TYPE 0x0e
#define | PCI_BIST 0x0f
#define | PCI_BAR0 0x10
#define | PCI_BAR1 0x14
#define | PCI_BAR2 0x18
#define | PCI_BAR3 0x1C
#define | PCI_BAR4 0x20
#define | PCI_BAR5 0x24
#define | PCI_CAPABILITIES 0x34
#define | PCI_INTERRUPT_LINE 0x3C
#define | PCI_INTERRUPT_PIN 0x3D
#define | PCI_MIN_GNT 0x3E
#define | PCI_MAX_LAT 0x3F
#define | PCI_SECONDARY_BUS 0x09
#define | PCI_STATUS_INTERRUPT (1 << 3)
#define | PCI_STATUS_CAPABAILITIES_LIST (1 << 4)
#define | PCI_STATUS_66MHZ_CAPABLE (1 << 5)
#define | PCI_STATUS_FAST_BACK_TO_BACK_CAPABLE (1 << 7)
#define | PCI_STATUS_MASTER_DATA_PARITY_ERROR (1 << 8)
#define | PCI_STATUS_DEVSEL_TIMING (1 << 9) & (1 << 10)
#define | PCI_STATUS_SIGNALLED_TARGET_ABORT (1 << 11)
#define | PCI_STATUS_RECEIVED_TARGET_ABORT (1 << 12)
#define | PCI_STATUS_RECEIVED_MASTER_ABORT (1 << 13)
#define | PCI_STATUS_SIGNALLED_SYSTEM_ERROR (1 << 14)
#define | PCI_STATUS_DETECTED_PARITY_ERROR (1 << 15)
#define | PCI_COMMAND_IOSPACE (1 << 0)
#define | PCI_COMMAND_MEMSPACE (1 << 1)
#define | PCI_COMMAND_BUS_MASTER (1 << 2)
#define | PCI_COMMAND_SPECIAL_CYCLES (1 << 3)
#define | PCI_COMMAND_MEMORY_WRITE_INVALIDATE (1 << 4)
#define | PCI_COMMAND_VGA_PALLETE_SNOOP (1 << 5)
#define | PCI_COMMAND_PARITY_ERROR_RESPONSE (1 << 6)
#define | PCI_COMMAND_RESERVED_0 (1 << 7)
#define | PCI_COMMAND_SERR_ENABLE (1 << 8)
#define | PCI_COMMAND_FAST_BACK_TO_BACK_ENABLE (1 << 9)
#define | PCI_COMMAND_INTERRUPT_DISABLE (1 << 10)
#define | PCI_COMMAND_RESERVED_1 (1 << 11)
#define | PCI_CAPABILITY_MSI 0x05
#define | PCI_MSI_64BIT (1 << 7)
#define | PCI_MSI_DEASSERT (1 << 14)
#define | PCI_MSI_EDGETRIGGER (1 << 15)
#define | PCI_MSI_ENABLE (1 << 16)
#define | PCI_BAR_TYPE_MEMORY 0x00
#define | PCI_BAR_TYPE_IOPORT 0x01
#define | PCI_HEADER_TYPE_DEVICE 0
#define | PCI_HEADER_TYPE_BRIDGE 1
#define | PCI_HEADER_TYPE_CARDBUS 2
#define | PCI_TYPE_BRIDGE 0x0604
#define | PCI_TYPE_SATA 0x0106
#define | PCI_NONE 0xFFFF
#define | DEVICE_PER_BUS 32
#define | FUNCTION_PER_DEVICE 32

## Functions
uint32_t | pci_read (pci_dev_t dev, uint32_t field)
void | pci_write (pci_dev_t dev, uint32_t field, uint32_t value)
uint32_t | get_device_type (pci_dev_t dev)
uint32_t | get_secondary_bus (pci_dev_t dev)
uint32_t | pci_reach_end (pci_dev_t dev)
pci_dev_t | pci_scan_function (uint16_t vendor_id, uint16_t device_id, uint32_t bus, uint32_t device, uint32_t function, int device_type)
pci_dev_t | pci_scan_device (uint16_t vendor_id, uint16_t device_id, uint32_t bus, uint32_t device, int device_type)
pci_dev_t | pci_scan_bus (uint16_t vendor_id, uint16_t device_id, uint32_t bus, int device_type)
pci_dev_t | pci_get_device (uint16_t vendor_id, uint16_t device_id, int device_type)
void | init_pci ()
bool | pci_bus_master (pci_dev_t device)
uint8_t | pci_bar_type (uint32_t field)
uint16_t | pci_io_base (uint32_t field)
uint32_t | pci_mem_base (uint32_t field)
bool | pci_not_found (pci_dev_t device)
bool | pci_enable_msi (pci_dev_t device, uint32_t vector, bool edgetrigger, bool deassert)
void | pci_display_device_list ()
size_t | pci_get_device_list (pci_dev_t **list)
void | pci_interrupt_enable (pci_dev_t device, bool enable)

## Variables
pci_dev_t | dev_zero

## Detailed Description

Author
  Craig Edwards (craig.nosp@m.edwa.nosp@m.rds@b.nosp@m.rain.nosp@m.box.c.nosp@m.c)

Copyright
  Copyright (c) 2012-2023

## Macro Definition Documentation

## ◆ DEVICE_PER_BUS

#define DEVICE_PER_BUS 32

## ◆ FUNCTION_PER_DEVICE

#define FUNCTION_PER_DEVICE 32

## ◆ PCI_BAR0

#define PCI_BAR0 0x10

## ◆ PCI_BAR1

#define PCI_BAR1 0x14

## ◆ PCI_BAR2

#define PCI_BAR2 0x18

## ◆ PCI_BAR3

#define PCI_BAR3 0x1C

## ◆ PCI_BAR4

#define PCI_BAR4 0x20

## ◆ PCI_BAR5

#define PCI_BAR5 0x24

## ◆ PCI_BAR_TYPE_IOPORT

#define PCI_BAR_TYPE_IOPORT 0x01

## ◆ PCI_BAR_TYPE_MEMORY

#define PCI_BAR_TYPE_MEMORY 0x00

## ◆ PCI_BIST

#define PCI_BIST 0x0f

## ◆ PCI_CACHE_LINE_SIZE

#define PCI_CACHE_LINE_SIZE 0x0c

## ◆ PCI_CAPABILITIES

#define PCI_CAPABILITIES 0x34

## ◆ PCI_CAPABILITY_MSI

#define PCI_CAPABILITY_MSI 0x05

## ◆ PCI_CLASS

#define PCI_CLASS 0x0b

## ◆ PCI_COMMAND

#define PCI_COMMAND 0x04

## ◆ PCI_COMMAND_BUS_MASTER

#define PCI_COMMAND_BUS_MASTER (1 << 2)

## ◆ PCI_COMMAND_FAST_BACK_TO_BACK_ENABLE

#define PCI_COMMAND_FAST_BACK_TO_BACK_ENABLE (1 << 9)

## ◆ PCI_COMMAND_INTERRUPT_DISABLE

#define PCI_COMMAND_INTERRUPT_DISABLE (1 << 10)

## ◆ PCI_COMMAND_IOSPACE

#define PCI_COMMAND_IOSPACE (1 << 0)

## ◆ PCI_COMMAND_MEMORY_WRITE_INVALIDATE

#define PCI_COMMAND_MEMORY_WRITE_INVALIDATE (1 << 4)

## ◆ PCI_COMMAND_MEMSPACE

#define PCI_COMMAND_MEMSPACE (1 << 1)

## ◆ PCI_COMMAND_PARITY_ERROR_RESPONSE

#define PCI_COMMAND_PARITY_ERROR_RESPONSE (1 << 6)

## ◆ PCI_COMMAND_RESERVED_0

#define PCI_COMMAND_RESERVED_0 (1 << 7)

## ◆ PCI_COMMAND_RESERVED_1

#define PCI_COMMAND_RESERVED_1 (1 << 11)

## ◆ PCI_COMMAND_SERR_ENABLE

#define PCI_COMMAND_SERR_ENABLE (1 << 8)

## ◆ PCI_COMMAND_SPECIAL_CYCLES

#define PCI_COMMAND_SPECIAL_CYCLES (1 << 3)

## ◆ PCI_COMMAND_VGA_PALLETE_SNOOP

#define PCI_COMMAND_VGA_PALLETE_SNOOP (1 << 5)

## ◆ PCI_CONFIG_ADDRESS

#define PCI_CONFIG_ADDRESS 0xCF8

## ◆ PCI_CONFIG_DATA

#define PCI_CONFIG_DATA 0xCFC

## ◆ PCI_DEVICE_ID

#define PCI_DEVICE_ID 0x02

## ◆ PCI_HEADER_TYPE

#define PCI_HEADER_TYPE 0x0e

## ◆ PCI_HEADER_TYPE_BRIDGE

#define PCI_HEADER_TYPE_BRIDGE 1

## ◆ PCI_HEADER_TYPE_CARDBUS

#define PCI_HEADER_TYPE_CARDBUS 2

## ◆ PCI_HEADER_TYPE_DEVICE

#define PCI_HEADER_TYPE_DEVICE 0

## ◆ PCI_INTERRUPT_LINE

#define PCI_INTERRUPT_LINE 0x3C

## ◆ PCI_INTERRUPT_PIN

#define PCI_INTERRUPT_PIN 0x3D

## ◆ PCI_LATENCY_TIMER

#define PCI_LATENCY_TIMER 0x0d

## ◆ PCI_MAX_LAT

#define PCI_MAX_LAT 0x3F

## ◆ PCI_MIN_GNT

#define PCI_MIN_GNT 0x3E

## ◆ PCI_MSI_64BIT

#define PCI_MSI_64BIT (1 << 7)

## ◆ PCI_MSI_DEASSERT

#define PCI_MSI_DEASSERT (1 << 14)

## ◆ PCI_MSI_EDGETRIGGER

#define PCI_MSI_EDGETRIGGER (1 << 15)

## ◆ PCI_MSI_ENABLE

#define PCI_MSI_ENABLE (1 << 16)

## ◆ PCI_NONE

#define PCI_NONE 0xFFFF

## ◆ PCI_PROG_IF

#define PCI_PROG_IF 0x09

## ◆ PCI_REVISION_ID

#define PCI_REVISION_ID 0x08

## ◆ PCI_SECONDARY_BUS

#define PCI_SECONDARY_BUS 0x09

## ◆ PCI_STATUS

#define PCI_STATUS 0x06

## ◆ PCI_STATUS_66MHZ_CAPABLE

#define PCI_STATUS_66MHZ_CAPABLE (1 << 5)

## ◆ PCI_STATUS_CAPABAILITIES_LIST

#define PCI_STATUS_CAPABAILITIES_LIST (1 << 4)

## ◆ PCI_STATUS_DETECTED_PARITY_ERROR

#define PCI_STATUS_DETECTED_PARITY_ERROR (1 << 15)

## ◆ PCI_STATUS_DEVSEL_TIMING

#define PCI_STATUS_DEVSEL_TIMING (1 << 9) & (1 << 10)

## ◆ PCI_STATUS_FAST_BACK_TO_BACK_CAPABLE

#define PCI_STATUS_FAST_BACK_TO_BACK_CAPABLE (1 << 7)

## ◆ PCI_STATUS_INTERRUPT

#define PCI_STATUS_INTERRUPT (1 << 3)

## ◆ PCI_STATUS_MASTER_DATA_PARITY_ERROR

#define PCI_STATUS_MASTER_DATA_PARITY_ERROR (1 << 8)

## ◆ PCI_STATUS_RECEIVED_MASTER_ABORT

#define PCI_STATUS_RECEIVED_MASTER_ABORT (1 << 13)

## ◆ PCI_STATUS_RECEIVED_TARGET_ABORT

#define PCI_STATUS_RECEIVED_TARGET_ABORT (1 << 12)

## ◆ PCI_STATUS_SIGNALLED_SYSTEM_ERROR

#define PCI_STATUS_SIGNALLED_SYSTEM_ERROR (1 << 14)

## ◆ PCI_STATUS_SIGNALLED_TARGET_ABORT

#define PCI_STATUS_SIGNALLED_TARGET_ABORT (1 << 11)

## ◆ PCI_SUBCLASS

#define PCI_SUBCLASS 0x0a

## ◆ PCI_TYPE_BRIDGE

#define PCI_TYPE_BRIDGE 0x0604

## ◆ PCI_TYPE_SATA

#define PCI_TYPE_SATA 0x0106

## ◆ PCI_VENDOR_ID

#define PCI_VENDOR_ID 0x00

## Function Documentation

## ◆ get_device_type()

uint32_t get_device_type | ( | pci_dev_t | dev | ) |

## ◆ get_secondary_bus()

uint32_t get_secondary_bus | ( | pci_dev_t | dev | ) |

## ◆ init_pci()

void init_pci | ( |  | ) |

## ◆ pci_bar_type()

uint8_t pci_bar_type | ( | uint32_t | field | ) |

## ◆ pci_bus_master()

bool pci_bus_master | ( | pci_dev_t | device | ) |

## ◆ pci_display_device_list()

void pci_display_device_list | ( |  | ) |

## ◆ pci_enable_msi()

bool pci_enable_msi | ( | pci_dev_t | device,
|  | uint32_t | vector,
|  | bool | edgetrigger,
|  | bool | deassert
| ) |  |

## ◆ pci_get_device()

pci_dev_t pci_get_device | ( | uint16_t | vendor_id,
|  | uint16_t | device_id,
|  | int | device_type
| ) |  |

## ◆ pci_get_device_list()

size_t pci_get_device_list | ( | pci_dev_t ** | list | ) |

## ◆ pci_interrupt_enable()

void pci_interrupt_enable | ( | pci_dev_t | device,
|  | bool | enable
| ) |  |

## ◆ pci_io_base()

uint16_t pci_io_base | ( | uint32_t | field | ) |

## ◆ pci_mem_base()

uint32_t pci_mem_base | ( | uint32_t | field | ) |

## ◆ pci_not_found()

bool pci_not_found | ( | pci_dev_t | device | ) |

## ◆ pci_reach_end()

uint32_t pci_reach_end | ( | pci_dev_t | dev | ) |

## ◆ pci_read()

uint32_t pci_read | ( | pci_dev_t | dev,
|  | uint32_t | field
| ) |  |

## ◆ pci_scan_bus()

pci_dev_t pci_scan_bus | ( | uint16_t | vendor_id,
|  | uint16_t | device_id,
|  | uint32_t | bus,
|  | int | device_type
| ) |  |

## ◆ pci_scan_device()

pci_dev_t pci_scan_device | ( | uint16_t | vendor_id,
|  | uint16_t | device_id,
|  | uint32_t | bus,
|  | uint32_t | device,
|  | int | device_type
| ) |  |

## ◆ pci_scan_function()

pci_dev_t pci_scan_function | ( | uint16_t | vendor_id,
|  | uint16_t | device_id,
|  | uint32_t | bus,
|  | uint32_t | device,
|  | uint32_t | function,
|  | int | device_type
| ) |  |

## ◆ pci_write()

void pci_write | ( | pci_dev_t | dev,
|  | uint32_t | field,
|  | uint32_t | value
| ) |  |

## Variable Documentation

## ◆ dev_zero

pci_dev_t dev_zero
| extern