/// Add with Carry.
ADC
/// Add with Carry and updates the flags.
ADCS
/// Add.
ADD
/// Add and updates the flags.
ADDS
/// Add Wide (12-bit).
ADDW
/// Form PC-relative Address.
ADR
/// AES single round decryption.
AESD
/// AES single round encryption.
AESE
/// AES inverse mix columns.
AESIMC
/// AES mix columns.
AESMC
/// Bitwise AND.
AND
/// Bitwise AND and updates the flags.
ANDS
/// Arithmetic Shift Right.
ASR
/// Arithmetic Shift Right and update the flags.
ASRS
/// Branch or Conditional branch.
B
/// Bit Field Clear.
BFC
/// Bit Field Insert.
BFI
/// Bitwise Bit Clear.
BIC
/// Bitwise Bit Clear and updates the flags.
BICS
/// Breakpoint.
BKPT
/// Branch with Link.
BL
/// Branch with Link and Exchange.
BLX
/// Branch and Exchange.
BX
/// Branch and Exchange Jazelle.
BXJ
/// Compare and Branch on Nonzero.
CBNZ
/// Compare and Branch on Zero.
CBZ
/// Coprocessor data operations.
CDP
/// Coprocessor data operations.
CDP2
/// Clear-Exclusive.
CLREX
/// Count Leading Zeros.
CLZ
/// Compare Negative.
CMN
/// Compare.
CMP
/// Change Processor State.
CPS
/// Change Processor State, Interrupt Disasble.
CPSID
/// Change Processor State, Interrupt Enasble.
CPSIE
/// CRC-32 sum from byte.
CRC32B
/// CRC-32C sum from byte.
CRC32CB
/// CRC-32C sum from halfword.
CRC32CH
/// CRC-32C sum from word.
CRC32CW
/// CRC-32 sum from halfword.
CRC32H
/// CRC-32 sum from word.
CRC32W
/// Consumption of Speculative Data Barrier.
CSDB
/// Debug hint.
DBG
/// Debug switch to Exception level 1.
DCPS1
/// Debug switch to Exception level 2.
DCPS2
/// Debug switch to Exception level 3.
DCPS3
/// Data Memory Barrier.
DMB
/// Data Synchronization Barrier.
DSB
/// Enter ThumbEE state.
ENTERX
/// Bitwise Exclusive OR.
EOR
/// Bitwise Exclusive OR and update the flags.
EORS
/// Exception Return.
ERET
/// Error Synchronization Barrier.
ESB
/// Loads multiple SIMD&FP registers.
FLDMDBX
/// Loads multiple SIMD&FP registers.
FLDMIAX
/// Stores multiple SIMD&FP registers .
FSTMDBX
/// Stores multiple SIMD&FP registers .
FSTMIAX
/// Halt Instruction.
HLT
/// Hypervisor Call.
HVC
/// Instruction Synchronization Barrier.
ISB
/// If-Then.
IT
/// If-Then.
ITE
/// If-Then.
ITEE
/// If-Then.
ITEEE
/// If-Then.
ITEET
/// If-Then.
ITET
/// If-Then.
ITETE
/// If-Then.
ITETT
/// If-Then.
ITT
/// If-Then.
ITTE
/// If-Then.
ITTEE
/// If-Then.
ITTET
/// If-Then.
ITTT
/// If-Then.
ITTTE
/// If-Then.
ITTTT
/// Load-Acquire Word.
LDA
/// Load-Acquire Byte.
LDAB
/// Load-Acquire Exclusive Word.
LDAEX
/// Load-Acquire Exclusive Byte.
LDAEXB
/// Load-Acquire Exclusive Double.
LDAEXD
/// Load-Acquire Exclusive Halfword.
LDAEXH
/// Load-Acquire Halfword.
LDAH
/// Load Coprocessor.
LDC
/// Load Coprocessor.
LDC2
/// Load Coprocessor.
LDC2L
/// Load Coprocessor.
LDCL
/// Load Multiple.
LDM
/// Load Multiple. Decrement After.
LDMDA
/// Load Multiple. Decrement Before.
LDMDB
/// Load Multiple. Increment After.
LDMIA
/// Load Multiple. Increment Before.
LDMIB
/// Load Register.
LDR
/// Load Register Byte.
LDRB
/// Load Register Byte Unprivileged.
LDRBT
/// Load Register Dual.
LDRD
/// Load Register Exclusive.
LDREX
/// Load Register Exclusive Byte.
LDREXB
/// Load Register Exclusive Doubleword.
LDREXD
/// Load Register Exclusive Halfword.
LDREXH
/// Load Register Halfword.
LDRH
/// Load Register Halfword Unprivileged.
LDRHT
/// Load Register Signed Byte.
LDRSB
/// Load Register Signed Byte Unprivileged.
LDRSBT
/// Load Register Signed Halfword.
LDRSH
/// Load Register Signed Halfword Unprivileged.
LDRSHT
/// Load Register Unprivileged.
LDRT
/// Exit ThumbEE state.
LEAVEX
/// Logical Shift Left.
LSL
/// Logical Shift Left and OutSide IT block.
LSLS
/// Logical Shift Right.
LSR
/// Logical Shift Right and OutSide IT block.
LSRS
/// Move to Coprocessor from ARM core register (T1/A1).
MCR
/// Move to Coprocessor from ARM core register (T2/A2).
MCR2
/// Move to Coprocessor from two ARM core registers (T1/A1).
MCRR
/// Move to Coprocessor from two ARM core registers (T2/A2).
MCRR2
/// Multiply Accumulate.
MLA
/// Multiply Accumulate and update the flags.
MLAS
/// Multiply and Subtract.
MLS
/// Move.
MOV
/// Move and update the flags.
MOVS
/// Move Top (16-bit).
MOVT
/// Move (Only encoding T3 or A2 permitted).
MOVW
/// Move to ARM core register from Coprocessor (T1/A1).
MRC
/// Move to ARM core register from Coprocessor (T2/A2).
MRC2
/// Move to two ARM core registers from Coprocessor (T1/A1).
MRRC
/// Move to two ARM core registers from Coprocessor (T2/A2).
MRRC2
/// Move from Banked or Special register.
MRS
/// Move to Special register, Application level.
MSR
/// Multiply.
MUL
/// Multiply and update the flags.
MULS
/// Bitwise NOT.
MVN
/// Bitwise NOT and update the flags.
MVNS
/// No Operation.
NOP
/// Bitwise OR NOT.
ORN
/// Bitwise OR NOT and update the flags.
ORNS
/// Bitwise OR.
ORR
/// Bitwise OR and update the flags.
ORRS
/// Pack Halfword (tbform == FALSE).
PKHBT
/// Pack Halfword (tbform == TRUE).
PKHTB
/// Preload Data.
PLD
/// Preload Data (W = 1 in Thumb or R = 0 in ARM).
PLDW
/// Preload Instruction.
PLI
/// Pop Multiple Registers.
POP
/// Physical Speculative Store Bypass Barrier.
PSSBB
/// Push Multiple Registers.
PUSH
/// Saturating Add.
QADD
/// Saturating Add 16-bit.
QADD16
/// Saturating Add 8-bit.
QADD8
/// Saturating Add and Subtract with Exchange, 16-bit.
QASX
/// Saturating Double and Add.
QDADD
/// Saturating Double and Subtract.
QDSUB
/// Saturating Subtract and Add with Exchange, 16-bit.
QSAX
/// Saturating Subtract.
QSUB
/// Saturating Subtract 16-bit.
QSUB16
/// Saturating Add 8-bit.
QSUB8
/// Reverse Bits.
RBIT
/// Byte-Reverse Word.
REV
/// Byte-Reverse Packed Halfword.
REV16
/// Byte-Reverse Signed Halfword.
REVSH
/// Return From Exception.
RFE
/// Return From Exception. Decrement After.
RFEDA
/// Return From Exception. Decrement Before.
RFEDB
/// Return From Exception. Increment After.
RFEIA
/// Return From Exception. Increment Before.
RFEIB
/// Rotate Right.
ROR
/// Rotate Right and update the flags.
RORS
/// Rotate Right with Extend.
RRX
/// Rotate Right with Extend and update the flags.
RRXS
/// Reverse Subtract.
RSB
/// Reverse Subtract and update the flags.
RSBS
/// Reverse Subtract with Carry.
RSC
/// Reverse Subtract with Carry and update the flags.
RSCS
/// Add 16-bit.
SADD16
/// Add 8-bit.
SADD8
/// Add and Subtract with Exchange, 16-bit.
SASX
/// Speculation Barrier.
SB
/// Subtract with Carry.
SBC
/// Subtract with Carry and update the flags.
SBCS
/// Signed Bit Field Extract.
SBFX
/// Signed Divide.
SDIV
/// Select Bytes.
SEL
/// Set Endianness.
SETEND
/// Set Privileged Access Never.
SETPAN
/// Send Event.
SEV
/// Send Event Local is a hint instruction.
SEVL
/// SHA1 hash update (choose).
SHA1C
/// SHA1 fixed rotate.
SHA1H
/// SHA1 hash update (majority).
SHA1M
/// SHA1 hash update (parity).
SHA1P
/// SHA1 schedule update 0.
SHA1SU0
/// SHA1 schedule update 1.
SHA1SU1
/// SHA256 schedule update 0.
SHA256H
/// SHA256 hash update (part 2).
SHA256H2
/// SHA256 schedule update 0.
SHA256SU0
/// SHA256 schedule update 1.
SHA256SU1
/// Halving Add 16-bit.
SHADD16
/// Halving Add 8-bit.
SHADD8
/// Halving Add and Subtract with Exchange, 16-bit.
SHASX
/// Halving Subtract and Add with Exchange, 16-bit.
SHSAX
/// Halving Subtract 16-bit.
SHSUB16
/// Halving Subtract 8-bit.
SHSUB8
/// Secure Monitor Call.
SMC
/// Signed Multiply Accumulate (Halfwords).
SMLABB
/// Signed Multiply Accumulate (Halfwords).
SMLABT
/// Signed Multiply Accumulate Dual.
SMLAD
/// Signed Multiply Accumulate Dual (M = 1).
SMLADX
/// Signed Multiply Accumulate Long.
SMLAL
/// Signed Multiply Accumulate Long (Halfwords).
SMLALBB
/// Signed Multiply Accumulate Long (Halfwords).
SMLALBT
/// Signed Multiply Accumulate Long Dual.
SMLALD
/// Signed Multiply Accumulate Long Dual (M = 1).
SMLALDX
/// Signed Multiply Accumulate Long and update the flags.
SMLALS
/// Signed Multiply Accumulate Long.
SMLALTB
/// Signed Multiply Accumulate Long (Halfwords).
SMLALTT
/// Signed Multiply Accumulate (Halfwords).
SMLATB
/// Signed Multiply Accumulate (Halfwords).
SMLATT
/// Signed Multiply Accumulate (Word by halfword).
SMLAWB
/// Signed Multiply Accumulate.
SMLAWT
/// Signed Multiply Subtract Dual.
SMLSD
/// Signed Multiply Subtract Dual (M = 1).
SMLSDX
/// Signed Multiply Subtract Long Dual.
SMLSLD
/// Signed Multiply Subtract Long Dual (M = 1).
SMLSLDX
/// Signed Most Significant Word Multiply Accumulate.
SMMLA
/// Signed Most Significant Word Multiply Accumulate (R = 1).
SMMLAR
/// Signed Most Significant Word Multiply Subtract.
SMMLS
/// Signed Most Significant Word Multiply Subtract (R = 1).
SMMLSR
/// Signed Most Significant Word Multiply.
SMMUL
/// Signed Most Significant Word Multiply (R = 1).
SMMULR
/// Signed Dual Multiply Add.
SMUAD
/// Signed Dual Multiply Add (M = 1).
SMUADX
/// Signed Multiply (Halfwords).
SMULBB
/// Signed Multiply (Halfwords).
SMULBT
/// Signed Multiply Long.
SMULL
/// Signed Multiply Long and update the flags.
SMULLS
/// Signed Multiply Long (Halfwords).
SMULTB
/// Signed Multiply Long (Halfwords).
SMULTT
/// Signed Multiply Accumulate (Word by halfword).
SMULWB
/// Signed Multiply Accumulate (Word by halfword).
SMULWT
/// Signed Dual Multiply Subtract.
SMUSD
/// Signed Dual Multiply Subtract (M = 1).
SMUSDX
/// Store Return State.
SRS
/// Store Return State. Decrement After.
SRSDA
/// Store Return State. Decrement Before.
SRSDB
/// Store Return State. Increment After.
SRSIA
/// Store Return State. Increment Before.
SRSIB
/// Signed Saturate.
SSAT
/// Signed Saturate, two 16-bit.
SSAT16
/// Subtract and Add with Exchange, 16-bit.
SSAX
/// Speculative Store Bypass Barrier.
SSBB
/// Subtract 16-bit.
SSUB16
/// Subtract 8-bit.
SSUB8
/// Store Coprocessor (T1/A1).
STC
/// Store Coprocessor (T2/A2).
STC2
/// Store Coprocessor (T2/A2) (D == 1).
STC2L
/// Store Coprocessor (T1/A1) (D == 1).
STCL
/// Store-Release Word.
STL
/// Store-Release Byte.
STLB
/// Store-Release Exclusive Word.
STLEX
/// Store-Release Exclusive Byte.
STLEXB
/// Store-Release Exclusive Doubleword.
STLEXD
/// Store-Release Exclusive Halfword.
STLEXH
/// Store-Release Halfword.
STLH
/// Store Multiple.
STM
/// Store Multiple. Decrement After.
STMDA
/// Store Multiple. Decrement Before.
STMDB
/// Store Multiple. Increment After.
STMEA
/// Store Multiple. Increment After.
STMIA
/// Store Multiple. Increment Before.
STMIB
/// Store Register.
STR
/// Store Register Byte.
STRB
/// Store Register Byte Unprivileged.
STRBT
/// Store Register Dual.
STRD
/// Store Register Exclusive.
STREX
/// Store Register Exclusive Byte.
STREXB
/// Store Register Exclusive Doubleword.
STREXD
/// Store Register Exclusive Halfword.
STREXH
/// Store Register Halfword.
STRH
/// Store Register Halfword Unprivileged.
STRHT
/// Store Register Unprivileged.
STRT
/// Subtract.
SUB
/// Subtract and update the flags.
SUBS
/// Subtract Wide.
SUBW
/// Supervisor Call.
SVC
/// Swap Word.
SWP
/// Swap Byte.
SWPB
/// Signed Extend and Add Byte.
SXTAB
/// Signed Extend and Add Byte 16.
SXTAB16
/// Signed Extend and Add Halfword.
SXTAH
/// Signed Extend Byte.
SXTB
/// Signed Extend Byte 16.
SXTB16
/// Signed Extend Halfword.
SXTH
/// Table Branch (byte offsets).
TBB
/// Table Branch (halfword offsets).
TBH
/// Test Equivalence.
TEQ
/// Trace Synchronization Barrier.
TSB
/// Test performs a bitwise AND operation.
TST
/// Add 16-bit.
UADD16
/// Add 8-bit.
UADD8
/// Add and Subtract with Exchange, 16-bit.
UASX
/// Unsigned Bit Field Extract.
UBFX
/// Permanently UNDEFINED.
UDF
/// Unsigned Divide.
UDIV
/// Halving Add 16-bit.
UHADD16
/// Halving Add 8-bit.
UHADD8
/// Halving Add and Subtract with Exchange, 16-bit.
UHASX
/// Halving Subtract and Add with Exchange, 16-bit.
UHSAX
/// Halving Subtract 16-bit.
UHSUB16
/// Halving Add 8-bit.
UHSUB8
/// Unsigned Multiply Accumulate Accumulate Long.
UMAAL
/// Unsigned Multiply Accumulate Long.
UMLAL
/// Unsigned Multiply Accumulate Long and update the flags.
UMLALS
/// Unsigned Multiply Long.
UMULL
/// Unsigned Multiply Long and update the flags.
UMULLS
/// Saturating Add 16-bit.
UQADD16
/// Saturating Add 8-bit.
UQADD8
/// Saturating Add and Subtract with Exchange, 16-bit.
UQASX
/// Saturating Subtract and Add with Exchange, 16-bit.
UQSAX
/// Saturating Subtract 16-bit.
UQSUB16
/// Saturating Subtract 8-bit.
UQSUB8
/// Unsigned Sum of Absolute Differences.
USAD8
/// Unsigned Sum of Absolute Differences, Accumulate.
USADA8
/// Unsigned Saturate.
USAT
/// Unsigned Saturate, two 16-bit.
USAT16
/// Subtract and Add with Exchange, 16-bit.
USAX
/// Subtract 16-bit.
USUB16
/// Subtract 8-bit.
USUB8
/// Unsigned Extend and Add Byte.
UXTAB
/// Unsigned Extend and Add Byte 16.
UXTAB16
/// Unsigned Extend and Add Halfword.
UXTAH
/// Unsigned Extend Byte.
UXTB
/// Unsigned Extend Byte 16.
UXTB16
/// Unsigned Extend Halfword.
UXTH
/// Vector Absolute Difference and Accumulate.
VABA
/// Vector Absolute Difference and Accumulate (T2/A2).
VABAL
/// Vector Absolute Difference.
VABD
/// Vector Absolute Difference (T2/A2).
VABDL
/// Vector Absolute.
VABS
/// Vector Absolute Compare Greater or Less Than (or Equal).
VACGE
/// Vector Absolute Compare Greater or Less Than (or Equal).
VACGT
/// Vector Absolute Compare Greater or Less Than (or Equal).
VACLE
/// Vector Absolute Compare Greater or Less Than (or Equal).
VACLT
/// Vector Add.
VADD
/// Vector Add and Narrow, returning High Half.
VADDHN
/// Vector Add Long.
VADDL
/// Vector Add Wide.
VADDW
/// Vector Bitwise AND.
VAND
/// Vector Bitwise Bit Clear, AND complement.
VBIC
/// Vector Bitwise Select. Bitwise Insert if False, encoded as op = 0b11.
VBIF
/// Vector Bitwise Select. Bitwise Insert if True, encoded as op = 0b10.
VBIT
/// Vector Bitwise Select. Bitwise Select, encoded as op = 0b01.
VBSL
/// Vector Complex Add.
VCADD
/// Vector Compare Equal.
VCEQ
/// Vector Compare Greater Than or Equal.
VCGE
/// Vector Compare Greater Than.
VCGT
/// Vector Compare Less Than or Equal to Zero.
VCLE
/// Vector Count Leading Sign Bits.
VCLS
/// Vector Compare Less Than Zero.
VCLT
/// Vector Count Leading Zeros.
VCLZ
/// Vector Complex Multiply Accumulate.
VCMLA
/// Vector Compare. (Encoded as E = 0).
VCMP
/// Vector Compare. (Encoded as E = 1).
VCMPE
/// Vector Count.
VCNT
/// Vector Convert.
VCVT
/// Convert floating-point to integer with Round to Nearest with Ties to Away.
VCVTA
/// Convert between half-precision and single-precision.
VCVTB
/// Convert floating-point to integer with Round towards Minus Infinity.
VCVTM
/// Convert floating-point to integer with Round to Nearest.
VCVTN
/// Convert floating-point to integer with Round towards Plus Infinity.
VCVTP
/// Vector Convert floating-point to integer.
VCVTR
/// Convert between half-precision and single-precision.
VCVTT
/// Vector Divide.
VDIV
/// BFloat16 floating-point (BF16) dot product (vector).
VDOT
/// Vector Duplicate.
VDUP
/// Vector Bitwise Exclusive OR.
VEOR
/// Vector Extract.
VEXT
/// Vector Fused Multiply Accumulate.
VFMA
/// BFloat16 floating-point widening multiply-add.
VFMAB
/// Vector Floating-point Multiply-Add Long to accumulator.
VFMAL
/// BFloat16 floating-point widening multiply-add.
VFMAT
/// Vector Fused Multiply Subtract.
VFMS
/// Vector Floating-Point Multiply-Subtract Long.
VFMSL
/// Vector Fused Negate Multiply Accumulate.
VFNMA
/// Vector Fused Negate Multiply Subtract.
VFNMS
/// Vector Halving Add.
VHADD
/// Vector Halving Subtract.
VHSUB
/// Vector move Insertion.
VINS
/// FP Javascript convert to signed fixed-point, rounding toward zero.
VJCVT
/// Vector Load. (multiple single elements).
VLD1
/// Vector Load. (multiple 2-element structures).
VLD2
/// Vector Load. (multiple 3-element structures).
VLD3
/// Vector Load. (multiple 4-element structures).
VLD4
/// Vector Load Multiple.
VLDM
/// Vector Load Multiple. Decrement Before.
VLDMDB
/// Vector Load Multiple. Increment After.
VLDMIA
/// Vector Load Register.
VLDR
/// Vector Maximum.
VMAX
/// Floating-point Maximum Number.
VMAXNM
/// Vector Minimum.
VMIN
/// Floating-point Minimum Number.
VMINNM
/// Vector Multiply Accumulate.
VMLA
/// Vector Multiply Accumulate (T2/A2).
VMLAL
/// Vector Multiply Subtract.
VMLS
/// Vector Multiply Subtract (T2/A2).
VMLSL
/// BFloat16 floating-point matrix multiply-accumulate.
VMMLA
/// Vector Move.
VMOV
/// Vector Move Long.
VMOVL
/// Vector Move and Narrow.
VMOVN
/// Vector Move extraction.
VMOVX
/// Move to ARM core register from Floating-point Special register.
VMRS
/// Move to Floating-point Special register from ARM core register.
VMSR
/// Vector Multiply.
VMUL
/// Vector Multiply Long.
VMULL
/// Vector Bitwise NOT.
VMVN
/// Vector Negate.
VNEG
/// Vector Negate Multiply Accumulate or Subtract.
VNMLA
/// Vector Negate Multiply Accumulate or Subtract.
VNMLS
/// Vector Negate Multiply Accumulate or Subtract.
VNMUL
/// Vector Bitwise OR NOT.
VORN
/// Vector Bitwise OR, if source registers differ.
VORR
/// Vector Pairwise Add and Accumulate Long.
VPADAL
/// Vector Pairwise Add.
VPADD
/// Vector Pairwise Add Long.
VPADDL
/// Vector Pairwise Maximum.
VPMAX
/// Vector Pairwise Minimum.
VPMIN
/// Vector Pop Registers.
VPOP
/// Vector Push Registers.
VPUSH
/// Vector Saturating Absolute.
VQABS
/// Vector Saturating Add.
VQADD
/// Vector Saturating Doubling Multiply Accumulate Long.
VQDMLAL
/// Vector Saturating Doubling Multiply Subtract Long.
VQDMLSL
/// Vector Saturating Doubling Multiply returning High Half.
VQDMULH
/// Vector Saturating Doubling Multiply Long.
VQDMULL
/// Vector Saturating Move and Unsigned Narrow (op <> 0b01).
VQMOVN
/// Vector Saturating Move and Unsigned Narrow (op = 0b01).
VQMOVUN
/// Vector Saturating Negate.
VQNEG
/// Vector Saturating Rounding Doubling Mul Accumulate Returning High Half.
VQRDMLAH
/// Vector Saturating Rounding Doubling Multiply Subtract Returning High Half.
VQRDMLSH
/// Vector Saturating Rounding Doubling Multiply returning High Half.
VQRDMULH
/// Vector Saturating Rounding Shift Left.
VQRSHL
/// Vector Saturating Shift Right, Rounded Unsigned Narrow.
VQRSHRN
/// Vector Saturating Shift Right, Rounded Unsigned Narrow.
VQRSHRUN
/// Vector Saturating Shift Left.
VQSHL
/// Vector Saturating Shift Left.
VQSHLU
/// Vector Saturating Shift Right, Narrow.
VQSHRN
/// Vector Saturating Shift Right, Narrow.
VQSHRUN
/// Vector Saturating Subtract.
VQSUB
/// Vector Rounding Add and Narrow, returning High Half.
VRADDHN
/// Vector Reciprocal Estimate.
VRECPE
/// Vector Reciprocal Step.
VRECPS
/// Vector Reverse in halfwords.
VREV16
/// Vector Reverse in words.
VREV32
/// Vector Reverse in doublewords.
VREV64
/// Vector Rounding Halving Add.
VRHADD
/// Vector Round floating-point to integer towards Nearest with Ties to Away.
VRINTA
/// Vector Round floating-point to integer towards Minus Infinity.
VRINTM
/// Vector Round floating-point to integer to Nearest.
VRINTN
/// Vector Round floating-point to integer towards Plus Infinity.
VRINTP
/// Vector Round floating-point to integer rounds.
VRINTR
/// Vector round floating-point to integer to nearest signaling inexactness.
VRINTX
/// Vector round floating-point to integer towards Zero.
VRINTZ
/// Vector Rounding Shift Left.
VRSHL
/// Vector Rounding Shift Right.
VRSHR
/// Vector Rounding Shift Right Narrow.
VRSHRN
/// Vector Reciprocal Square Root Estimate.
VRSQRTE
/// Vector Reciprocal Square Root Step.
VRSQRTS
/// Vector Rounding Shift Right and Accumulate.
VRSRA
/// Vector Rounding Subtract and Narrow, returning High Half.
VRSUBHN
/// Dot Product vector form with signed integers.
VSDOT
/// Floating-point conditional select.
VSELEQ
/// Floating-point conditional select.
VSELGE
/// Floating-point conditional select.
VSELGT
/// Floating-point conditional select.
VSELVS
/// Vector Shift Left.
VSHL
/// Vector Shift Left Long.
VSHLL
/// Vector Shift Right.
VSHR
/// Vector Shift Right Narrow.
VSHRN
/// Vector Shift Left and Insert.
VSLI
/// The widening integer matrix multiply-accumulate instruction.
VSMMLA
/// Vector Square Root.
VSQRT
/// Vector Shift Right and Accumulate.
VSRA
/// Vector Shift Right and Insert.
VSRI
/// Vector Store. (multiple single elements).
VST1
/// Vector Store. (multiple 2-element structures).
VST2
/// Vector Store. (multiple 3-element structures).
VST3
/// Vector Store. (multiple 4-element structures).
VST4
/// Vector Store Multiple.
VSTM
/// Vector Store Multiple. Decrement Before.
VSTMDB
/// Vector Store Multiple. Increment After.
VSTMIA
/// Vector Store Register.
VSTR
/// Vector Subtract.
VSUB
/// Vector Subtract and Narrow, returning High Half.
VSUBHN
/// Vector Subtract Long.
VSUBL
/// Vector Subtract Wide.
VSUBW
/// Dot Product index form with signed and unsigned integers.
VSUDOT
/// Vector Swap.
VSWP
/// Vector Table Lookup.
VTBL
/// Vector Table Extension.
VTBX
/// Vector Transpose.
VTRN
/// Vector Test Bits.
VTST
/// Dot Product index form with unsigned integers.
VUDOT
/// Widening 8-bit unsigned int matrix multiply-accumulate into 2x2 matrix.
VUMMLA
/// Dot Product index form with unsigned and signed integers.
VUSDOT
/// Widening 8-bit mixed sign int matrix multiply-accumulate into 2x2 matrix.
VUSMMLA
/// Vector Unzip.
VUZP
/// Vector Zip.
VZIP
/// Wait For Event hint.
WFE
/// Wait For Interrupt hint.
WFI
/// Yield hint.
YIELD
/// Invalid Opcode.
InvalidOP
